|
-
- #if defined ( __ICCARM__ )
- #pragma system_include
- #endif
-
- #ifdef __cplusplus
- extern "C" {
- #endif
-
- #ifndef __CORE_CM4_H_GENERIC
- #define __CORE_CM4_H_GENERIC
-
-
-
-
-
-
-
-
- #define __CM4_CMSIS_VERSION_MAIN (0x03)
- #define __CM4_CMSIS_VERSION_SUB (0x01)
- #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
- __CM4_CMSIS_VERSION_SUB )
-
- #define __CORTEX_M (0x04)
-
-
- #if defined ( __CC_ARM )
- #define __ASM __asm
- #define __INLINE __inline
- #define __STATIC_INLINE static __inline
-
- #elif defined ( __ICCARM__ )
- #define __ASM __asm
- #define __INLINE inline
- #define __STATIC_INLINE static inline
-
- #elif defined ( __TMS470__ )
- #define __ASM __asm
- #define __STATIC_INLINE static inline
-
- #elif defined ( __GNUC__ )
- #define __ASM __asm
- #define __INLINE inline
- #define __STATIC_INLINE static inline
-
- #elif defined ( __TASKING__ )
- #define __ASM __asm
- #define __INLINE inline
- #define __STATIC_INLINE static inline
-
- #endif
-
-
- #if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
- #elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
- #elif defined ( __TMS470__ )
- #if defined __TI_VFP_SUPPORT__
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
- #elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
- #elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
- #endif
-
- #include <stdint.h> /* standard types definitions */
- #include <core_cmInstr.h> /* Core Instruction Access */
- #include <core_cmFunc.h> /* Core Function Access */
- #include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
-
- #endif
-
- #ifndef __CMSIS_GENERIC
-
- #ifndef __CORE_CM4_H_DEPENDANT
- #define __CORE_CM4_H_DEPENDANT
-
-
- #if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM4_REV
- #define __CM4_REV 0x0000
- #warning "__CM4_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __FPU_PRESENT
- #define __FPU_PRESENT 0
- #warning "__FPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 4
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
- #endif
-
-
-
- #ifdef __cplusplus
- #define __I volatile
- #else
- #define __I volatile const
- #endif
- #define __O volatile
- #define __IO volatile
-
-
-
-
-
-
-
-
-
-
-
- typedef union
- {
- struct
- {
- #if (__CORTEX_M != 0x04)
- uint32_t _reserved0:27;
- #else
- uint32_t _reserved0:16;
- uint32_t GE:4;
- uint32_t _reserved1:7;
- #endif
- uint32_t Q:1;
- uint32_t V:1;
- uint32_t C:1;
- uint32_t Z:1;
- uint32_t N:1;
- } b;
- uint32_t w;
- } APSR_Type;
-
-
-
- typedef union
- {
- struct
- {
- uint32_t ISR:9;
- uint32_t _reserved0:23;
- } b;
- uint32_t w;
- } IPSR_Type;
-
-
-
- typedef union
- {
- struct
- {
- uint32_t ISR:9;
- #if (__CORTEX_M != 0x04)
- uint32_t _reserved0:15;
- #else
- uint32_t _reserved0:7;
- uint32_t GE:4;
- uint32_t _reserved1:4;
- #endif
- uint32_t T:1;
- uint32_t IT:2;
- uint32_t Q:1;
- uint32_t V:1;
- uint32_t C:1;
- uint32_t Z:1;
- uint32_t N:1;
- } b;
- uint32_t w;
- } xPSR_Type;
-
-
-
- typedef union
- {
- struct
- {
- uint32_t nPRIV:1;
- uint32_t SPSEL:1;
- uint32_t FPCA:1;
- uint32_t _reserved0:29;
- } b;
- uint32_t w;
- } CONTROL_Type;
-
-
-
-
-
-
-
- typedef struct
- {
- __IO uint32_t ISER[8];
- uint32_t RESERVED0[24];
- __IO uint32_t ICER[8];
- uint32_t RSERVED1[24];
- __IO uint32_t ISPR[8];
- uint32_t RESERVED2[24];
- __IO uint32_t ICPR[8];
- uint32_t RESERVED3[24];
- __IO uint32_t IABR[8];
- uint32_t RESERVED4[56];
- __IO uint8_t IP[240];
- uint32_t RESERVED5[644];
- __O uint32_t STIR;
- } NVIC_Type;
-
-
- #define NVIC_STIR_INTID_Pos 0
- #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos)
-
-
-
-
-
-
-
- typedef struct
- {
- __I uint32_t CPUID;
- __IO uint32_t ICSR;
- __IO uint32_t VTOR;
- __IO uint32_t AIRCR;
- __IO uint32_t SCR;
- __IO uint32_t CCR;
- __IO uint8_t SHP[12];
- __IO uint32_t SHCSR;
- __IO uint32_t CFSR;
- __IO uint32_t HFSR;
- __IO uint32_t DFSR;
- __IO uint32_t MMFAR;
- __IO uint32_t BFAR;
- __IO uint32_t AFSR;
- __I uint32_t PFR[2];
- __I uint32_t DFR;
- __I uint32_t ADR;
- __I uint32_t MMFR[4];
- __I uint32_t ISAR[5];
- uint32_t RESERVED0[5];
- __IO uint32_t CPACR;
- } SCB_Type;
-
-
- #define SCB_CPUID_IMPLEMENTER_Pos 24
- #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
-
- #define SCB_CPUID_VARIANT_Pos 20
- #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
-
- #define SCB_CPUID_ARCHITECTURE_Pos 16
- #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
-
- #define SCB_CPUID_PARTNO_Pos 4
- #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
-
- #define SCB_CPUID_REVISION_Pos 0
- #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos)
-
-
- #define SCB_ICSR_NMIPENDSET_Pos 31
- #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
-
- #define SCB_ICSR_PENDSVSET_Pos 28
- #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
-
- #define SCB_ICSR_PENDSVCLR_Pos 27
- #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
-
- #define SCB_ICSR_PENDSTSET_Pos 26
- #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
-
- #define SCB_ICSR_PENDSTCLR_Pos 25
- #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
-
- #define SCB_ICSR_ISRPREEMPT_Pos 23
- #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
-
- #define SCB_ICSR_ISRPENDING_Pos 22
- #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
-
- #define SCB_ICSR_VECTPENDING_Pos 12
- #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
-
- #define SCB_ICSR_RETTOBASE_Pos 11
- #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
-
- #define SCB_ICSR_VECTACTIVE_Pos 0
- #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)
-
-
- #define SCB_VTOR_TBLOFF_Pos 7
- #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
-
-
- #define SCB_AIRCR_VECTKEY_Pos 16
- #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
-
- #define SCB_AIRCR_VECTKEYSTAT_Pos 16
- #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
-
- #define SCB_AIRCR_ENDIANESS_Pos 15
- #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
-
- #define SCB_AIRCR_PRIGROUP_Pos 8
- #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
-
- #define SCB_AIRCR_SYSRESETREQ_Pos 2
- #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
-
- #define SCB_AIRCR_VECTCLRACTIVE_Pos 1
- #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
-
- #define SCB_AIRCR_VECTRESET_Pos 0
- #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos)
-
-
- #define SCB_SCR_SEVONPEND_Pos 4
- #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
-
- #define SCB_SCR_SLEEPDEEP_Pos 2
- #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
-
- #define SCB_SCR_SLEEPONEXIT_Pos 1
- #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
-
-
- #define SCB_CCR_STKALIGN_Pos 9
- #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
-
- #define SCB_CCR_BFHFNMIGN_Pos 8
- #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
-
- #define SCB_CCR_DIV_0_TRP_Pos 4
- #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
-
- #define SCB_CCR_UNALIGN_TRP_Pos 3
- #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
-
- #define SCB_CCR_USERSETMPEND_Pos 1
- #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
-
- #define SCB_CCR_NONBASETHRDENA_Pos 0
- #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos)
-
-
- #define SCB_SHCSR_USGFAULTENA_Pos 18
- #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
-
- #define SCB_SHCSR_BUSFAULTENA_Pos 17
- #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
-
- #define SCB_SHCSR_MEMFAULTENA_Pos 16
- #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
-
- #define SCB_SHCSR_SVCALLPENDED_Pos 15
- #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
-
- #define SCB_SHCSR_BUSFAULTPENDED_Pos 14
- #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
-
- #define SCB_SHCSR_MEMFAULTPENDED_Pos 13
- #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
-
- #define SCB_SHCSR_USGFAULTPENDED_Pos 12
- #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
-
- #define SCB_SHCSR_SYSTICKACT_Pos 11
- #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
-
- #define SCB_SHCSR_PENDSVACT_Pos 10
- #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
-
- #define SCB_SHCSR_MONITORACT_Pos 8
- #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
-
- #define SCB_SHCSR_SVCALLACT_Pos 7
- #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
-
- #define SCB_SHCSR_USGFAULTACT_Pos 3
- #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
-
- #define SCB_SHCSR_BUSFAULTACT_Pos 1
- #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
-
- #define SCB_SHCSR_MEMFAULTACT_Pos 0
- #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos)
-
-
- #define SCB_CFSR_USGFAULTSR_Pos 16
- #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
-
- #define SCB_CFSR_BUSFAULTSR_Pos 8
- #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
-
- #define SCB_CFSR_MEMFAULTSR_Pos 0
- #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)
-
-
- #define SCB_HFSR_DEBUGEVT_Pos 31
- #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
-
- #define SCB_HFSR_FORCED_Pos 30
- #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
-
- #define SCB_HFSR_VECTTBL_Pos 1
- #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
-
-
- #define SCB_DFSR_EXTERNAL_Pos 4
- #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
-
- #define SCB_DFSR_VCATCH_Pos 3
- #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
-
- #define SCB_DFSR_DWTTRAP_Pos 2
- #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
-
- #define SCB_DFSR_BKPT_Pos 1
- #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
-
- #define SCB_DFSR_HALTED_Pos 0
- #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos)
-
-
-
-
-
-
-
- typedef struct
- {
- uint32_t RESERVED0[1];
- __I uint32_t ICTR;
- __IO uint32_t ACTLR;
- } SCnSCB_Type;
-
-
- #define SCnSCB_ICTR_INTLINESNUM_Pos 0
- #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)
-
-
- #define SCnSCB_ACTLR_DISOOFP_Pos 9
- #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos)
-
- #define SCnSCB_ACTLR_DISFPCA_Pos 8
- #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos)
-
- #define SCnSCB_ACTLR_DISFOLD_Pos 2
- #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)
-
- #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1
- #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)
-
- #define SCnSCB_ACTLR_DISMCYCINT_Pos 0
- #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)
-
-
-
-
-
-
-
- typedef struct
- {
- __IO uint32_t CTRL;
- __IO uint32_t LOAD;
- __IO uint32_t VAL;
- __I uint32_t CALIB;
- } SysTick_Type;
-
-
- #define SysTick_CTRL_COUNTFLAG_Pos 16
- #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
-
- #define SysTick_CTRL_CLKSOURCE_Pos 2
- #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
-
- #define SysTick_CTRL_TICKINT_Pos 1
- #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
-
- #define SysTick_CTRL_ENABLE_Pos 0
- #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos)
-
-
- #define SysTick_LOAD_RELOAD_Pos 0
- #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)
-
-
- #define SysTick_VAL_CURRENT_Pos 0
- #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)
-
-
- #define SysTick_CALIB_NOREF_Pos 31
- #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
-
- #define SysTick_CALIB_SKEW_Pos 30
- #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
-
- #define SysTick_CALIB_TENMS_Pos 0
- #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)
-
-
-
-
-
-
-
- typedef struct
- {
- __O union
- {
- __O uint8_t u8;
- __O uint16_t u16;
- __O uint32_t u32;
- } PORT [32];
- uint32_t RESERVED0[864];
- __IO uint32_t TER;
- uint32_t RESERVED1[15];
- __IO uint32_t TPR;
- uint32_t RESERVED2[15];
- __IO uint32_t TCR;
- uint32_t RESERVED3[29];
- __O uint32_t IWR;
- __I uint32_t IRR;
- __IO uint32_t IMCR;
- uint32_t RESERVED4[43];
- __O uint32_t LAR;
- __I uint32_t LSR;
- uint32_t RESERVED5[6];
- __I uint32_t PID4;
- __I uint32_t PID5;
- __I uint32_t PID6;
- __I uint32_t PID7;
- __I uint32_t PID0;
- __I uint32_t PID1;
- __I uint32_t PID2;
- __I uint32_t PID3;
- __I uint32_t CID0;
- __I uint32_t CID1;
- __I uint32_t CID2;
- __I uint32_t CID3;
- } ITM_Type;
-
-
- #define ITM_TPR_PRIVMASK_Pos 0
- #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos)
-
-
- #define ITM_TCR_BUSY_Pos 23
- #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
-
- #define ITM_TCR_TraceBusID_Pos 16
- #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)
-
- #define ITM_TCR_GTSFREQ_Pos 10
- #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
-
- #define ITM_TCR_TSPrescale_Pos 8
- #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)
-
- #define ITM_TCR_SWOENA_Pos 4
- #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
-
- #define ITM_TCR_DWTENA_Pos 3
- #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
-
- #define ITM_TCR_SYNCENA_Pos 2
- #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
-
- #define ITM_TCR_TSENA_Pos 1
- #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
-
- #define ITM_TCR_ITMENA_Pos 0
- #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos)
-
-
- #define ITM_IWR_ATVALIDM_Pos 0
- #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos)
-
-
- #define ITM_IRR_ATREADYM_Pos 0
- #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos)
-
-
- #define ITM_IMCR_INTEGRATION_Pos 0
- #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos)
-
-
- #define ITM_LSR_ByteAcc_Pos 2
- #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
-
- #define ITM_LSR_Access_Pos 1
- #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
-
- #define ITM_LSR_Present_Pos 0
- #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos)
-
-
-
-
-
-
-
- typedef struct
- {
- __IO uint32_t CTRL;
- __IO uint32_t CYCCNT;
- __IO uint32_t CPICNT;
- __IO uint32_t EXCCNT;
- __IO uint32_t SLEEPCNT;
- __IO uint32_t LSUCNT;
- __IO uint32_t FOLDCNT;
- __I uint32_t PCSR;
- __IO uint32_t COMP0;
- __IO uint32_t MASK0;
- __IO uint32_t FUNCTION0;
- uint32_t RESERVED0[1];
- __IO uint32_t COMP1;
- __IO uint32_t MASK1;
- __IO uint32_t FUNCTION1;
- uint32_t RESERVED1[1];
- __IO uint32_t COMP2;
- __IO uint32_t MASK2;
- __IO uint32_t FUNCTION2;
- uint32_t RESERVED2[1];
- __IO uint32_t COMP3;
- __IO uint32_t MASK3;
- __IO uint32_t FUNCTION3;
- } DWT_Type;
-
-
- #define DWT_CTRL_NUMCOMP_Pos 28
- #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
-
- #define DWT_CTRL_NOTRCPKT_Pos 27
- #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
-
- #define DWT_CTRL_NOEXTTRIG_Pos 26
- #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
-
- #define DWT_CTRL_NOCYCCNT_Pos 25
- #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
-
- #define DWT_CTRL_NOPRFCNT_Pos 24
- #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
-
- #define DWT_CTRL_CYCEVTENA_Pos 22
- #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
-
- #define DWT_CTRL_FOLDEVTENA_Pos 21
- #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
-
- #define DWT_CTRL_LSUEVTENA_Pos 20
- #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
-
- #define DWT_CTRL_SLEEPEVTENA_Pos 19
- #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
-
- #define DWT_CTRL_EXCEVTENA_Pos 18
- #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
-
- #define DWT_CTRL_CPIEVTENA_Pos 17
- #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
-
- #define DWT_CTRL_EXCTRCENA_Pos 16
- #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
-
- #define DWT_CTRL_PCSAMPLENA_Pos 12
- #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
-
- #define DWT_CTRL_SYNCTAP_Pos 10
- #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
-
- #define DWT_CTRL_CYCTAP_Pos 9
- #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
-
- #define DWT_CTRL_POSTINIT_Pos 5
- #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
-
- #define DWT_CTRL_POSTPRESET_Pos 1
- #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
-
- #define DWT_CTRL_CYCCNTENA_Pos 0
- #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos)
-
-
- #define DWT_CPICNT_CPICNT_Pos 0
- #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos)
-
-
- #define DWT_EXCCNT_EXCCNT_Pos 0
- #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)
-
-
- #define DWT_SLEEPCNT_SLEEPCNT_Pos 0
- #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)
-
-
- #define DWT_LSUCNT_LSUCNT_Pos 0
- #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)
-
-
- #define DWT_FOLDCNT_FOLDCNT_Pos 0
- #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)
-
-
- #define DWT_MASK_MASK_Pos 0
- #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos)
-
-
- #define DWT_FUNCTION_MATCHED_Pos 24
- #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
-
- #define DWT_FUNCTION_DATAVADDR1_Pos 16
- #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
-
- #define DWT_FUNCTION_DATAVADDR0_Pos 12
- #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
-
- #define DWT_FUNCTION_DATAVSIZE_Pos 10
- #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
-
- #define DWT_FUNCTION_LNK1ENA_Pos 9
- #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
-
- #define DWT_FUNCTION_DATAVMATCH_Pos 8
- #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
-
- #define DWT_FUNCTION_CYCMATCH_Pos 7
- #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
-
- #define DWT_FUNCTION_EMITRANGE_Pos 5
- #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
-
- #define DWT_FUNCTION_FUNCTION_Pos 0
- #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos)
-
-
-
-
-
-
-
- typedef struct
- {
- __IO uint32_t SSPSR;
- __IO uint32_t CSPSR;
- uint32_t RESERVED0[2];
- __IO uint32_t ACPR;
- uint32_t RESERVED1[55];
- __IO uint32_t SPPR;
- uint32_t RESERVED2[131];
- __I uint32_t FFSR;
- __IO uint32_t FFCR;
- __I uint32_t FSCR;
- uint32_t RESERVED3[759];
- __I uint32_t TRIGGER;
- __I uint32_t FIFO0;
- __I uint32_t ITATBCTR2;
- uint32_t RESERVED4[1];
- __I uint32_t ITATBCTR0;
- __I uint32_t FIFO1;
- __IO uint32_t ITCTRL;
- uint32_t RESERVED5[39];
- __IO uint32_t CLAIMSET;
- __IO uint32_t CLAIMCLR;
- uint32_t RESERVED7[8];
- __I uint32_t DEVID;
- __I uint32_t DEVTYPE;
- } TPI_Type;
-
-
- #define TPI_ACPR_PRESCALER_Pos 0
- #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)
-
-
- #define TPI_SPPR_TXMODE_Pos 0
- #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos)
-
-
- #define TPI_FFSR_FtNonStop_Pos 3
- #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
-
- #define TPI_FFSR_TCPresent_Pos 2
- #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
-
- #define TPI_FFSR_FtStopped_Pos 1
- #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
-
- #define TPI_FFSR_FlInProg_Pos 0
- #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos)
-
-
- #define TPI_FFCR_TrigIn_Pos 8
- #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
-
- #define TPI_FFCR_EnFCont_Pos 1
- #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
-
-
- #define TPI_TRIGGER_TRIGGER_Pos 0
- #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos)
-
-
- #define TPI_FIFO0_ITM_ATVALID_Pos 29
- #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
-
- #define TPI_FIFO0_ITM_bytecount_Pos 27
- #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
-
- #define TPI_FIFO0_ETM_ATVALID_Pos 26
- #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
-
- #define TPI_FIFO0_ETM_bytecount_Pos 24
- #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
-
- #define TPI_FIFO0_ETM2_Pos 16
- #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
-
- #define TPI_FIFO0_ETM1_Pos 8
- #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
-
- #define TPI_FIFO0_ETM0_Pos 0
- #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos)
-
-
- #define TPI_ITATBCTR2_ATREADY_Pos 0
- #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)
-
-
- #define TPI_FIFO1_ITM_ATVALID_Pos 29
- #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
-
- #define TPI_FIFO1_ITM_bytecount_Pos 27
- #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
-
- #define TPI_FIFO1_ETM_ATVALID_Pos 26
- #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
-
- #define TPI_FIFO1_ETM_bytecount_Pos 24
- #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
-
- #define TPI_FIFO1_ITM2_Pos 16
- #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
-
- #define TPI_FIFO1_ITM1_Pos 8
- #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
-
- #define TPI_FIFO1_ITM0_Pos 0
- #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos)
-
-
- #define TPI_ITATBCTR0_ATREADY_Pos 0
- #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)
-
-
- #define TPI_ITCTRL_Mode_Pos 0
- #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos)
-
-
- #define TPI_DEVID_NRZVALID_Pos 11
- #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
-
- #define TPI_DEVID_MANCVALID_Pos 10
- #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
-
- #define TPI_DEVID_PTINVALID_Pos 9
- #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
-
- #define TPI_DEVID_MinBufSz_Pos 6
- #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
-
- #define TPI_DEVID_AsynClkIn_Pos 5
- #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
-
- #define TPI_DEVID_NrTraceInput_Pos 0
- #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos)
-
-
- #define TPI_DEVTYPE_SubType_Pos 0
- #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos)
-
- #define TPI_DEVTYPE_MajorType_Pos 4
- #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
-
-
-
-
- #if (__MPU_PRESENT == 1)
-
-
-
- typedef struct
- {
- __I uint32_t TYPE;
- __IO uint32_t CTRL;
- __IO uint32_t RNR;
- __IO uint32_t RBAR;
- __IO uint32_t RASR;
- __IO uint32_t RBAR_A1;
- __IO uint32_t RASR_A1;
- __IO uint32_t RBAR_A2;
- __IO uint32_t RASR_A2;
- __IO uint32_t RBAR_A3;
- __IO uint32_t RASR_A3;
- } MPU_Type;
-
-
- #define MPU_TYPE_IREGION_Pos 16
- #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
-
- #define MPU_TYPE_DREGION_Pos 8
- #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
-
- #define MPU_TYPE_SEPARATE_Pos 0
- #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos)
-
-
- #define MPU_CTRL_PRIVDEFENA_Pos 2
- #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
-
- #define MPU_CTRL_HFNMIENA_Pos 1
- #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
-
- #define MPU_CTRL_ENABLE_Pos 0
- #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos)
-
-
- #define MPU_RNR_REGION_Pos 0
- #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos)
-
-
- #define MPU_RBAR_ADDR_Pos 5
- #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
-
- #define MPU_RBAR_VALID_Pos 4
- #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
-
- #define MPU_RBAR_REGION_Pos 0
- #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos)
-
-
- #define MPU_RASR_ATTRS_Pos 16
- #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
-
- #define MPU_RASR_XN_Pos 28
- #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
-
- #define MPU_RASR_AP_Pos 24
- #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
-
- #define MPU_RASR_TEX_Pos 19
- #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
-
- #define MPU_RASR_S_Pos 18
- #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
-
- #define MPU_RASR_C_Pos 17
- #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
-
- #define MPU_RASR_B_Pos 16
- #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
-
- #define MPU_RASR_SRD_Pos 8
- #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
-
- #define MPU_RASR_SIZE_Pos 1
- #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
-
- #define MPU_RASR_ENABLE_Pos 0
- #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos)
-
-
- #endif
-
-
- #if (__FPU_PRESENT == 1)
-
-
-
- typedef struct
- {
- uint32_t RESERVED0[1];
- __IO uint32_t FPCCR;
- __IO uint32_t FPCAR;
- __IO uint32_t FPDSCR;
- __I uint32_t MVFR0;
- __I uint32_t MVFR1;
- } FPU_Type;
-
-
- #define FPU_FPCCR_ASPEN_Pos 31
- #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
-
- #define FPU_FPCCR_LSPEN_Pos 30
- #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
-
- #define FPU_FPCCR_MONRDY_Pos 8
- #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
-
- #define FPU_FPCCR_BFRDY_Pos 6
- #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
-
- #define FPU_FPCCR_MMRDY_Pos 5
- #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
-
- #define FPU_FPCCR_HFRDY_Pos 4
- #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
-
- #define FPU_FPCCR_THREAD_Pos 3
- #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
-
- #define FPU_FPCCR_USER_Pos 1
- #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
-
- #define FPU_FPCCR_LSPACT_Pos 0
- #define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos)
-
-
- #define FPU_FPCAR_ADDRESS_Pos 3
- #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
-
-
- #define FPU_FPDSCR_AHP_Pos 26
- #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
-
- #define FPU_FPDSCR_DN_Pos 25
- #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
-
- #define FPU_FPDSCR_FZ_Pos 24
- #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
-
- #define FPU_FPDSCR_RMode_Pos 22
- #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
-
-
- #define FPU_MVFR0_FP_rounding_modes_Pos 28
- #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
-
- #define FPU_MVFR0_Short_vectors_Pos 24
- #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)
-
- #define FPU_MVFR0_Square_root_Pos 20
- #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)
-
- #define FPU_MVFR0_Divide_Pos 16
- #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)
-
- #define FPU_MVFR0_FP_excep_trapping_Pos 12
- #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
-
- #define FPU_MVFR0_Double_precision_Pos 8
- #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)
-
- #define FPU_MVFR0_Single_precision_Pos 4
- #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)
-
- #define FPU_MVFR0_A_SIMD_registers_Pos 0
- #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)
-
-
- #define FPU_MVFR1_FP_fused_MAC_Pos 28
- #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
-
- #define FPU_MVFR1_FP_HPFP_Pos 24
- #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
-
- #define FPU_MVFR1_D_NaN_mode_Pos 4
- #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
-
- #define FPU_MVFR1_FtZ_mode_Pos 0
- #define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos)
-
-
- #endif
-
-
-
-
-
- typedef struct
- {
- __IO uint32_t DHCSR;
- __O uint32_t DCRSR;
- __IO uint32_t DCRDR;
- __IO uint32_t DEMCR;
- } CoreDebug_Type;
-
-
- #define CoreDebug_DHCSR_DBGKEY_Pos 16
- #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
-
- #define CoreDebug_DHCSR_S_RESET_ST_Pos 25
- #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
-
- #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24
- #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
-
- #define CoreDebug_DHCSR_S_LOCKUP_Pos 19
- #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
-
- #define CoreDebug_DHCSR_S_SLEEP_Pos 18
- #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
-
- #define CoreDebug_DHCSR_S_HALT_Pos 17
- #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
-
- #define CoreDebug_DHCSR_S_REGRDY_Pos 16
- #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
-
- #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5
- #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
-
- #define CoreDebug_DHCSR_C_MASKINTS_Pos 3
- #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
-
- #define CoreDebug_DHCSR_C_STEP_Pos 2
- #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
-
- #define CoreDebug_DHCSR_C_HALT_Pos 1
- #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
-
- #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0
- #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)
-
-
- #define CoreDebug_DCRSR_REGWnR_Pos 16
- #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
-
- #define CoreDebug_DCRSR_REGSEL_Pos 0
- #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)
-
-
- #define CoreDebug_DEMCR_TRCENA_Pos 24
- #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
-
- #define CoreDebug_DEMCR_MON_REQ_Pos 19
- #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
-
- #define CoreDebug_DEMCR_MON_STEP_Pos 18
- #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
-
- #define CoreDebug_DEMCR_MON_PEND_Pos 17
- #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
-
- #define CoreDebug_DEMCR_MON_EN_Pos 16
- #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
-
- #define CoreDebug_DEMCR_VC_HARDERR_Pos 10
- #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
-
- #define CoreDebug_DEMCR_VC_INTERR_Pos 9
- #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
-
- #define CoreDebug_DEMCR_VC_BUSERR_Pos 8
- #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
-
- #define CoreDebug_DEMCR_VC_STATERR_Pos 7
- #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
-
- #define CoreDebug_DEMCR_VC_CHKERR_Pos 6
- #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
-
- #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5
- #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
-
- #define CoreDebug_DEMCR_VC_MMERR_Pos 4
- #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
-
- #define CoreDebug_DEMCR_VC_CORERESET_Pos 0
- #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)
-
-
-
-
-
-
-
- #define SCS_BASE (0xE000E000UL)
- #define ITM_BASE (0xE0000000UL)
- #define DWT_BASE (0xE0001000UL)
- #define TPI_BASE (0xE0040000UL)
- #define CoreDebug_BASE (0xE000EDF0UL)
- #define SysTick_BASE (SCS_BASE + 0x0010UL)
- #define NVIC_BASE (SCS_BASE + 0x0100UL)
- #define SCB_BASE (SCS_BASE + 0x0D00UL)
-
- #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
- #define SCB ((SCB_Type *) SCB_BASE )
- #define SysTick ((SysTick_Type *) SysTick_BASE )
- #define NVIC ((NVIC_Type *) NVIC_BASE )
- #define ITM ((ITM_Type *) ITM_BASE )
- #define DWT ((DWT_Type *) DWT_BASE )
- #define TPI ((TPI_Type *) TPI_BASE )
- #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)
-
- #if (__MPU_PRESENT == 1)
- #define MPU_BASE (SCS_BASE + 0x0D90UL)
- #define MPU ((MPU_Type *) MPU_BASE )
- #endif
-
- #if (__FPU_PRESENT == 1)
- #define FPU_BASE (SCS_BASE + 0x0F30UL)
- #define FPU ((FPU_Type *) FPU_BASE )
- #endif
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
- {
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);
-
- reg_value = SCB->AIRCR;
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);
- reg_value = (reg_value |
- ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8));
- SCB->AIRCR = reg_value;
- }
-
-
-
- __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
- {
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);
- }
-
-
-
- __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
- {
-
- NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F));
- }
-
-
-
- __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
- {
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
- }
-
-
-
- __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
- {
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
- }
-
-
-
- __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
- {
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
- }
-
-
-
- __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
- {
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
- }
-
-
-
- __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
- {
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
- }
-
-
-
- __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
- {
- if(IRQn < 0) {
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); }
- else {
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); }
- }
-
-
-
- __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
- {
-
- if(IRQn < 0) {
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); }
- else {
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); }
- }
-
-
-
- __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
- {
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
- return (
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
- );
- }
-
-
-
- __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
- {
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
- }
-
-
-
- __STATIC_INLINE void NVIC_SystemReset(void)
- {
- __DSB();
-
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk);
- __DSB();
- while(1);
- }
-
-
-
-
-
-
-
-
- #if (__Vendor_SysTickConfig == 0)
-
-
- __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
- {
- if (ticks > SysTick_LOAD_RELOAD_Msk) return (1);
-
- SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);
- SysTick->VAL = 0;
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk;
- return (0);
- }
-
- #endif
-
-
-
-
-
-
-
-
- extern volatile int32_t ITM_RxBuffer;
- #define ITM_RXBUFFER_EMPTY 0x5AA55AA5
-
-
-
- __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
- {
- if ((ITM->TCR & ITM_TCR_ITMENA_Msk) &&
- (ITM->TER & (1UL << 0) ) )
- {
- while (ITM->PORT[0].u32 == 0);
- ITM->PORT[0].u8 = (uint8_t) ch;
- }
- return (ch);
- }
-
-
-
- __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
- int32_t ch = -1;
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY;
- }
-
- return (ch);
- }
-
-
-
- __STATIC_INLINE int32_t ITM_CheckChar (void) {
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
- return (0);
- } else {
- return (1);
- }
- }
-
-
-
- #endif
-
- #endif
-
- #ifdef __cplusplus
- }
- #endif
|