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Teensy 4.1 core updated for C++20
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teensy-core-4.1/teensy/pins_teensy.c

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  1. /* Pin functions for the Teensy and Teensy++

  2.  * http://www.pjrc.com/teensy/

  3.  * Copyright (c) 2008-2010 PJRC.COM, LLC

  4.  * 

  5.  * Permission is hereby granted, free of charge, to any person obtaining a copy

  6.  * of this software and associated documentation files (the "Software"), to deal

  7.  * in the Software without restriction, including without limitation the rights

  8.  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

  9.  * copies of the Software, and to permit persons to whom the Software is

  10.  * furnished to do so, subject to the following conditions:

  11.  * 

  12.  * The above copyright notice and this permission notice shall be included in

  13.  * all copies or substantial portions of the Software.

  14.  * 

  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE

  18.  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

  20.  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

  21.  * THE SOFTWARE.

  22.  */

  23. 

  24. 

  25. #include <avr/io.h>

  26. #include <avr/pgmspace.h>

  27. #include <avr/sleep.h>

  28. #include "wiring_private.h"

  29. #include "pins_arduino.h"

  30. #include "usb_private.h"

  31. #include "core_pins.h"

  32. 

  33. // this doubles the analog input speed

  34. #define USE_ADC_HIGH_SPEED

  35. 

  36. 

  37. #ifdef USE_ADC_HIGH_SPEED

  38. #define DEFAULT_ADCSRB		0x80  // ADHSM

  39. #define ADC_PRESCALE_ADJUST	(-1)

  40. #else 

  41. #define DEFAULT_ADCSRB		0

  42. #define ADC_PRESCALE_ADJUST	0

  43. #endif

  44. 

  45. void _init_Teensyduino_internal_(void)

  46. {

  47. 	cli();

  48. 	CLKPR = 0x80;

  49. 	CLKPR = CPU_PRESCALER;

  50. 	// timer 0, fast pwm mode

  51. 	TCCR0A = (1<<WGM01) | (1<<WGM00);

  52. 	TCCR0B = (1<<CS01) | (1<<CS00);		// div 64 prescaler

  53. 	sbi(TIMSK0, TOIE0);

  54. 	// timer 1, 8 bit phase correct pwm

  55. 	TCCR1A = (1<<WGM10);

  56. 	TCCR1B = (1<<CS11);			// div 8 prescaler

  57. #if defined(__AVR_ATmega32U4__)

  58. 	// timer 3, 8 bit phase correct pwm

  59. 	TCCR3A = (1<<WGM30);

  60. 	TCCR3B = (1<<CS31);			// div 8 prescaler

  61. 	// timer 4, 8 bit phase correct pwm

  62. 	TCCR4A = (1<<PWM4A);

  63. 	TCCR4B = (1<<CS42);			// div 8 prescaler

  64. 	TCCR4C = (1<<PWM4D);

  65. 	TCCR4D = (1<<WGM40);			// phase correct pwm

  66. 	TCCR4E = 0;

  67. 	// ADC

  68. 	ADCSRA = (1<<ADEN) | (ADC_PRESCALER + ADC_PRESCALE_ADJUST);

  69. 	ADCSRB = DEFAULT_ADCSRB;

  70. 	DIDR0 = 0;

  71. 	DIDR2 = 0;

  72. #endif

  73. #if defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__)

  74. 	// timer 2, 8 bit phase correct pwm

  75. 	TCCR2A = (1<<WGM20);

  76. 	TCCR2B = (1<<CS21);			// div 8 prescaler

  77. 	// timer 3, 8 bit phase correct pwm

  78. 	TCCR3A = (1<<WGM30);

  79. 	TCCR3B = (1<<CS31);			// div 8 prescaler

  80. 	// ADC

  81. 	ADCSRA = (1<<ADEN) | (ADC_PRESCALER + ADC_PRESCALE_ADJUST);

  82. 	ADCSRB = DEFAULT_ADCSRB;

  83. 	DIDR0 = 0;

  84. #endif

  85. 	// initialize USB

  86. 	usb_init();

  87. 	sei();

  88. }

  89. 

  90. 

  91. void _analogWrite(uint8_t pin, int val)

  92. {

  93. 	pinMode(pin, OUTPUT);

  94. 

  95. 	switch (pin) {

  96. 	case CORE_OC0B_PIN:

  97. 		if (val == 0) {

  98. 			CORE_PORTREG(CORE_OC0B_PIN) &= ~CORE_BITMASK(CORE_OC0B_PIN);

  99. 			cbi(TCCR0A, COM0B1);

  100. 		} else {

  101. 			OCR0B = val;

  102. 			sbi(TCCR0A, COM0B1);

  103. 		}

  104. 		break;

  105. 	case CORE_OC1A_PIN: //TIMER1A:

  106. 		OCR1A = val;

  107. 		sbi(TCCR1A, COM1A1);

  108. 		break;

  109. 	case CORE_OC1B_PIN: //TIMER1B:

  110. 		OCR1B = val;

  111. 		sbi(TCCR1A, COM1B1);

  112. 		break;

  113. 	case CORE_OC1C_PIN: //TIMER1C:

  114. 		OCR1C = val;

  115. 		sbi(TCCR1A, COM1C1);

  116. 		break;

  117. #if defined(__AVR_ATmega32U4__)

  118. 	case CORE_OC3A_PIN: //TIMER3A:

  119. 		OCR3A = val;

  120. 		sbi(TCCR3A, COM3A1);

  121. 		break;

  122. 	case CORE_OC4A_PIN: //TIMER4A

  123. 		OCR4A = val;

  124. 		sbi(TCCR4A, COM4A1);

  125. 		break;

  126. 	case CORE_OC4D_PIN: //TIMER4D

  127. 		OCR4D = val;

  128. 		sbi(TCCR4C, COM4D1);

  129. 		break;

  130. #endif

  131. #if defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__)

  132. 	case CORE_OC2A_PIN: //TIMER2A:

  133. 		OCR2A = val;

  134. 		sbi(TCCR2A, COM2A1);

  135. 		break;

  136. 	case CORE_OC2B_PIN: //TIMER2B:

  137. 		OCR2B = val;

  138. 		sbi(TCCR2A, COM2B1);

  139. 		break;

  140. 	case CORE_OC3A_PIN: //TIMER3A:

  141. 		OCR3A = val;

  142. 		sbi(TCCR3A, COM3A1);

  143. 		break;

  144. 	case CORE_OC3B_PIN: //TIMER3B:

  145. 		OCR3B = val;

  146. 		sbi(TCCR3A, COM3B1);

  147. 		break;

  148. 	case CORE_OC3C_PIN: //TIMER3C:

  149. 		OCR3C = val;

  150. 		sbi(TCCR3A, COM3C1);

  151. 		break;

  152. #endif

  153. 	default:

  154. 		if (val < 128) {

  155. 			digitalWrite(pin, LOW);

  156. 		} else {

  157. 			digitalWrite(pin, HIGH);

  158. 		}

  159. 	}

  160. }

  161. 

  162. 

  163. 

  164. #if defined(__AVR_ATmega32U4__)

  165. uint8_t w_analog_reference = 0x40;

  166. 

  167. static const uint8_t PROGMEM adc_mapping[] = {

  168. // 0, 1, 4, 5, 6, 7, 13, 12, 11, 10, 9, 8

  169.    0, 1, 4, 5, 6, 7, 13, 12, 11, 10, 9, 8, 10, 11, 12, 13, 7, 6, 5, 4, 1, 0, 8 

  170. };

  171. 

  172. int analogRead(uint8_t pin)

  173. {

  174. 	uint8_t low, high, adc;

  175. 

  176. 	if (pin >= sizeof(adc_mapping)) return 0;

  177. 	adc = pgm_read_byte(adc_mapping + pin);

  178. 	if (adc < 8) {

  179. 		DIDR0 |= (1 << adc);

  180. 		//DDRF &= ~(1 << adc);

  181. 		//PORTF &= ~(1 << adc);

  182. 		ADCSRB = DEFAULT_ADCSRB;

  183. 		ADMUX = w_analog_reference | adc;

  184. 	} else {

  185. 		adc -= 8;

  186. 		DIDR2 |= (1 << adc);

  187. 		ADCSRB = DEFAULT_ADCSRB | (1<<MUX5);

  188. 		ADMUX = w_analog_reference | adc;

  189. 	}

  190. 	ADCSRA |= (1<<ADSC);

  191. 	while (ADCSRA & (1<<ADSC)) ;

  192. 	low = ADCL;

  193. 	high = ADCH;

  194. 	return (high << 8) | low;

  195. }

  196. 

  197. #elif defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__)

  198. 

  199. uint8_t w_analog_reference = 0x40;

  200. 

  201. int analogRead(uint8_t pin)

  202. {

  203. 	uint8_t low, high;

  204. 

  205. 	if (pin >= PIN_F0 && pin <= PIN_F7) pin -= PIN_F0;

  206. 	if (pin < 8) {

  207. 		DIDR0 |= (1 << pin);

  208. 		//DDRF &= ~(1 << pin);

  209. 		//PORTF &= ~(1 << pin);

  210. 	}

  211. 	ADMUX = w_analog_reference | (pin & 0x1F);

  212. 	ADCSRA |= (1<<ADSC);

  213. 	while (ADCSRA & (1<<ADSC)) ;

  214. 	low = ADCL;

  215. 	high = ADCH;

  216. 	return (high << 8) | low;

  217. }

  218. 

  219. #elif defined(__AVR_AT90USB162__)

  220. int analogRead(uint8_t pin)

  221. {

  222. 	return 0;

  223. }

  224. #endif

  225. 

  226. 

  227. 

  228. void _pinMode(uint8_t pin, uint8_t mode)

  229. {

  230. 	if (mode == OUTPUT) {

  231. 		_pinMode_output(pin);

  232. 	} else if (mode == INPUT_PULLUP) {

  233. 		_pinMode_input_pullup(pin);

  234. 	} else {

  235. 		_pinMode_input(pin);

  236. 	}

  237. }

  238. 

  239. #define PIN_REG_AND_MASK_LOOKUP(pin, reg, mask) \

  240. 	asm volatile(				\

  241. 		"lsl %2"		"\n\t"	\

  242. 		"add %A3, %2"		"\n\t"	\

  243. 		"adc %B3, __zero_reg__"	"\n\n"	\

  244. 		"lpm %1, Z+"		"\n\t"	\

  245. 		"lpm %A0, Z"		"\n\t"	\

  246. 		"ldi %B0, 0"		"\n"	\

  247. 		: "=z" (reg), "=r" (mask), "+r" (pin)	\

  248. 		: "z" (digital_pin_table_PGM), "2" (pin))

  249. 

  250. void _pinMode_output(uint8_t pin)

  251. {

  252. 	volatile uint8_t *reg;

  253. 	uint8_t mask, status;

  254. 

  255. 	if (pin >= CORE_NUM_TOTAL_PINS) return;

  256. 	PIN_REG_AND_MASK_LOOKUP(pin, reg, mask);

  257. 	status = SREG;

  258. 	cli();

  259. 	*(reg + 1) |= mask;

  260. 	SREG = status;

  261. }

  262. 

  263. #if defined(__AVR_ATmega32U4__)

  264. static const uint8_t PROGMEM didr_table_PGM[] = {

  265. 	(int)&DIDR2, ~0x02,

  266. 	(int)&DIDR2, ~0x04,

  267. 	(int)&DIDR2, ~0x08,

  268. 	(int)&DIDR2, ~0x10,

  269. 	(int)&DIDR2, ~0x20,

  270. 	(int)&DIDR0, 0x7F,  // ~0x80,

  271. 	(int)&DIDR0, ~0x40,

  272. 	(int)&DIDR0, ~0x20,

  273. 	(int)&DIDR0, ~0x10,

  274. 	(int)&DIDR0, ~0x02,

  275. 	(int)&DIDR0, ~0x01,

  276. 	(int)&DIDR2, ~0x01

  277. };

  278. #elif defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__)

  279. static const uint8_t PROGMEM didr_table_PGM[] = {

  280. 	(int)&DIDR0, ~0x01,

  281. 	(int)&DIDR0, ~0x02,

  282. 	(int)&DIDR0, ~0x04,

  283. 	(int)&DIDR0, ~0x08,

  284. 	(int)&DIDR0, ~0x10,

  285. 	(int)&DIDR0, ~0x20,

  286. 	(int)&DIDR0, ~0x40,

  287. 	(int)&DIDR0, 0x7F  // ~0x80

  288. };

  289. #endif

  290. 

  291. #define PIN_DIDR_AND_MASK_LOOKUP(pin, didreg, didmask)	\

  292. 	asm volatile(					\

  293. 		"lsl	%3"			"\n\t"	\

  294. 		"add	%A2, %3"		"\n\t"	\

  295. 		"adc	%B2, __zero_reg__"	"\n\n"	\

  296. 		"lpm	%A0, Z+"		"\n\t"	\

  297. 		"ldi	%B0, 0"			"\n\t"	\

  298. 		"lpm	%1, Z+"			"\n\t"	\

  299. 		: "=x" (didreg), "=r" (didmask)		\

  300. 		: "z" (didr_table_PGM), "r" (pin))

  301. 

  302. 

  303. void _pinMode_input(uint8_t pin)

  304. {

  305. 	volatile uint8_t *reg, *didr=0;

  306. 	uint8_t mask, didrmask=0xFF, status;

  307. 

  308. 	if (pin >= CORE_NUM_TOTAL_PINS) return;

  309. 	#if defined(__AVR_ATmega32U4__)

  310. 	if (pin >= 11 && pin <= 22) {

  311. 		PIN_DIDR_AND_MASK_LOOKUP((uint8_t)(pin - 11), didr, didrmask);

  312. 	}

  313. 	#elif defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__)

  314. 	if (pin >= PIN_F0 && pin <= PIN_F7) {

  315. 		PIN_DIDR_AND_MASK_LOOKUP((uint8_t)(pin - PIN_F0), didr, didrmask);

  316. 	}

  317. 	#endif

  318. 	PIN_REG_AND_MASK_LOOKUP(pin, reg, mask);

  319. 	status = SREG;

  320. 	cli();

  321. 	*(reg + 1) &= ~mask;

  322. 	*(reg + 2) &= ~mask;

  323. 	*didr &= didrmask;

  324. 	SREG = status;

  325. }

  326. 

  327. 

  328. void _pinMode_input_pullup(uint8_t pin)

  329. {

  330. 	volatile uint8_t *reg, *didr=0;

  331. 	uint8_t mask, didrmask=0xFF, status;

  332. 

  333. 	if (pin >= CORE_NUM_TOTAL_PINS) return;

  334. 	#if defined(__AVR_ATmega32U4__)

  335. 	if (pin >= 11 && pin <= 22) {

  336. 		PIN_DIDR_AND_MASK_LOOKUP((uint8_t)(pin - 11), didr, didrmask);

  337. 	}

  338. 	#elif defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__)

  339. 	if (pin >= PIN_F0 && pin <= PIN_F7) {

  340. 		PIN_DIDR_AND_MASK_LOOKUP((uint8_t)(pin - PIN_F0), didr, didrmask);

  341. 	}

  342. 	#endif

  343. 	PIN_REG_AND_MASK_LOOKUP(pin, reg, mask);

  344. 	status = SREG;

  345. 	cli();

  346. 	*(reg + 1) &= ~mask;

  347. 	*(reg + 2) |= mask;

  348. 	*didr &= didrmask;

  349. 	SREG = status;

  350. }

  351. 

  352. 

  353. 

  354. void _digitalWrite(void) __attribute__((naked));

  355. void _digitalWrite_HIGH(void) __attribute__((naked));

  356. void _digitalWrite_LOW(void) __attribute__((naked));

  357. void _digitalWrite_bailout(void);

  358. void _digitalWrite_HIGH_TABLE(void) __attribute__((naked));

  359. void _digitalWrite_LOW_TABLE(void) __attribute__((naked));

  360. void _digitalWrite_OC0B(void) __attribute__((naked));

  361. void _digitalWrite_OC1A(void) __attribute__((naked));

  362. void _digitalWrite_OC1B(void) __attribute__((naked));

  363. void _digitalWrite_OC1C(void) __attribute__((naked));

  364. void _digitalWrite_OC2A(void) __attribute__((naked));

  365. void _digitalWrite_OC2B(void) __attribute__((naked));

  366. void _digitalWrite_OC3A(void) __attribute__((naked));

  367. void _digitalWrite_OC3B(void) __attribute__((naked));

  368. void _digitalWrite_OC3C(void) __attribute__((naked));

  369. void _digitalWrite_OC4A(void) __attribute__((naked));

  370. void _digitalWrite_OC4D(void) __attribute__((naked));

  371. 

  372. 

  373. void _digitalWrite(void)

  374. {

  375. 	asm volatile(

  376. 		"tst	r0"				"\n\t"

  377. 		"breq	_digitalWrite_LOW"		"\n\t"

  378. 		"rjmp	_digitalWrite_HIGH"		"\n\t"

  379. 	);

  380. }

  381. 

  382. void _digitalWrite_HIGH(void)

  383. {

  384. 	asm volatile (

  385. 		#if !defined(DIGITAL_WRITE_RISKY_OMIT_OVERFLOW_CHECK)

  386. 		"cpi	r30, %0"					"\n\t"

  387. 		"brsh	_digitalWrite_bailout"				"\n\t"

  388. 		#endif

  389. 		"lsl	r30"						"\n\t"

  390. 		//"clr	r31"						"\n\t"

  391. 		"subi	r30, lo8(-(pm(_digitalWrite_HIGH_TABLE)))"	"\n\t"

  392. 		"sbci	r31, hi8(-(pm(_digitalWrite_HIGH_TABLE)))"	"\n\t"

  393. 		"ijmp"							"\n\t"

  394. 		: : "M" (CORE_NUM_TOTAL_PINS)

  395. 	);

  396. }

  397. 

  398. void _digitalWrite_LOW(void)

  399. {

  400. 	asm volatile (

  401. 		#if !defined(DIGITAL_WRITE_RISKY_OMIT_OVERFLOW_CHECK)

  402. 		"cpi	r30, %0"					"\n\t"

  403. 		"brsh	_digitalWrite_bailout"				"\n\t"

  404. 		#endif

  405. 		"lsl	r30"						"\n\t"

  406. 		//"clr	r31"						"\n\t"

  407. 		"subi	r30, lo8(-(pm(_digitalWrite_LOW_TABLE)))"	"\n\t"

  408. 		"sbci	r31, hi8(-(pm(_digitalWrite_LOW_TABLE)))"	"\n\t"

  409. 		"ijmp"							"\n\t"

  410. 		: : "M" (CORE_NUM_TOTAL_PINS)

  411. 	);

  412. }

  413. 

  414. void _digitalWrite_bailout(void) {}

  415. 

  416. #if defined(__AVR_ATmega32U4__)

  417. void _digitalWrite_HIGH_TABLE(void)

  418. {

  419. 	asm volatile (

  420. 		"sbi	%0, %1"					"\n\t"	// pin 0

  421. 		"ret"						"\n\t"

  422. 		"sbi	%2, %3"					"\n\t"	// pin 1

  423. 		"ret"						"\n\t"

  424. 		"sbi	%4, %5"					"\n\t"	// pin 2

  425. 		"ret"						"\n\t"

  426. 		"sbi	%6, %7"					"\n\t"	// pin 3

  427. 		"ret"						"\n\t"

  428. 		"sbi	%8, %9"					"\n\t"	// pin 4

  429. 		"rjmp	_digitalWrite_OC1C"			"\n\t"

  430. 		:: "I" (_SFR_IO_ADDR(CORE_PIN0_PORTREG)), "I" (CORE_PIN0_BIT),

  431. 		   "I" (_SFR_IO_ADDR(CORE_PIN1_PORTREG)), "I" (CORE_PIN1_BIT),

  432. 		   "I" (_SFR_IO_ADDR(CORE_PIN2_PORTREG)), "I" (CORE_PIN2_BIT),

  433. 		   "I" (_SFR_IO_ADDR(CORE_PIN3_PORTREG)), "I" (CORE_PIN3_BIT),

  434. 		   "I" (_SFR_IO_ADDR(CORE_PIN4_PORTREG)), "I" (CORE_PIN4_BIT)

  435. 	);

  436. 	asm volatile (

  437. 		"sbi	%0, %1"					"\n\t"	// pin 5

  438. 		"rjmp	_digitalWrite_OC0B"			"\n\t"

  439. 		"sbi	%2, %3"					"\n\t"	// pin 6

  440. 		"ret"						"\n\t"

  441. 		"sbi	%4, %5"					"\n\t"	// pin 7

  442. 		"ret"						"\n\t"

  443. 		"sbi	%6, %7"					"\n\t"	// pin 8

  444. 		"ret"						"\n\t"

  445. 		"sbi	%8, %9"					"\n\t"	// pin 9

  446. 		"rjmp	_digitalWrite_OC3A"			"\n\t"

  447. 		:: "I" (_SFR_IO_ADDR(CORE_PIN5_PORTREG)), "I" (CORE_PIN5_BIT),

  448. 		   "I" (_SFR_IO_ADDR(CORE_PIN6_PORTREG)), "I" (CORE_PIN6_BIT),

  449. 		   "I" (_SFR_IO_ADDR(CORE_PIN7_PORTREG)), "I" (CORE_PIN7_BIT),

  450. 		   "I" (_SFR_IO_ADDR(CORE_PIN8_PORTREG)), "I" (CORE_PIN8_BIT),

  451. 		   "I" (_SFR_IO_ADDR(CORE_PIN9_PORTREG)), "I" (CORE_PIN9_BIT)

  452. 	);

  453. 	asm volatile (

  454. 		"sbi	%0, %1"					"\n\t"	// pin 10

  455. 		"rjmp	_digitalWrite_OC4A"			"\n\t"

  456. 		"sbi	%2, %3"					"\n\t"	// pin 11

  457. 		"ret"						"\n\t"

  458. 		"sbi	%4, %5"					"\n\t"	// pin 12

  459. 		"rjmp	_digitalWrite_OC4D"			"\n\t"

  460. 		"sbi	%6, %7"					"\n\t"	// pin 13

  461. 		"ret"						"\n\t"

  462. 		"sbi	%8, %9"					"\n\t"	// pin 14

  463. 		"rjmp	_digitalWrite_OC1A"			"\n\t"

  464. 		:: "I" (_SFR_IO_ADDR(CORE_PIN10_PORTREG)), "I" (CORE_PIN10_BIT),

  465. 		   "I" (_SFR_IO_ADDR(CORE_PIN11_PORTREG)), "I" (CORE_PIN11_BIT),

  466. 		   "I" (_SFR_IO_ADDR(CORE_PIN12_PORTREG)), "I" (CORE_PIN12_BIT),

  467. 		   "I" (_SFR_IO_ADDR(CORE_PIN13_PORTREG)), "I" (CORE_PIN13_BIT),

  468. 		   "I" (_SFR_IO_ADDR(CORE_PIN14_PORTREG)), "I" (CORE_PIN14_BIT)

  469. 	);

  470. 	asm volatile (

  471. 		"sbi	%0, %1"					"\n\t"	// pin 15

  472. 		"rjmp	_digitalWrite_OC1B"			"\n\t"

  473. 		"sbi	%2, %3"					"\n\t"	// pin 16

  474. 		"ret"						"\n\t"

  475. 		"sbi	%4, %5"					"\n\t"	// pin 17

  476. 		"ret"						"\n\t"

  477. 		"sbi	%6, %7"					"\n\t"	// pin 18

  478. 		"ret"						"\n\t"

  479. 		"sbi	%8, %9"					"\n\t"	// pin 19

  480. 		"ret"						"\n\t"

  481. 		:: "I" (_SFR_IO_ADDR(CORE_PIN15_PORTREG)), "I" (CORE_PIN15_BIT),

  482. 		   "I" (_SFR_IO_ADDR(CORE_PIN16_PORTREG)), "I" (CORE_PIN16_BIT),

  483. 		   "I" (_SFR_IO_ADDR(CORE_PIN17_PORTREG)), "I" (CORE_PIN17_BIT),

  484. 		   "I" (_SFR_IO_ADDR(CORE_PIN18_PORTREG)), "I" (CORE_PIN18_BIT),

  485. 		   "I" (_SFR_IO_ADDR(CORE_PIN19_PORTREG)), "I" (CORE_PIN19_BIT)

  486. 	);

  487. 	asm volatile (

  488. 		"sbi	%0, %1"					"\n\t"	// pin 20

  489. 		"ret"						"\n\t"

  490. 		"sbi	%2, %3"					"\n\t"	// pin 21

  491. 		"ret"						"\n\t"

  492. 		"sbi	%4, %5"					"\n\t"	// pin 22

  493. 		"ret"						"\n\t"

  494. 		"sbi	%6, %7"					"\n\t"	// pin 23

  495. 		"ret"						"\n\t"

  496. 		"sbi	%8, %9"					"\n\t"	// pin 24

  497. 		"ret"						"\n\t"

  498. 		:: "I" (_SFR_IO_ADDR(CORE_PIN20_PORTREG)), "I" (CORE_PIN20_BIT),

  499. 		   "I" (_SFR_IO_ADDR(CORE_PIN21_PORTREG)), "I" (CORE_PIN21_BIT),

  500. 		   "I" (_SFR_IO_ADDR(CORE_PIN22_PORTREG)), "I" (CORE_PIN22_BIT),

  501. 		   "I" (_SFR_IO_ADDR(CORE_PIN23_PORTREG)), "I" (CORE_PIN23_BIT),

  502. 		   "I" (_SFR_IO_ADDR(CORE_PIN24_PORTREG)), "I" (CORE_PIN24_BIT)

  503. 	);

  504. }

  505. void _digitalWrite_LOW_TABLE(void)

  506. {

  507. 	asm volatile (

  508. 		"cbi	%0, %1"					"\n\t"	// pin 0

  509. 		"ret"						"\n\t"

  510. 		"cbi	%2, %3"					"\n\t"	// pin 1

  511. 		"ret"						"\n\t"

  512. 		"cbi	%4, %5"					"\n\t"	// pin 2

  513. 		"ret"						"\n\t"

  514. 		"cbi	%6, %7"					"\n\t"	// pin 3

  515. 		"ret"						"\n\t"

  516. 		"cbi	%8, %9"					"\n\t"	// pin 4

  517. 		"rjmp	_digitalWrite_OC1C"			"\n\t"

  518. 		:: "I" (_SFR_IO_ADDR(CORE_PIN0_PORTREG)), "I" (CORE_PIN0_BIT),

  519. 		   "I" (_SFR_IO_ADDR(CORE_PIN1_PORTREG)), "I" (CORE_PIN1_BIT),

  520. 		   "I" (_SFR_IO_ADDR(CORE_PIN2_PORTREG)), "I" (CORE_PIN2_BIT),

  521. 		   "I" (_SFR_IO_ADDR(CORE_PIN3_PORTREG)), "I" (CORE_PIN3_BIT),

  522. 		   "I" (_SFR_IO_ADDR(CORE_PIN4_PORTREG)), "I" (CORE_PIN4_BIT)

  523. 	);

  524. 	asm volatile (

  525. 		"cbi	%0, %1"					"\n\t"	// pin 5

  526. 		"rjmp	_digitalWrite_OC0B"			"\n\t"

  527. 		"cbi	%2, %3"					"\n\t"	// pin 6

  528. 		"ret"						"\n\t"

  529. 		"cbi	%4, %5"					"\n\t"	// pin 7

  530. 		"ret"						"\n\t"

  531. 		"cbi	%6, %7"					"\n\t"	// pin 8

  532. 		"ret"						"\n\t"

  533. 		"cbi	%8, %9"					"\n\t"	// pin 9

  534. 		"rjmp	_digitalWrite_OC3A"			"\n\t"

  535. 		:: "I" (_SFR_IO_ADDR(CORE_PIN5_PORTREG)), "I" (CORE_PIN5_BIT),

  536. 		   "I" (_SFR_IO_ADDR(CORE_PIN6_PORTREG)), "I" (CORE_PIN6_BIT),

  537. 		   "I" (_SFR_IO_ADDR(CORE_PIN7_PORTREG)), "I" (CORE_PIN7_BIT),

  538. 		   "I" (_SFR_IO_ADDR(CORE_PIN8_PORTREG)), "I" (CORE_PIN8_BIT),

  539. 		   "I" (_SFR_IO_ADDR(CORE_PIN9_PORTREG)), "I" (CORE_PIN9_BIT)

  540. 	);

  541. 	asm volatile (

  542. 		"cbi	%0, %1"					"\n\t"	// pin 10

  543. 		"rjmp	_digitalWrite_OC4A"			"\n\t"

  544. 		"cbi	%2, %3"					"\n\t"	// pin 11

  545. 		"ret"						"\n\t"

  546. 		"cbi	%4, %5"					"\n\t"	// pin 12

  547. 		"rjmp	_digitalWrite_OC4D"			"\n\t"

  548. 		"cbi	%6, %7"					"\n\t"	// pin 13

  549. 		"ret"						"\n\t"

  550. 		"cbi	%8, %9"					"\n\t"	// pin 14

  551. 		"rjmp	_digitalWrite_OC1A"			"\n\t"

  552. 		:: "I" (_SFR_IO_ADDR(CORE_PIN10_PORTREG)), "I" (CORE_PIN10_BIT),

  553. 		   "I" (_SFR_IO_ADDR(CORE_PIN11_PORTREG)), "I" (CORE_PIN11_BIT),

  554. 		   "I" (_SFR_IO_ADDR(CORE_PIN12_PORTREG)), "I" (CORE_PIN12_BIT),

  555. 		   "I" (_SFR_IO_ADDR(CORE_PIN13_PORTREG)), "I" (CORE_PIN13_BIT),

  556. 		   "I" (_SFR_IO_ADDR(CORE_PIN14_PORTREG)), "I" (CORE_PIN14_BIT)

  557. 	);

  558. 	asm volatile (

  559. 		"cbi	%0, %1"					"\n\t"	// pin 15

  560. 		"rjmp	_digitalWrite_OC1B"			"\n\t"

  561. 		"cbi	%2, %3"					"\n\t"	// pin 16

  562. 		"ret"						"\n\t"

  563. 		"cbi	%4, %5"					"\n\t"	// pin 17

  564. 		"ret"						"\n\t"

  565. 		"cbi	%6, %7"					"\n\t"	// pin 18

  566. 		"ret"						"\n\t"

  567. 		"cbi	%8, %9"					"\n\t"	// pin 19

  568. 		"ret"						"\n\t"

  569. 		:: "I" (_SFR_IO_ADDR(CORE_PIN15_PORTREG)), "I" (CORE_PIN15_BIT),

  570. 		   "I" (_SFR_IO_ADDR(CORE_PIN16_PORTREG)), "I" (CORE_PIN16_BIT),

  571. 		   "I" (_SFR_IO_ADDR(CORE_PIN17_PORTREG)), "I" (CORE_PIN17_BIT),

  572. 		   "I" (_SFR_IO_ADDR(CORE_PIN18_PORTREG)), "I" (CORE_PIN18_BIT),

  573. 		   "I" (_SFR_IO_ADDR(CORE_PIN19_PORTREG)), "I" (CORE_PIN19_BIT)

  574. 	);

  575. 	asm volatile (

  576. 		"cbi	%0, %1"					"\n\t"	// pin 20

  577. 		"ret"						"\n\t"

  578. 		"cbi	%2, %3"					"\n\t"	// pin 21

  579. 		"ret"						"\n\t"

  580. 		"cbi	%4, %5"					"\n\t"	// pin 22

  581. 		"ret"						"\n\t"

  582. 		"cbi	%6, %7"					"\n\t"	// pin 23

  583. 		"ret"						"\n\t"

  584. 		"cbi	%8, %9"					"\n\t"	// pin 24

  585. 		"ret"						"\n\t"

  586. 		:: "I" (_SFR_IO_ADDR(CORE_PIN20_PORTREG)), "I" (CORE_PIN20_BIT),

  587. 		   "I" (_SFR_IO_ADDR(CORE_PIN21_PORTREG)), "I" (CORE_PIN21_BIT),

  588. 		   "I" (_SFR_IO_ADDR(CORE_PIN22_PORTREG)), "I" (CORE_PIN22_BIT),

  589. 		   "I" (_SFR_IO_ADDR(CORE_PIN23_PORTREG)), "I" (CORE_PIN23_BIT),

  590. 		   "I" (_SFR_IO_ADDR(CORE_PIN24_PORTREG)), "I" (CORE_PIN24_BIT)

  591. 	);

  592. }

  593. #elif defined(__AVR_AT90USB162__)

  594. void _digitalWrite_HIGH_TABLE(void)

  595. {

  596. 	asm volatile (

  597. 		"sbi	%0, %1"					"\n\t"	// pin 0

  598. 		"rjmp	_digitalWrite_OC0B"			"\n\t"

  599. 		"sbi	%2, %3"					"\n\t"	// pin 1

  600. 		"ret"						"\n\t"

  601. 		"sbi	%4, %5"					"\n\t"	// pin 2

  602. 		"ret"						"\n\t"

  603. 		"sbi	%6, %7"					"\n\t"	// pin 3

  604. 		"ret"						"\n\t"

  605. 		"sbi	%8, %9"					"\n\t"	// pin 4

  606. 		"ret"						"\n\t"

  607. 		:: "I" (_SFR_IO_ADDR(CORE_PIN0_PORTREG)), "I" (CORE_PIN0_BIT),

  608. 		   "I" (_SFR_IO_ADDR(CORE_PIN1_PORTREG)), "I" (CORE_PIN1_BIT),

  609. 		   "I" (_SFR_IO_ADDR(CORE_PIN2_PORTREG)), "I" (CORE_PIN2_BIT),

  610. 		   "I" (_SFR_IO_ADDR(CORE_PIN3_PORTREG)), "I" (CORE_PIN3_BIT),

  611. 		   "I" (_SFR_IO_ADDR(CORE_PIN4_PORTREG)), "I" (CORE_PIN4_BIT)

  612. 	);

  613. 	asm volatile (

  614. 		"sbi	%0, %1"					"\n\t"	// pin 5

  615. 		"ret"						"\n\t"

  616. 		"sbi	%2, %3"					"\n\t"	// pin 6

  617. 		"ret"						"\n\t"

  618. 		"sbi	%4, %5"					"\n\t"	// pin 7

  619. 		"ret"						"\n\t"

  620. 		"sbi	%6, %7"					"\n\t"	// pin 8

  621. 		"ret"						"\n\t"

  622. 		"sbi	%8, %9"					"\n\t"	// pin 9

  623. 		"ret"						"\n\t"

  624. 		:: "I" (_SFR_IO_ADDR(CORE_PIN5_PORTREG)), "I" (CORE_PIN5_BIT),

  625. 		   "I" (_SFR_IO_ADDR(CORE_PIN6_PORTREG)), "I" (CORE_PIN6_BIT),

  626. 		   "I" (_SFR_IO_ADDR(CORE_PIN7_PORTREG)), "I" (CORE_PIN7_BIT),

  627. 		   "I" (_SFR_IO_ADDR(CORE_PIN8_PORTREG)), "I" (CORE_PIN8_BIT),

  628. 		   "I" (_SFR_IO_ADDR(CORE_PIN9_PORTREG)), "I" (CORE_PIN9_BIT)

  629. 	);

  630. 	asm volatile (

  631. 		"sbi	%0, %1"					"\n\t"	// pin 10

  632. 		"ret"						"\n\t"

  633. 		"sbi	%2, %3"					"\n\t"	// pin 11

  634. 		"ret"						"\n\t"

  635. 		"sbi	%4, %5"					"\n\t"	// pin 12

  636. 		"ret"						"\n\t"

  637. 		"sbi	%6, %7"					"\n\t"	// pin 13

  638. 		"ret"						"\n\t"

  639. 		"sbi	%8, %9"					"\n\t"	// pin 14

  640. 		"ret"						"\n\t"

  641. 		:: "I" (_SFR_IO_ADDR(CORE_PIN10_PORTREG)), "I" (CORE_PIN10_BIT),

  642. 		   "I" (_SFR_IO_ADDR(CORE_PIN11_PORTREG)), "I" (CORE_PIN11_BIT),

  643. 		   "I" (_SFR_IO_ADDR(CORE_PIN12_PORTREG)), "I" (CORE_PIN12_BIT),

  644. 		   "I" (_SFR_IO_ADDR(CORE_PIN13_PORTREG)), "I" (CORE_PIN13_BIT),

  645. 		   "I" (_SFR_IO_ADDR(CORE_PIN14_PORTREG)), "I" (CORE_PIN14_BIT)

  646. 	);

  647. 	asm volatile (

  648. 		"sbi	%0, %1"					"\n\t"	// pin 15

  649. 		"rjmp	_digitalWrite_OC1C"			"\n\t"

  650. 		"sbi	%2, %3"					"\n\t"	// pin 16

  651. 		"ret"						"\n\t"

  652. 		"sbi	%4, %5"					"\n\t"	// pin 17

  653. 		"rjmp	_digitalWrite_OC1A"			"\n\t"

  654. 		"sbi	%6, %7"					"\n\t"	// pin 18

  655. 		"rjmp	_digitalWrite_OC1B"			"\n\t"

  656. 		"sbi	%8, %9"					"\n\t"	// pin 19

  657. 		"ret"						"\n\t"

  658. 		"sbi	%10, %11"				"\n\t"	// pin 20

  659. 		"ret"						"\n\t"

  660. 		:: "I" (_SFR_IO_ADDR(CORE_PIN15_PORTREG)), "I" (CORE_PIN15_BIT),

  661. 		   "I" (_SFR_IO_ADDR(CORE_PIN16_PORTREG)), "I" (CORE_PIN16_BIT),

  662. 		   "I" (_SFR_IO_ADDR(CORE_PIN17_PORTREG)), "I" (CORE_PIN17_BIT),

  663. 		   "I" (_SFR_IO_ADDR(CORE_PIN18_PORTREG)), "I" (CORE_PIN18_BIT),

  664. 		   "I" (_SFR_IO_ADDR(CORE_PIN19_PORTREG)), "I" (CORE_PIN19_BIT),

  665. 		   "I" (_SFR_IO_ADDR(CORE_PIN20_PORTREG)), "I" (CORE_PIN20_BIT)

  666. 	);

  667. }

  668. void _digitalWrite_LOW_TABLE(void)

  669. {

  670. 	asm volatile (

  671. 		"cbi	%0, %1"					"\n\t"	// pin 0

  672. 		"rjmp	_digitalWrite_OC0B"			"\n\t"

  673. 		"cbi	%2, %3"					"\n\t"	// pin 1

  674. 		"ret"						"\n\t"

  675. 		"cbi	%4, %5"					"\n\t"	// pin 2

  676. 		"ret"						"\n\t"

  677. 		"cbi	%6, %7"					"\n\t"	// pin 3

  678. 		"ret"						"\n\t"

  679. 		"cbi	%8, %9"					"\n\t"	// pin 4

  680. 		"ret"						"\n\t"

  681. 		:: "I" (_SFR_IO_ADDR(CORE_PIN0_PORTREG)), "I" (CORE_PIN0_BIT),

  682. 		   "I" (_SFR_IO_ADDR(CORE_PIN1_PORTREG)), "I" (CORE_PIN1_BIT),

  683. 		   "I" (_SFR_IO_ADDR(CORE_PIN2_PORTREG)), "I" (CORE_PIN2_BIT),

  684. 		   "I" (_SFR_IO_ADDR(CORE_PIN3_PORTREG)), "I" (CORE_PIN3_BIT),

  685. 		   "I" (_SFR_IO_ADDR(CORE_PIN4_PORTREG)), "I" (CORE_PIN4_BIT)

  686. 	);

  687. 	asm volatile (

  688. 		"cbi	%0, %1"					"\n\t"	// pin 5

  689. 		"ret"						"\n\t"

  690. 		"cbi	%2, %3"					"\n\t"	// pin 6

  691. 		"ret"						"\n\t"

  692. 		"cbi	%4, %5"					"\n\t"	// pin 7

  693. 		"ret"						"\n\t"

  694. 		"cbi	%6, %7"					"\n\t"	// pin 8

  695. 		"ret"						"\n\t"

  696. 		"cbi	%8, %9"					"\n\t"	// pin 9

  697. 		"ret"						"\n\t"

  698. 		:: "I" (_SFR_IO_ADDR(CORE_PIN5_PORTREG)), "I" (CORE_PIN5_BIT),

  699. 		   "I" (_SFR_IO_ADDR(CORE_PIN6_PORTREG)), "I" (CORE_PIN6_BIT),

  700. 		   "I" (_SFR_IO_ADDR(CORE_PIN7_PORTREG)), "I" (CORE_PIN7_BIT),

  701. 		   "I" (_SFR_IO_ADDR(CORE_PIN8_PORTREG)), "I" (CORE_PIN8_BIT),

  702. 		   "I" (_SFR_IO_ADDR(CORE_PIN9_PORTREG)), "I" (CORE_PIN9_BIT)

  703. 	);

  704. 	asm volatile (

  705. 		"cbi	%0, %1"					"\n\t"	// pin 10

  706. 		"ret"						"\n\t"

  707. 		"cbi	%2, %3"					"\n\t"	// pin 11

  708. 		"ret"						"\n\t"

  709. 		"cbi	%4, %5"					"\n\t"	// pin 12

  710. 		"ret"						"\n\t"

  711. 		"cbi	%6, %7"					"\n\t"	// pin 13

  712. 		"ret"						"\n\t"

  713. 		"cbi	%8, %9"					"\n\t"	// pin 14

  714. 		"ret"						"\n\t"

  715. 		:: "I" (_SFR_IO_ADDR(CORE_PIN10_PORTREG)), "I" (CORE_PIN10_BIT),

  716. 		   "I" (_SFR_IO_ADDR(CORE_PIN11_PORTREG)), "I" (CORE_PIN11_BIT),

  717. 		   "I" (_SFR_IO_ADDR(CORE_PIN12_PORTREG)), "I" (CORE_PIN12_BIT),

  718. 		   "I" (_SFR_IO_ADDR(CORE_PIN13_PORTREG)), "I" (CORE_PIN13_BIT),

  719. 		   "I" (_SFR_IO_ADDR(CORE_PIN14_PORTREG)), "I" (CORE_PIN14_BIT)

  720. 	);

  721. 	asm volatile (

  722. 		"cbi	%0, %1"					"\n\t"	// pin 15

  723. 		"rjmp	_digitalWrite_OC1C"			"\n\t"

  724. 		"cbi	%2, %3"					"\n\t"	// pin 16

  725. 		"ret"						"\n\t"

  726. 		"cbi	%4, %5"					"\n\t"	// pin 17

  727. 		"rjmp	_digitalWrite_OC1A"			"\n\t"

  728. 		"cbi	%6, %7"					"\n\t"	// pin 18

  729. 		"rjmp	_digitalWrite_OC1B"			"\n\t"

  730. 		"cbi	%8, %9"					"\n\t"	// pin 19

  731. 		"ret"						"\n\t"

  732. 		"cbi	%10, %11"				"\n\t"	// pin 20

  733. 		"ret"						"\n\t"

  734. 		:: "I" (_SFR_IO_ADDR(CORE_PIN15_PORTREG)), "I" (CORE_PIN15_BIT),

  735. 		   "I" (_SFR_IO_ADDR(CORE_PIN16_PORTREG)), "I" (CORE_PIN16_BIT),

  736. 		   "I" (_SFR_IO_ADDR(CORE_PIN17_PORTREG)), "I" (CORE_PIN17_BIT),

  737. 		   "I" (_SFR_IO_ADDR(CORE_PIN18_PORTREG)), "I" (CORE_PIN18_BIT),

  738. 		   "I" (_SFR_IO_ADDR(CORE_PIN19_PORTREG)), "I" (CORE_PIN19_BIT),

  739. 		   "I" (_SFR_IO_ADDR(CORE_PIN20_PORTREG)), "I" (CORE_PIN20_BIT)

  740. 	);

  741. }

  742. 

  743. 

  744. 

  745. #elif defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__)

  746. void _digitalWrite_HIGH_TABLE(void)

  747. {

  748. 	asm volatile (

  749. 		"sbi	%0, %1"					"\n\t"	// pin 0

  750. 		"rjmp	_digitalWrite_OC0B"			"\n\t"

  751. 		"sbi	%2, %3"					"\n\t"	// pin 1

  752. 		"rjmp	_digitalWrite_OC2B"			"\n\t"

  753. 		"sbi	%4, %5"					"\n\t"	// pin 2

  754. 		"ret"						"\n\t"

  755. 		"sbi	%6, %7"					"\n\t"	// pin 3

  756. 		"ret"						"\n\t"

  757. 		"sbi	%8, %9"					"\n\t"	// pin 4

  758. 		"ret"						"\n\t"

  759. 		:: "I" (_SFR_IO_ADDR(CORE_PIN0_PORTREG)), "I" (CORE_PIN0_BIT),

  760. 		   "I" (_SFR_IO_ADDR(CORE_PIN1_PORTREG)), "I" (CORE_PIN1_BIT),

  761. 		   "I" (_SFR_IO_ADDR(CORE_PIN2_PORTREG)), "I" (CORE_PIN2_BIT),

  762. 		   "I" (_SFR_IO_ADDR(CORE_PIN3_PORTREG)), "I" (CORE_PIN3_BIT),

  763. 		   "I" (_SFR_IO_ADDR(CORE_PIN4_PORTREG)), "I" (CORE_PIN4_BIT)

  764. 	);

  765. 	asm volatile (

  766. 		"sbi	%0, %1"					"\n\t"	// pin 5

  767. 		"ret"						"\n\t"

  768. 		"sbi	%2, %3"					"\n\t"	// pin 6

  769. 		"ret"						"\n\t"

  770. 		"sbi	%4, %5"					"\n\t"	// pin 7

  771. 		"ret"						"\n\t"

  772. 		"sbi	%6, %7"					"\n\t"	// pin 8

  773. 		"ret"						"\n\t"

  774. 		"sbi	%8, %9"					"\n\t"	// pin 9

  775. 		"ret"						"\n\t"

  776. 		:: "I" (_SFR_IO_ADDR(CORE_PIN5_PORTREG)), "I" (CORE_PIN5_BIT),

  777. 		   "I" (_SFR_IO_ADDR(CORE_PIN6_PORTREG)), "I" (CORE_PIN6_BIT),

  778. 		   "I" (_SFR_IO_ADDR(CORE_PIN7_PORTREG)), "I" (CORE_PIN7_BIT),

  779. 		   "I" (_SFR_IO_ADDR(CORE_PIN8_PORTREG)), "I" (CORE_PIN8_BIT),

  780. 		   "I" (_SFR_IO_ADDR(CORE_PIN9_PORTREG)), "I" (CORE_PIN9_BIT)

  781. 	);

  782. 	asm volatile (

  783. 		"sbi	%0, %1"					"\n\t"	// pin 10

  784. 		"ret"						"\n\t"

  785. 		"sbi	%2, %3"					"\n\t"	// pin 11

  786. 		"ret"						"\n\t"

  787. 		"sbi	%4, %5"					"\n\t"	// pin 12

  788. 		"ret"						"\n\t"

  789. 		"sbi	%6, %7"					"\n\t"	// pin 13

  790. 		"ret"						"\n\t"

  791. 		"sbi	%8, %9"					"\n\t"	// pin 14

  792. 		"rjmp	_digitalWrite_OC3C"			"\n\t"

  793. 		:: "I" (_SFR_IO_ADDR(CORE_PIN10_PORTREG)), "I" (CORE_PIN10_BIT),

  794. 		   "I" (_SFR_IO_ADDR(CORE_PIN11_PORTREG)), "I" (CORE_PIN11_BIT),

  795. 		   "I" (_SFR_IO_ADDR(CORE_PIN12_PORTREG)), "I" (CORE_PIN12_BIT),

  796. 		   "I" (_SFR_IO_ADDR(CORE_PIN13_PORTREG)), "I" (CORE_PIN13_BIT),

  797. 		   "I" (_SFR_IO_ADDR(CORE_PIN14_PORTREG)), "I" (CORE_PIN14_BIT)

  798. 	);

  799. 	asm volatile (

  800. 		"sbi	%0, %1"					"\n\t"	// pin 15

  801. 		"rjmp	_digitalWrite_OC3B"			"\n\t"

  802. 		"sbi	%2, %3"					"\n\t"	// pin 16

  803. 		"rjmp	_digitalWrite_OC3A"			"\n\t"

  804. 		"sbi	%4, %5"					"\n\t"	// pin 17

  805. 		"ret"						"\n\t"

  806. 		"sbi	%6, %7"					"\n\t"	// pin 18

  807. 		"ret"						"\n\t"

  808. 		"sbi	%8, %9"					"\n\t"	// pin 19

  809. 		"ret"						"\n\t"

  810. 		:: "I" (_SFR_IO_ADDR(CORE_PIN15_PORTREG)), "I" (CORE_PIN15_BIT),

  811. 		   "I" (_SFR_IO_ADDR(CORE_PIN16_PORTREG)), "I" (CORE_PIN16_BIT),

  812. 		   "I" (_SFR_IO_ADDR(CORE_PIN17_PORTREG)), "I" (CORE_PIN17_BIT),

  813. 		   "I" (_SFR_IO_ADDR(CORE_PIN18_PORTREG)), "I" (CORE_PIN18_BIT),

  814. 		   "I" (_SFR_IO_ADDR(CORE_PIN19_PORTREG)), "I" (CORE_PIN19_BIT)

  815. 	);

  816. 	asm volatile (

  817. 		"sbi	%0, %1"					"\n\t"	// pin 20

  818. 		"ret"						"\n\t"

  819. 		"sbi	%2, %3"					"\n\t"	// pin 21

  820. 		"ret"						"\n\t"

  821. 		"sbi	%4, %5"					"\n\t"	// pin 22

  822. 		"ret"						"\n\t"

  823. 		"sbi	%6, %7"					"\n\t"	// pin 23

  824. 		"ret"						"\n\t"

  825. 		"sbi	%8, %9"					"\n\t"	// pin 24

  826. 		"rjmp	_digitalWrite_OC2A"			"\n\t"

  827. 		:: "I" (_SFR_IO_ADDR(CORE_PIN20_PORTREG)), "I" (CORE_PIN20_BIT),

  828. 		   "I" (_SFR_IO_ADDR(CORE_PIN21_PORTREG)), "I" (CORE_PIN21_BIT),

  829. 		   "I" (_SFR_IO_ADDR(CORE_PIN22_PORTREG)), "I" (CORE_PIN22_BIT),

  830. 		   "I" (_SFR_IO_ADDR(CORE_PIN23_PORTREG)), "I" (CORE_PIN23_BIT),

  831. 		   "I" (_SFR_IO_ADDR(CORE_PIN24_PORTREG)), "I" (CORE_PIN24_BIT)

  832. 	);

  833. 	asm volatile (

  834. 		"sbi	%0, %1"					"\n\t"	// pin 25

  835. 		"rjmp	_digitalWrite_OC1A"			"\n\t"

  836. 		"sbi	%2, %3"					"\n\t"	// pin 26

  837. 		"rjmp	_digitalWrite_OC1B"			"\n\t"

  838. 		"sbi	%4, %5"					"\n\t"	// pin 27

  839. 		"rjmp	_digitalWrite_OC1C"			"\n\t"

  840. 		"sbi	%6, %7"					"\n\t"	// pin 28

  841. 		"ret"						"\n\t"

  842. 		"sbi	%8, %9"					"\n\t"	// pin 29

  843. 		"ret"						"\n\t"

  844. 		:: "I" (_SFR_IO_ADDR(CORE_PIN25_PORTREG)), "I" (CORE_PIN25_BIT),

  845. 		   "I" (_SFR_IO_ADDR(CORE_PIN26_PORTREG)), "I" (CORE_PIN26_BIT),

  846. 		   "I" (_SFR_IO_ADDR(CORE_PIN27_PORTREG)), "I" (CORE_PIN27_BIT),

  847. 		   "I" (_SFR_IO_ADDR(CORE_PIN28_PORTREG)), "I" (CORE_PIN28_BIT),

  848. 		   "I" (_SFR_IO_ADDR(CORE_PIN29_PORTREG)), "I" (CORE_PIN29_BIT)

  849. 	);

  850. 	asm volatile (

  851. 		"sbi	%0, %1"					"\n\t"	// pin 30

  852. 		"ret"						"\n\t"

  853. 		"sbi	%2, %3"					"\n\t"	// pin 31

  854. 		"ret"						"\n\t"

  855. 		"sbi	%4, %5"					"\n\t"	// pin 32

  856. 		"ret"						"\n\t"

  857. 		"sbi	%6, %7"					"\n\t"	// pin 33

  858. 		"ret"						"\n\t"

  859. 		"sbi	%8, %9"					"\n\t"	// pin 34

  860. 		"ret"						"\n\t"

  861. 		:: "I" (_SFR_IO_ADDR(CORE_PIN30_PORTREG)), "I" (CORE_PIN30_BIT),

  862. 		   "I" (_SFR_IO_ADDR(CORE_PIN31_PORTREG)), "I" (CORE_PIN31_BIT),

  863. 		   "I" (_SFR_IO_ADDR(CORE_PIN32_PORTREG)), "I" (CORE_PIN32_BIT),

  864. 		   "I" (_SFR_IO_ADDR(CORE_PIN33_PORTREG)), "I" (CORE_PIN33_BIT),

  865. 		   "I" (_SFR_IO_ADDR(CORE_PIN34_PORTREG)), "I" (CORE_PIN34_BIT)

  866. 	);

  867. 	asm volatile (

  868. 		"sbi	%0, %1"					"\n\t"	// pin 35

  869. 		"ret"						"\n\t"

  870. 		"sbi	%2, %3"					"\n\t"	// pin 36

  871. 		"ret"						"\n\t"

  872. 		"sbi	%4, %5"					"\n\t"	// pin 37

  873. 		"ret"						"\n\t"

  874. 		"sbi	%6, %7"					"\n\t"	// pin 38

  875. 		"ret"						"\n\t"

  876. 		"sbi	%8, %9"					"\n\t"	// pin 39

  877. 		"ret"						"\n\t"

  878. 		:: "I" (_SFR_IO_ADDR(CORE_PIN35_PORTREG)), "I" (CORE_PIN35_BIT),

  879. 		   "I" (_SFR_IO_ADDR(CORE_PIN36_PORTREG)), "I" (CORE_PIN36_BIT),

  880. 		   "I" (_SFR_IO_ADDR(CORE_PIN37_PORTREG)), "I" (CORE_PIN37_BIT),

  881. 		   "I" (_SFR_IO_ADDR(CORE_PIN38_PORTREG)), "I" (CORE_PIN38_BIT),

  882. 		   "I" (_SFR_IO_ADDR(CORE_PIN39_PORTREG)), "I" (CORE_PIN39_BIT)

  883. 	);

  884. 	asm volatile (

  885. 		"sbi	%0, %1"					"\n\t"	// pin 40

  886. 		"ret"						"\n\t"

  887. 		"sbi	%2, %3"					"\n\t"	// pin 41

  888. 		"ret"						"\n\t"

  889. 		"sbi	%4, %5"					"\n\t"	// pin 42

  890. 		"ret"						"\n\t"

  891. 		"sbi	%6, %7"					"\n\t"	// pin 43

  892. 		"ret"						"\n\t"

  893. 		"sbi	%8, %9"					"\n\t"	// pin 44

  894. 		"ret"						"\n\t"

  895. 		"sbi	%10, %11"				"\n\t"	// pin 45

  896. 		"ret"						"\n\t"

  897. 		:: "I" (_SFR_IO_ADDR(CORE_PIN40_PORTREG)), "I" (CORE_PIN40_BIT),

  898. 		   "I" (_SFR_IO_ADDR(CORE_PIN41_PORTREG)), "I" (CORE_PIN41_BIT),

  899. 		   "I" (_SFR_IO_ADDR(CORE_PIN42_PORTREG)), "I" (CORE_PIN42_BIT),

  900. 		   "I" (_SFR_IO_ADDR(CORE_PIN43_PORTREG)), "I" (CORE_PIN43_BIT),

  901. 		   "I" (_SFR_IO_ADDR(CORE_PIN44_PORTREG)), "I" (CORE_PIN44_BIT),

  902. 		   "I" (_SFR_IO_ADDR(CORE_PIN45_PORTREG)), "I" (CORE_PIN45_BIT)

  903. 	);

  904. }

  905. void _digitalWrite_LOW_TABLE(void)

  906. {

  907. 	asm volatile (

  908. 		"cbi	%0, %1"					"\n\t"	// pin 0

  909. 		"rjmp	_digitalWrite_OC0B"			"\n\t"

  910. 		"cbi	%2, %3"					"\n\t"	// pin 1

  911. 		"rjmp	_digitalWrite_OC2B"			"\n\t"

  912. 		"cbi	%4, %5"					"\n\t"	// pin 2

  913. 		"ret"						"\n\t"

  914. 		"cbi	%6, %7"					"\n\t"	// pin 3

  915. 		"ret"						"\n\t"

  916. 		"cbi	%8, %9"					"\n\t"	// pin 4

  917. 		"ret"						"\n\t"

  918. 		:: "I" (_SFR_IO_ADDR(CORE_PIN0_PORTREG)), "I" (CORE_PIN0_BIT),

  919. 		   "I" (_SFR_IO_ADDR(CORE_PIN1_PORTREG)), "I" (CORE_PIN1_BIT),

  920. 		   "I" (_SFR_IO_ADDR(CORE_PIN2_PORTREG)), "I" (CORE_PIN2_BIT),

  921. 		   "I" (_SFR_IO_ADDR(CORE_PIN3_PORTREG)), "I" (CORE_PIN3_BIT),

  922. 		   "I" (_SFR_IO_ADDR(CORE_PIN4_PORTREG)), "I" (CORE_PIN4_BIT)

  923. 	);

  924. 	asm volatile (

  925. 		"cbi	%0, %1"					"\n\t"	// pin 5

  926. 		"ret"						"\n\t"

  927. 		"cbi	%2, %3"					"\n\t"	// pin 6

  928. 		"ret"						"\n\t"

  929. 		"cbi	%4, %5"					"\n\t"	// pin 7

  930. 		"ret"						"\n\t"

  931. 		"cbi	%6, %7"					"\n\t"	// pin 8

  932. 		"ret"						"\n\t"

  933. 		"cbi	%8, %9"					"\n\t"	// pin 9

  934. 		"ret"						"\n\t"

  935. 		:: "I" (_SFR_IO_ADDR(CORE_PIN5_PORTREG)), "I" (CORE_PIN5_BIT),

  936. 		   "I" (_SFR_IO_ADDR(CORE_PIN6_PORTREG)), "I" (CORE_PIN6_BIT),

  937. 		   "I" (_SFR_IO_ADDR(CORE_PIN7_PORTREG)), "I" (CORE_PIN7_BIT),

  938. 		   "I" (_SFR_IO_ADDR(CORE_PIN8_PORTREG)), "I" (CORE_PIN8_BIT),

  939. 		   "I" (_SFR_IO_ADDR(CORE_PIN9_PORTREG)), "I" (CORE_PIN9_BIT)

  940. 	);

  941. 	asm volatile (

  942. 		"cbi	%0, %1"					"\n\t"	// pin 10

  943. 		"ret"						"\n\t"

  944. 		"cbi	%2, %3"					"\n\t"	// pin 11

  945. 		"ret"						"\n\t"

  946. 		"cbi	%4, %5"					"\n\t"	// pin 12

  947. 		"ret"						"\n\t"

  948. 		"cbi	%6, %7"					"\n\t"	// pin 13

  949. 		"ret"						"\n\t"

  950. 		"cbi	%8, %9"					"\n\t"	// pin 14

  951. 		"rjmp	_digitalWrite_OC3C"			"\n\t"

  952. 		:: "I" (_SFR_IO_ADDR(CORE_PIN10_PORTREG)), "I" (CORE_PIN10_BIT),

  953. 		   "I" (_SFR_IO_ADDR(CORE_PIN11_PORTREG)), "I" (CORE_PIN11_BIT),

  954. 		   "I" (_SFR_IO_ADDR(CORE_PIN12_PORTREG)), "I" (CORE_PIN12_BIT),

  955. 		   "I" (_SFR_IO_ADDR(CORE_PIN13_PORTREG)), "I" (CORE_PIN13_BIT),

  956. 		   "I" (_SFR_IO_ADDR(CORE_PIN14_PORTREG)), "I" (CORE_PIN14_BIT)

  957. 	);

  958. 	asm volatile (

  959. 		"cbi	%0, %1"					"\n\t"	// pin 15

  960. 		"rjmp	_digitalWrite_OC3B"			"\n\t"

  961. 		"cbi	%2, %3"					"\n\t"	// pin 16

  962. 		"rjmp	_digitalWrite_OC3A"			"\n\t"

  963. 		"cbi	%4, %5"					"\n\t"	// pin 17

  964. 		"ret"						"\n\t"

  965. 		"cbi	%6, %7"					"\n\t"	// pin 18

  966. 		"ret"						"\n\t"

  967. 		"cbi	%8, %9"					"\n\t"	// pin 19

  968. 		"ret"						"\n\t"

  969. 		:: "I" (_SFR_IO_ADDR(CORE_PIN15_PORTREG)), "I" (CORE_PIN15_BIT),

  970. 		   "I" (_SFR_IO_ADDR(CORE_PIN16_PORTREG)), "I" (CORE_PIN16_BIT),

  971. 		   "I" (_SFR_IO_ADDR(CORE_PIN17_PORTREG)), "I" (CORE_PIN17_BIT),

  972. 		   "I" (_SFR_IO_ADDR(CORE_PIN18_PORTREG)), "I" (CORE_PIN18_BIT),

  973. 		   "I" (_SFR_IO_ADDR(CORE_PIN19_PORTREG)), "I" (CORE_PIN19_BIT)

  974. 	);

  975. 	asm volatile (

  976. 		"cbi	%0, %1"					"\n\t"	// pin 20

  977. 		"ret"						"\n\t"

  978. 		"cbi	%2, %3"					"\n\t"	// pin 21

  979. 		"ret"						"\n\t"

  980. 		"cbi	%4, %5"					"\n\t"	// pin 22

  981. 		"ret"						"\n\t"

  982. 		"cbi	%6, %7"					"\n\t"	// pin 23

  983. 		"ret"						"\n\t"

  984. 		"cbi	%8, %9"					"\n\t"	// pin 24

  985. 		"rjmp	_digitalWrite_OC2A"			"\n\t"

  986. 		:: "I" (_SFR_IO_ADDR(CORE_PIN20_PORTREG)), "I" (CORE_PIN20_BIT),

  987. 		   "I" (_SFR_IO_ADDR(CORE_PIN21_PORTREG)), "I" (CORE_PIN21_BIT),

  988. 		   "I" (_SFR_IO_ADDR(CORE_PIN22_PORTREG)), "I" (CORE_PIN22_BIT),

  989. 		   "I" (_SFR_IO_ADDR(CORE_PIN23_PORTREG)), "I" (CORE_PIN23_BIT),

  990. 		   "I" (_SFR_IO_ADDR(CORE_PIN24_PORTREG)), "I" (CORE_PIN24_BIT)

  991. 	);

  992. 	asm volatile (

  993. 		"cbi	%0, %1"					"\n\t"	// pin 25

  994. 		"rjmp	_digitalWrite_OC1A"			"\n\t"

  995. 		"cbi	%2, %3"					"\n\t"	// pin 26

  996. 		"rjmp	_digitalWrite_OC1B"			"\n\t"

  997. 		"cbi	%4, %5"					"\n\t"	// pin 27

  998. 		"rjmp	_digitalWrite_OC1C"			"\n\t"

  999. 		"cbi	%6, %7"					"\n\t"	// pin 28

  1000. 		"ret"						"\n\t"

  1001. 		"cbi	%8, %9"					"\n\t"	// pin 29

  1002. 		"ret"						"\n\t"

  1003. 		:: "I" (_SFR_IO_ADDR(CORE_PIN25_PORTREG)), "I" (CORE_PIN25_BIT),

  1004. 		   "I" (_SFR_IO_ADDR(CORE_PIN26_PORTREG)), "I" (CORE_PIN26_BIT),

  1005. 		   "I" (_SFR_IO_ADDR(CORE_PIN27_PORTREG)), "I" (CORE_PIN27_BIT),

  1006. 		   "I" (_SFR_IO_ADDR(CORE_PIN28_PORTREG)), "I" (CORE_PIN28_BIT),

  1007. 		   "I" (_SFR_IO_ADDR(CORE_PIN29_PORTREG)), "I" (CORE_PIN29_BIT)

  1008. 	);

  1009. 	asm volatile (

  1010. 		"cbi	%0, %1"					"\n\t"	// pin 30

  1011. 		"ret"						"\n\t"

  1012. 		"cbi	%2, %3"					"\n\t"	// pin 31

  1013. 		"ret"						"\n\t"

  1014. 		"cbi	%4, %5"					"\n\t"	// pin 32

  1015. 		"ret"						"\n\t"

  1016. 		"cbi	%6, %7"					"\n\t"	// pin 33

  1017. 		"ret"						"\n\t"

  1018. 		"cbi	%8, %9"					"\n\t"	// pin 34

  1019. 		"ret"						"\n\t"

  1020. 		:: "I" (_SFR_IO_ADDR(CORE_PIN30_PORTREG)), "I" (CORE_PIN30_BIT),

  1021. 		   "I" (_SFR_IO_ADDR(CORE_PIN31_PORTREG)), "I" (CORE_PIN31_BIT),

  1022. 		   "I" (_SFR_IO_ADDR(CORE_PIN32_PORTREG)), "I" (CORE_PIN32_BIT),

  1023. 		   "I" (_SFR_IO_ADDR(CORE_PIN33_PORTREG)), "I" (CORE_PIN33_BIT),

  1024. 		   "I" (_SFR_IO_ADDR(CORE_PIN34_PORTREG)), "I" (CORE_PIN34_BIT)

  1025. 	);

  1026. 	asm volatile (

  1027. 		"cbi	%0, %1"					"\n\t"	// pin 35

  1028. 		"ret"						"\n\t"

  1029. 		"cbi	%2, %3"					"\n\t"	// pin 36

  1030. 		"ret"						"\n\t"

  1031. 		"cbi	%4, %5"					"\n\t"	// pin 37

  1032. 		"ret"						"\n\t"

  1033. 		"cbi	%6, %7"					"\n\t"	// pin 38

  1034. 		"ret"						"\n\t"

  1035. 		"cbi	%8, %9"					"\n\t"	// pin 39

  1036. 		"ret"						"\n\t"

  1037. 		:: "I" (_SFR_IO_ADDR(CORE_PIN35_PORTREG)), "I" (CORE_PIN35_BIT),

  1038. 		   "I" (_SFR_IO_ADDR(CORE_PIN36_PORTREG)), "I" (CORE_PIN36_BIT),

  1039. 		   "I" (_SFR_IO_ADDR(CORE_PIN37_PORTREG)), "I" (CORE_PIN37_BIT),

  1040. 		   "I" (_SFR_IO_ADDR(CORE_PIN38_PORTREG)), "I" (CORE_PIN38_BIT),

  1041. 		   "I" (_SFR_IO_ADDR(CORE_PIN39_PORTREG)), "I" (CORE_PIN39_BIT)

  1042. 	);

  1043. 	asm volatile (

  1044. 		"cbi	%0, %1"					"\n\t"	// pin 40

  1045. 		"ret"						"\n\t"

  1046. 		"cbi	%2, %3"					"\n\t"	// pin 41

  1047. 		"ret"						"\n\t"

  1048. 		"cbi	%4, %5"					"\n\t"	// pin 42

  1049. 		"ret"						"\n\t"

  1050. 		"cbi	%6, %7"					"\n\t"	// pin 43

  1051. 		"ret"						"\n\t"

  1052. 		"cbi	%8, %9"					"\n\t"	// pin 44

  1053. 		"ret"						"\n\t"

  1054. 		"cbi	%10, %11"				"\n\t"	// pin 45

  1055. 		"ret"						"\n\t"

  1056. 		:: "I" (_SFR_IO_ADDR(CORE_PIN40_PORTREG)), "I" (CORE_PIN40_BIT),

  1057. 		   "I" (_SFR_IO_ADDR(CORE_PIN41_PORTREG)), "I" (CORE_PIN41_BIT),

  1058. 		   "I" (_SFR_IO_ADDR(CORE_PIN42_PORTREG)), "I" (CORE_PIN42_BIT),

  1059. 		   "I" (_SFR_IO_ADDR(CORE_PIN43_PORTREG)), "I" (CORE_PIN43_BIT),

  1060. 		   "I" (_SFR_IO_ADDR(CORE_PIN44_PORTREG)), "I" (CORE_PIN44_BIT),

  1061. 		   "I" (_SFR_IO_ADDR(CORE_PIN45_PORTREG)), "I" (CORE_PIN45_BIT)

  1062. 	);

  1063. }

  1064. #endif

  1065. 

  1066. void _digitalWrite_OC0B(void)

  1067. {

  1068. 	asm volatile (

  1069. 		"in	r30, %0"				"\n\t"

  1070. 		"andi	r30, ~(1 << %1)"			"\n\t"

  1071. 		"out	%0, r30"				"\n\t"

  1072. 		"ret"

  1073. 		:: "I" (_SFR_IO_ADDR(TCCR0A)), "I" (COM0B1)

  1074. 	);

  1075. }

  1076. 

  1077. void _digitalWrite_OC1A(void)

  1078. {

  1079. 	asm volatile (

  1080. 		"lds	r30, %0"				"\n\t"

  1081. 		"andi	r30, ~(1 << %1)"			"\n\t"

  1082. 		"sts	%0, r30"				"\n\t"

  1083. 		"ret"

  1084. 		:: "M" (&TCCR1A), "I" (COM1A1)

  1085. 	);

  1086. }

  1087. 

  1088. void _digitalWrite_OC1B(void)

  1089. {

  1090. 	asm volatile (

  1091. 		"lds	r30, %0"				"\n\t"

  1092. 		"andi	r30, ~(1 << %1)"			"\n\t"

  1093. 		"sts	%0, r30"				"\n\t"

  1094. 		"ret"

  1095. 		:: "M" (&TCCR1A), "I" (COM1B1)

  1096. 	);

  1097. }

  1098. 

  1099. void _digitalWrite_OC1C(void)

  1100. {

  1101. 	asm volatile (

  1102. 		"lds	r30, %0"				"\n\t"

  1103. 		"andi	r30, ~(1 << %1)"			"\n\t"

  1104. 		"sts	%0, r30"				"\n\t"

  1105. 		"ret"

  1106. 		:: "M" (&TCCR1A), "I" (COM1C1)

  1107. 	);

  1108. }

  1109. 

  1110. #if defined(__AVR_ATmega32U4__)

  1111. void _digitalWrite_OC3A(void)

  1112. {

  1113. 	asm volatile (

  1114. 		"lds	r30, %0"				"\n\t"

  1115. 		"andi	r30, ~(1 << %1)"			"\n\t"

  1116. 		"sts	%0, r30"				"\n\t"

  1117. 		"ret"

  1118. 		:: "M" (&TCCR3A), "I" (COM3A1)

  1119. 	);

  1120. }

  1121. 

  1122. void _digitalWrite_OC4A(void)

  1123. {

  1124. 	asm volatile (

  1125. 		"lds	r30, %0"				"\n\t"

  1126. 		"andi	r30, ~(1 << %1)"			"\n\t"

  1127. 		"sts	%0, r30"				"\n\t"

  1128. 		"ret"

  1129. 		:: "M" (&TCCR4A), "I" (COM4A1)

  1130. 	);

  1131. }

  1132. 

  1133. void _digitalWrite_OC4D(void)

  1134. {

  1135. 	asm volatile (

  1136. 		"lds	r30, %0"				"\n\t"

  1137. 		"andi	r30, ~(1 << %1)"			"\n\t"

  1138. 		"sts	%0, r30"				"\n\t"

  1139. 		"ret"

  1140. 		:: "M" (&TCCR4C), "I" (COM4D1)

  1141. 	);

  1142. }

  1143. #endif

  1144. #if defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__)

  1145. void _digitalWrite_OC2A(void)

  1146. {

  1147. 	asm volatile (

  1148. 		"lds	r30, %0"				"\n\t"

  1149. 		"andi	r30, ~(1 << %1)"			"\n\t"

  1150. 		"sts	%0, r30"				"\n\t"

  1151. 		"ret"

  1152. 		:: "M" (&TCCR2A), "I" (COM3A1)

  1153. 	);

  1154. }

  1155. 

  1156. void _digitalWrite_OC2B(void)

  1157. {

  1158. 	asm volatile (

  1159. 		"lds	r30, %0"				"\n\t"

  1160. 		"andi	r30, ~(1 << %1)"			"\n\t"

  1161. 		"sts	%0, r30"				"\n\t"

  1162. 		"ret"

  1163. 		:: "M" (&TCCR2A), "I" (COM3B1)

  1164. 	);

  1165. }

  1166. 

  1167. void _digitalWrite_OC3A(void)

  1168. {

  1169. 	asm volatile (

  1170. 		"lds	r30, %0"				"\n\t"

  1171. 		"andi	r30, ~(1 << %1)"			"\n\t"

  1172. 		"sts	%0, r30"				"\n\t"

  1173. 		"ret"

  1174. 		:: "M" (&TCCR3A), "I" (COM3A1)

  1175. 	);

  1176. }

  1177. 

  1178. void _digitalWrite_OC3B(void)

  1179. {

  1180. 	asm volatile (

  1181. 		"lds	r30, %0"				"\n\t"

  1182. 		"andi	r30, ~(1 << %1)"			"\n\t"

  1183. 		"sts	%0, r30"				"\n\t"

  1184. 		"ret"

  1185. 		:: "M" (&TCCR3A), "I" (COM3B1)

  1186. 	);

  1187. }

  1188. 

  1189. void _digitalWrite_OC3C(void)

  1190. {

  1191. 	asm volatile (

  1192. 		"lds	r30, %0"				"\n\t"

  1193. 		"andi	r30, ~(1 << %1)"			"\n\t"

  1194. 		"sts	%0, r30"				"\n\t"

  1195. 		"ret"

  1196. 		:: "M" (&TCCR3A), "I" (COM3C1)

  1197. 	);

  1198. }

  1199. 

  1200. #endif

  1201. 

  1202. void _digitalRead(void) __attribute__((naked));

  1203. void _digitalRead_false(void) __attribute__((naked));

  1204. void _digitalRead_true(void) __attribute__((naked));

  1205. void _digitalRead_TABLE(void) __attribute__((naked));

  1206. void _digitalRead_true2(void) __attribute__((naked));

  1207. void _digitalRead_TABLE2(void) __attribute__((naked));

  1208. 

  1209. void _digitalRead(void)

  1210. {

  1211. 	asm volatile (

  1212. 		#if !defined(DIGITAL_WRITE_RISKY_OMIT_OVERFLOW_CHECK)

  1213. 		"cpi	r30, %0"					"\n\t"

  1214. 		"brsh	_digitalRead_false"				"\n\t"

  1215. 		#endif

  1216. 		"lsl	r30"						"\n\t"

  1217. 		"lsl	r30"						"\n\t"

  1218. 		"clr	r31"						"\n\t"

  1219. 		#if CORE_NUM_TOTAL_PINS > 25

  1220. 		"cpi	r30, 124"					"\n\t"

  1221. 		"brsh	L%=2"						"\n\t"

  1222. 		#endif

  1223. 		"subi	r30, lo8(-(pm(_digitalRead_TABLE)))"		"\n\t"

  1224. 		"sbci	r31, hi8(-(pm(_digitalRead_TABLE)))"		"\n\t"

  1225. 		"ijmp"							"\n"

  1226. 		#if CORE_NUM_TOTAL_PINS > 25

  1227. 		"L%=2:"							"\n\t"

  1228. 		"subi	r30, lo8(-(pm(_digitalRead_TABLE2 - 248)))"	"\n\t"

  1229. 		"sbci	r31, hi8(-(pm(_digitalRead_TABLE2 - 248)))"	"\n\t"

  1230. 		"ijmp"							"\n"

  1231. 		#endif

  1232. 		: : "M" (CORE_NUM_TOTAL_PINS)

  1233. 	);

  1234. }

  1235. 

  1236. #if !defined(DIGITAL_WRITE_RISKY_OMIT_OVERFLOW_CHECK)

  1237. void _digitalRead_false(void)

  1238. {

  1239. 	asm volatile (

  1240. 		"clr	r30"						"\n\t"

  1241. 		"ret"							"\n"

  1242. 	);

  1243. }

  1244. #endif

  1245. 

  1246. void _digitalRead_true(void)

  1247. {

  1248. 	asm volatile (

  1249. 		"ldi	r30, 1"						"\n\t"

  1250. 		"ret"							"\n"

  1251. 	);

  1252. }

  1253. 

  1254. void _digitalRead_TABLE(void)

  1255. {

  1256. 	asm volatile (

  1257. 		"in	r30, %0"				"\n\t"	// pin 0

  1258. 		"andi	r30, %1"				"\n\t"

  1259. 		"brne	_digitalRead_true"			"\n\t"

  1260. 		"ret"						"\n\t"

  1261. 		"in	r30, %2"				"\n\t"	// pin 1

  1262. 		"andi	r30, %3"				"\n\t"

  1263. 		"brne	_digitalRead_true"			"\n\t"

  1264. 		"ret"						"\n\t"

  1265. 		"in	r30, %4"				"\n\t"	// pin 2

  1266. 		"andi	r30, %5"				"\n\t"

  1267. 		"brne	_digitalRead_true"			"\n\t"

  1268. 		"ret"						"\n\t"

  1269. 		"in	r30, %6"				"\n\t"	// pin 3

  1270. 		"andi	r30, %7"				"\n\t"

  1271. 		"brne	_digitalRead_true"			"\n\t"

  1272. 		"ret"						"\n\t"

  1273. 		"in	r30, %8"				"\n\t"	// pin 4

  1274. 		"andi	r30, %9"				"\n\t"

  1275. 		"brne	_digitalRead_true"			"\n\t"

  1276. 		"ret"						"\n\t"

  1277. 		:: "I" (_SFR_IO_ADDR(CORE_PIN0_PINREG)), "M" (CORE_PIN0_BITMASK),

  1278. 		   "I" (_SFR_IO_ADDR(CORE_PIN1_PINREG)), "M" (CORE_PIN1_BITMASK),

  1279. 		   "I" (_SFR_IO_ADDR(CORE_PIN2_PINREG)), "M" (CORE_PIN2_BITMASK),

  1280. 		   "I" (_SFR_IO_ADDR(CORE_PIN3_PINREG)), "M" (CORE_PIN3_BITMASK),

  1281. 		   "I" (_SFR_IO_ADDR(CORE_PIN4_PINREG)), "M" (CORE_PIN4_BITMASK)

  1282. 	);

  1283. 	asm volatile (

  1284. 		"in	r30, %0"				"\n\t"	// pin 5

  1285. 		"andi	r30, %1"				"\n\t"

  1286. 		"brne	_digitalRead_true"			"\n\t"

  1287. 		"ret"						"\n\t"

  1288. 		"in	r30, %2"				"\n\t"	// pin 6

  1289. 		"andi	r30, %3"				"\n\t"

  1290. 		"brne	_digitalRead_true"			"\n\t"

  1291. 		"ret"						"\n\t"

  1292. 		"in	r30, %4"				"\n\t"	// pin 7

  1293. 		"andi	r30, %5"				"\n\t"

  1294. 		"brne	_digitalRead_true"			"\n\t"

  1295. 		"ret"						"\n\t"

  1296. 		"in	r30, %6"				"\n\t"	// pin 8

  1297. 		"andi	r30, %7"				"\n\t"

  1298. 		"brne	_digitalRead_true"			"\n\t"

  1299. 		"ret"						"\n\t"

  1300. 		"in	r30, %8"				"\n\t"	// pin 9

  1301. 		"andi	r30, %9"				"\n\t"

  1302. 		"brne	_digitalRead_true"			"\n\t"

  1303. 		"ret"						"\n\t"

  1304. 		:: "I" (_SFR_IO_ADDR(CORE_PIN5_PINREG)), "M" (CORE_PIN5_BITMASK),

  1305. 		   "I" (_SFR_IO_ADDR(CORE_PIN6_PINREG)), "M" (CORE_PIN6_BITMASK),

  1306. 		   "I" (_SFR_IO_ADDR(CORE_PIN7_PINREG)), "M" (CORE_PIN7_BITMASK),

  1307. 		   "I" (_SFR_IO_ADDR(CORE_PIN8_PINREG)), "M" (CORE_PIN8_BITMASK),

  1308. 		   "I" (_SFR_IO_ADDR(CORE_PIN9_PINREG)), "M" (CORE_PIN9_BITMASK)

  1309. 	);

  1310. 	asm volatile (

  1311. 		"in	r30, %0"				"\n\t"	// pin 10

  1312. 		"andi	r30, %1"				"\n\t"

  1313. 		"brne	_digitalRead_true"			"\n\t"

  1314. 		"ret"						"\n\t"

  1315. 		"in	r30, %2"				"\n\t"	// pin 11

  1316. 		"andi	r30, %3"				"\n\t"

  1317. 		"brne	_digitalRead_true"			"\n\t"

  1318. 		"ret"						"\n\t"

  1319. 		"in	r30, %4"				"\n\t"	// pin 12

  1320. 		"andi	r30, %5"				"\n\t"

  1321. 		"brne	_digitalRead_true"			"\n\t"

  1322. 		"ret"						"\n\t"

  1323. 		"in	r30, %6"				"\n\t"	// pin 13

  1324. 		"andi	r30, %7"				"\n\t"

  1325. 		"brne	_digitalRead_true"			"\n\t"

  1326. 		"ret"						"\n\t"

  1327. 		"in	r30, %8"				"\n\t"	// pin 14

  1328. 		"andi	r30, %9"				"\n\t"

  1329. 		"brne	_digitalRead_true"			"\n\t"

  1330. 		"ret"						"\n\t"

  1331. 		:: "I" (_SFR_IO_ADDR(CORE_PIN10_PINREG)), "M" (CORE_PIN10_BITMASK),

  1332. 		   "I" (_SFR_IO_ADDR(CORE_PIN11_PINREG)), "M" (CORE_PIN11_BITMASK),

  1333. 		   "I" (_SFR_IO_ADDR(CORE_PIN12_PINREG)), "M" (CORE_PIN12_BITMASK),

  1334. 		   "I" (_SFR_IO_ADDR(CORE_PIN13_PINREG)), "M" (CORE_PIN13_BITMASK),

  1335. 		   "I" (_SFR_IO_ADDR(CORE_PIN14_PINREG)), "M" (CORE_PIN14_BITMASK)

  1336. 	);

  1337. 	asm volatile (

  1338. 		"in	r30, %0"				"\n\t"	// pin 15

  1339. 		"andi	r30, %1"				"\n\t"

  1340. 		"brne	_digitalRead_true2"			"\n\t"

  1341. 		"ret"						"\n\t"

  1342. 		"in	r30, %2"				"\n\t"	// pin 16

  1343. 		"andi	r30, %3"				"\n\t"

  1344. 		"brne	_digitalRead_true2"			"\n\t"

  1345. 		"ret"						"\n\t"

  1346. 		"in	r30, %4"				"\n\t"	// pin 17

  1347. 		"andi	r30, %5"				"\n\t"

  1348. 		"brne	_digitalRead_true2"			"\n\t"

  1349. 		"ret"						"\n\t"

  1350. 		"in	r30, %6"				"\n\t"	// pin 18

  1351. 		"andi	r30, %7"				"\n\t"

  1352. 		"brne	_digitalRead_true2"			"\n\t"

  1353. 		"ret"						"\n\t"

  1354. 		"in	r30, %8"				"\n\t"	// pin 19

  1355. 		"andi	r30, %9"				"\n\t"

  1356. 		"brne	_digitalRead_true2"			"\n\t"

  1357. 		"ret"						"\n\t"

  1358. 		"in	r30, %10"				"\n\t"	// pin 20

  1359. 		"andi	r30, %11"				"\n\t"

  1360. 		"brne	_digitalRead_true2"			"\n\t"

  1361. 		"ret"						"\n\t"

  1362. 		:: "I" (_SFR_IO_ADDR(CORE_PIN15_PINREG)), "M" (CORE_PIN15_BITMASK),

  1363. 		   "I" (_SFR_IO_ADDR(CORE_PIN16_PINREG)), "M" (CORE_PIN16_BITMASK),

  1364. 		   "I" (_SFR_IO_ADDR(CORE_PIN17_PINREG)), "M" (CORE_PIN17_BITMASK),

  1365. 		   "I" (_SFR_IO_ADDR(CORE_PIN18_PINREG)), "M" (CORE_PIN18_BITMASK),

  1366. 		   "I" (_SFR_IO_ADDR(CORE_PIN19_PINREG)), "M" (CORE_PIN19_BITMASK),

  1367. 		   "I" (_SFR_IO_ADDR(CORE_PIN20_PINREG)), "M" (CORE_PIN20_BITMASK)

  1368. 	);

  1369. 	#if CORE_NUM_TOTAL_PINS > 21

  1370. 	asm volatile (

  1371. 		"in	r30, %0"				"\n\t"	// pin 21

  1372. 		"andi	r30, %1"				"\n\t"

  1373. 		"brne	_digitalRead_true2"			"\n\t"

  1374. 		"ret"						"\n\t"

  1375. 		"in	r30, %2"				"\n\t"	// pin 22

  1376. 		"andi	r30, %3"				"\n\t"

  1377. 		"brne	_digitalRead_true2"			"\n\t"

  1378. 		"ret"						"\n\t"

  1379. 		"in	r30, %4"				"\n\t"	// pin 23

  1380. 		"andi	r30, %5"				"\n\t"

  1381. 		"brne	_digitalRead_true2"			"\n\t"

  1382. 		"ret"						"\n\t"

  1383. 		"in	r30, %6"				"\n\t"	// pin 24

  1384. 		"andi	r30, %7"				"\n\t"

  1385. 		"brne	_digitalRead_true2"			"\n\t"

  1386. 		"ret"						"\n\t"

  1387. 		:: "I" (_SFR_IO_ADDR(CORE_PIN21_PINREG)), "M" (CORE_PIN21_BITMASK),

  1388. 		   "I" (_SFR_IO_ADDR(CORE_PIN22_PINREG)), "M" (CORE_PIN22_BITMASK),

  1389. 		   "I" (_SFR_IO_ADDR(CORE_PIN23_PINREG)), "M" (CORE_PIN23_BITMASK),

  1390. 		   "I" (_SFR_IO_ADDR(CORE_PIN24_PINREG)), "M" (CORE_PIN24_BITMASK)

  1391. 	);

  1392. 	#endif

  1393. 	#if CORE_NUM_TOTAL_PINS > 25

  1394. 	asm volatile (

  1395. 		"in	r30, %0"				"\n\t"	// pin 25

  1396. 		"andi	r30, %1"				"\n\t"

  1397. 		"brne	_digitalRead_true2"			"\n\t"

  1398. 		"ret"						"\n\t"

  1399. 		"in	r30, %2"				"\n\t"	// pin 26

  1400. 		"andi	r30, %3"				"\n\t"

  1401. 		"brne	_digitalRead_true2"			"\n\t"

  1402. 		"ret"						"\n\t"

  1403. 		"in	r30, %4"				"\n\t"	// pin 27

  1404. 		"andi	r30, %5"				"\n\t"

  1405. 		"brne	_digitalRead_true2"			"\n\t"

  1406. 		"ret"						"\n\t"

  1407. 		"in	r30, %6"				"\n\t"	// pin 28

  1408. 		"andi	r30, %7"				"\n\t"

  1409. 		"brne	_digitalRead_true2"			"\n\t"

  1410. 		"ret"						"\n\t"

  1411. 		"in	r30, %8"				"\n\t"	// pin 29

  1412. 		"andi	r30, %9"				"\n\t"

  1413. 		"brne	_digitalRead_true2"			"\n\t"

  1414. 		"ret"						"\n\t"

  1415. 		"in	r30, %10"				"\n\t"	// pin 30

  1416. 		"andi	r30, %11"				"\n\t"

  1417. 		"brne	_digitalRead_true2"			"\n\t"

  1418. 		"ret"						"\n\t"

  1419. 		:: "I" (_SFR_IO_ADDR(CORE_PIN25_PINREG)), "M" (CORE_PIN25_BITMASK),

  1420. 		   "I" (_SFR_IO_ADDR(CORE_PIN26_PINREG)), "M" (CORE_PIN26_BITMASK),

  1421. 		   "I" (_SFR_IO_ADDR(CORE_PIN27_PINREG)), "M" (CORE_PIN27_BITMASK),

  1422. 		   "I" (_SFR_IO_ADDR(CORE_PIN28_PINREG)), "M" (CORE_PIN28_BITMASK),

  1423. 		   "I" (_SFR_IO_ADDR(CORE_PIN29_PINREG)), "M" (CORE_PIN29_BITMASK),

  1424. 		   "I" (_SFR_IO_ADDR(CORE_PIN30_PINREG)), "M" (CORE_PIN30_BITMASK)

  1425. 	);

  1426. 	#endif

  1427. }

  1428. 

  1429. void _digitalRead_true2(void)

  1430. {

  1431. 	asm volatile (

  1432. 		"ldi	r30, 1"						"\n\t"

  1433. 		"ret"							"\n"

  1434. 	);

  1435. }

  1436. 

  1437. #if CORE_NUM_TOTAL_PINS > 25

  1438. void _digitalRead_TABLE2(void)

  1439. {

  1440. 	asm volatile (

  1441. 		"in	r30, %0"				"\n\t"	// pin 31

  1442. 		"andi	r30, %1"				"\n\t"

  1443. 		"brne	_digitalRead_true2"			"\n\t"

  1444. 		"ret"						"\n\t"

  1445. 		"in	r30, %2"				"\n\t"	// pin 32

  1446. 		"andi	r30, %3"				"\n\t"

  1447. 		"brne	_digitalRead_true2"			"\n\t"

  1448. 		"ret"						"\n\t"

  1449. 		"in	r30, %4"				"\n\t"	// pin 33

  1450. 		"andi	r30, %5"				"\n\t"

  1451. 		"brne	_digitalRead_true2"			"\n\t"

  1452. 		"ret"						"\n\t"

  1453. 		"in	r30, %6"				"\n\t"	// pin 34

  1454. 		"andi	r30, %7"				"\n\t"

  1455. 		"brne	_digitalRead_true2"			"\n\t"

  1456. 		"ret"						"\n\t"

  1457. 		:: "I" (_SFR_IO_ADDR(CORE_PIN31_PINREG)), "M" (CORE_PIN31_BITMASK),

  1458. 		   "I" (_SFR_IO_ADDR(CORE_PIN32_PINREG)), "M" (CORE_PIN32_BITMASK),

  1459. 		   "I" (_SFR_IO_ADDR(CORE_PIN33_PINREG)), "M" (CORE_PIN33_BITMASK),

  1460. 		   "I" (_SFR_IO_ADDR(CORE_PIN34_PINREG)), "M" (CORE_PIN34_BITMASK)

  1461. 	);

  1462. 	asm volatile (

  1463. 		"in	r30, %0"				"\n\t"	// pin 35

  1464. 		"andi	r30, %1"				"\n\t"

  1465. 		"brne	_digitalRead_true2"			"\n\t"

  1466. 		"ret"						"\n\t"

  1467. 		"in	r30, %2"				"\n\t"	// pin 36

  1468. 		"andi	r30, %3"				"\n\t"

  1469. 		"brne	_digitalRead_true2"			"\n\t"

  1470. 		"ret"						"\n\t"

  1471. 		"in	r30, %4"				"\n\t"	// pin 37

  1472. 		"andi	r30, %5"				"\n\t"

  1473. 		"brne	_digitalRead_true2"			"\n\t"

  1474. 		"ret"						"\n\t"

  1475. 		"in	r30, %6"				"\n\t"	// pin 38

  1476. 		"andi	r30, %7"				"\n\t"

  1477. 		"brne	_digitalRead_true2"			"\n\t"

  1478. 		"ret"						"\n\t"

  1479. 		"in	r30, %8"				"\n\t"	// pin 39

  1480. 		"andi	r30, %9"				"\n\t"

  1481. 		"brne	_digitalRead_true2"			"\n\t"

  1482. 		"ret"						"\n\t"

  1483. 		:: "I" (_SFR_IO_ADDR(CORE_PIN35_PINREG)), "M" (CORE_PIN35_BITMASK),

  1484. 		   "I" (_SFR_IO_ADDR(CORE_PIN36_PINREG)), "M" (CORE_PIN36_BITMASK),

  1485. 		   "I" (_SFR_IO_ADDR(CORE_PIN37_PINREG)), "M" (CORE_PIN37_BITMASK),

  1486. 		   "I" (_SFR_IO_ADDR(CORE_PIN38_PINREG)), "M" (CORE_PIN38_BITMASK),

  1487. 		   "I" (_SFR_IO_ADDR(CORE_PIN39_PINREG)), "M" (CORE_PIN39_BITMASK)

  1488. 	);

  1489. 	asm volatile (

  1490. 		"in	r30, %0"				"\n\t"	// pin 40

  1491. 		"andi	r30, %1"				"\n\t"

  1492. 		"brne	_digitalRead_true2"			"\n\t"

  1493. 		"ret"						"\n\t"

  1494. 		"in	r30, %2"				"\n\t"	// pin 41

  1495. 		"andi	r30, %3"				"\n\t"

  1496. 		"brne	_digitalRead_true2"			"\n\t"

  1497. 		"ret"						"\n\t"

  1498. 		"in	r30, %4"				"\n\t"	// pin 42

  1499. 		"andi	r30, %5"				"\n\t"

  1500. 		"brne	_digitalRead_true2"			"\n\t"

  1501. 		"ret"						"\n\t"

  1502. 		"in	r30, %6"				"\n\t"	// pin 43

  1503. 		"andi	r30, %7"				"\n\t"

  1504. 		"brne	_digitalRead_true2"			"\n\t"

  1505. 		"ret"						"\n\t"

  1506. 		"in	r30, %8"				"\n\t"	// pin 44

  1507. 		"andi	r30, %9"				"\n\t"

  1508. 		"brne	_digitalRead_true2"			"\n\t"

  1509. 		"ret"						"\n\t"

  1510. 		"in	r30, %10"				"\n\t"	// pin 45

  1511. 		"andi	r30, %11"				"\n\t"

  1512. 		"brne	_digitalRead_true2"			"\n\t"

  1513. 		"ret"						"\n\t"

  1514. 		:: "I" (_SFR_IO_ADDR(CORE_PIN40_PINREG)), "M" (CORE_PIN40_BITMASK),

  1515. 		   "I" (_SFR_IO_ADDR(CORE_PIN41_PINREG)), "M" (CORE_PIN41_BITMASK),

  1516. 		   "I" (_SFR_IO_ADDR(CORE_PIN42_PINREG)), "M" (CORE_PIN42_BITMASK),

  1517. 		   "I" (_SFR_IO_ADDR(CORE_PIN43_PINREG)), "M" (CORE_PIN43_BITMASK),

  1518. 		   "I" (_SFR_IO_ADDR(CORE_PIN44_PINREG)), "M" (CORE_PIN44_BITMASK),

  1519. 		   "I" (_SFR_IO_ADDR(CORE_PIN45_PINREG)), "M" (CORE_PIN45_BITMASK)

  1520. 	);

  1521. }

  1522. #endif

  1523. 

  1524. 

  1525. 

  1526. const uint8_t PROGMEM digital_pin_table_PGM[] = {

  1527. 	CORE_PIN0_BITMASK,	(int)&CORE_PIN0_PINREG,

  1528. 	CORE_PIN1_BITMASK,	(int)&CORE_PIN1_PINREG,

  1529. 	CORE_PIN2_BITMASK,	(int)&CORE_PIN2_PINREG,

  1530. 	CORE_PIN3_BITMASK,	(int)&CORE_PIN3_PINREG,

  1531. 	CORE_PIN4_BITMASK,	(int)&CORE_PIN4_PINREG,

  1532. 	CORE_PIN5_BITMASK,	(int)&CORE_PIN5_PINREG,

  1533. 	CORE_PIN6_BITMASK,	(int)&CORE_PIN6_PINREG,

  1534. 	CORE_PIN7_BITMASK,	(int)&CORE_PIN7_PINREG,

  1535. 	CORE_PIN8_BITMASK,	(int)&CORE_PIN8_PINREG,

  1536. 	CORE_PIN9_BITMASK,	(int)&CORE_PIN9_PINREG,

  1537. 	CORE_PIN10_BITMASK,	(int)&CORE_PIN10_PINREG,

  1538. 	CORE_PIN11_BITMASK,	(int)&CORE_PIN11_PINREG,

  1539. 	CORE_PIN12_BITMASK,	(int)&CORE_PIN12_PINREG,

  1540. 	CORE_PIN13_BITMASK,	(int)&CORE_PIN13_PINREG,

  1541. 	CORE_PIN14_BITMASK,	(int)&CORE_PIN14_PINREG,

  1542. 	CORE_PIN15_BITMASK,	(int)&CORE_PIN15_PINREG,

  1543. 	CORE_PIN16_BITMASK,	(int)&CORE_PIN16_PINREG,

  1544. 	CORE_PIN17_BITMASK,	(int)&CORE_PIN17_PINREG,

  1545. 	CORE_PIN18_BITMASK,	(int)&CORE_PIN18_PINREG,

  1546. 	CORE_PIN19_BITMASK,	(int)&CORE_PIN19_PINREG,

  1547. 	CORE_PIN20_BITMASK,	(int)&CORE_PIN20_PINREG,

  1548. 	#if CORE_NUM_TOTAL_PINS > 21

  1549. 	CORE_PIN21_BITMASK,	(int)&CORE_PIN21_PINREG,

  1550. 	CORE_PIN22_BITMASK,	(int)&CORE_PIN22_PINREG,

  1551. 	CORE_PIN23_BITMASK,	(int)&CORE_PIN23_PINREG,

  1552. 	CORE_PIN24_BITMASK,	(int)&CORE_PIN24_PINREG,

  1553. 	#endif

  1554. 	#if CORE_NUM_TOTAL_PINS > 25

  1555. 	CORE_PIN25_BITMASK,	(int)&CORE_PIN25_PINREG,

  1556. 	CORE_PIN26_BITMASK,	(int)&CORE_PIN26_PINREG,

  1557. 	CORE_PIN27_BITMASK,	(int)&CORE_PIN27_PINREG,

  1558. 	CORE_PIN28_BITMASK,	(int)&CORE_PIN28_PINREG,

  1559. 	CORE_PIN29_BITMASK,	(int)&CORE_PIN29_PINREG,

  1560. 	CORE_PIN30_BITMASK,	(int)&CORE_PIN30_PINREG,

  1561. 	CORE_PIN31_BITMASK,	(int)&CORE_PIN31_PINREG,

  1562. 	CORE_PIN32_BITMASK,	(int)&CORE_PIN32_PINREG,

  1563. 	CORE_PIN33_BITMASK,	(int)&CORE_PIN33_PINREG,

  1564. 	CORE_PIN34_BITMASK,	(int)&CORE_PIN34_PINREG,

  1565. 	CORE_PIN35_BITMASK,	(int)&CORE_PIN35_PINREG,

  1566. 	CORE_PIN36_BITMASK,	(int)&CORE_PIN36_PINREG,

  1567. 	CORE_PIN37_BITMASK,	(int)&CORE_PIN37_PINREG,

  1568. 	CORE_PIN38_BITMASK,	(int)&CORE_PIN38_PINREG,

  1569. 	CORE_PIN39_BITMASK,	(int)&CORE_PIN39_PINREG,

  1570. 	CORE_PIN40_BITMASK,	(int)&CORE_PIN40_PINREG,

  1571. 	CORE_PIN41_BITMASK,	(int)&CORE_PIN41_PINREG,

  1572. 	CORE_PIN42_BITMASK,	(int)&CORE_PIN42_PINREG,

  1573. 	CORE_PIN43_BITMASK,	(int)&CORE_PIN43_PINREG,

  1574. 	CORE_PIN44_BITMASK,	(int)&CORE_PIN44_PINREG,

  1575. 	CORE_PIN45_BITMASK,	(int)&CORE_PIN45_PINREG

  1576.         #endif

  1577. };

  1578. 

  1579. void _shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t value)

  1580. {

  1581. 	if (bitOrder == LSBFIRST) {

  1582. 		shiftOut_lsbFirst(dataPin, clockPin, value);

  1583. 	} else {

  1584. 		shiftOut_msbFirst(dataPin, clockPin, value);

  1585. 	}

  1586. }

  1587. 

  1588. void shiftOut_lsbFirst(uint8_t dataPin, uint8_t clockPin, uint8_t value)

  1589. {

  1590. 	uint8_t mask;

  1591. 	for (mask=0x01; mask; mask <<= 1) {

  1592. 		digitalWrite(dataPin, value & mask);

  1593. 		digitalWrite(clockPin, HIGH);

  1594. 		digitalWrite(clockPin, LOW);

  1595. 	}

  1596. }

  1597. 

  1598. void shiftOut_msbFirst(uint8_t dataPin, uint8_t clockPin, uint8_t value)

  1599. {

  1600. 	uint8_t mask;

  1601. 	for (mask=0x80; mask; mask >>= 1) {

  1602. 		digitalWrite(dataPin, value & mask);

  1603. 		digitalWrite(clockPin, HIGH);

  1604. 		digitalWrite(clockPin, LOW);

  1605. 	}

  1606. }

  1607. 

  1608. uint8_t _shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder)

  1609. {

  1610. 	if (bitOrder == LSBFIRST) {

  1611. 		return shiftIn_lsbFirst(dataPin, clockPin);

  1612. 	} else {

  1613. 		return shiftIn_msbFirst(dataPin, clockPin);

  1614. 	}

  1615. }

  1616. 

  1617. uint8_t shiftIn_lsbFirst(uint8_t dataPin, uint8_t clockPin)

  1618. {

  1619. 	uint8_t mask, value=0;

  1620. 	for (mask=0x01; mask; mask <<= 1) {

  1621. 		digitalWrite(clockPin, HIGH);

  1622. 		if (digitalRead(dataPin)) value |= mask;

  1623. 		digitalWrite(clockPin, LOW);

  1624. 	}

  1625. 	return value;

  1626. }

  1627. 

  1628. uint8_t shiftIn_msbFirst(uint8_t dataPin, uint8_t clockPin)

  1629. {

  1630. 	uint8_t mask, value=0;

  1631. 	for (mask=0x80; mask; mask >>= 1) {

  1632. 		digitalWrite(clockPin, HIGH);

  1633. 		if (digitalRead(dataPin)) value |= mask;

  1634. 		digitalWrite(clockPin, LOW);

  1635. 	}

  1636. 	return value;

  1637. }

  1638. 

  1639. static void disable_peripherals(void) __attribute__((noinline));

  1640. static void disable_peripherals(void)

  1641. {

  1642. 	#if defined(__AVR_AT90USB162__)

  1643. 	EIMSK = 0; PCICR = 0; SPCR = 0; ACSR = 0; EECR = 0;

  1644. 	TIMSK0 = 0; TIMSK1 = 0; UCSR1B = 0;

  1645. 	DDRB = 0; DDRC = 0; DDRD = 0;

  1646. 	PORTB = 0; PORTC = 0; PORTD = 0;

  1647. 	#elif defined(__AVR_ATmega32U4__)

  1648. 	EIMSK = 0; PCICR = 0; SPCR = 0; ACSR = 0; EECR = 0; ADCSRA = 0;

  1649. 	TIMSK0 = 0; TIMSK1 = 0; TIMSK3 = 0; TIMSK4 = 0; UCSR1B = 0; TWCR = 0;

  1650. 	DDRB = 0; DDRC = 0; DDRD = 0; DDRE = 0; DDRF = 0; TWCR = 0;

  1651. 	PORTB = 0; PORTC = 0; PORTD = 0; PORTE = 0; PORTF = 0;

  1652. 	#elif defined(__AVR_AT90USB646__)

  1653. 	EIMSK = 0; PCICR = 0; SPCR = 0; ACSR = 0; EECR = 0; ADCSRA = 0;

  1654. 	TIMSK0 = 0; TIMSK1 = 0; TIMSK2 = 0; TIMSK3 = 0; UCSR1B = 0; TWCR = 0;

  1655. 	DDRA = 0; DDRB = 0; DDRC = 0; DDRD = 0; DDRE = 0; DDRF = 0;

  1656. 	PORTA = 0; PORTB = 0; PORTC = 0; PORTD = 0; PORTE = 0; PORTF = 0;

  1657. 	#elif defined(__AVR_AT90USB1286__)

  1658. 	EIMSK = 0; PCICR = 0; SPCR = 0; ACSR = 0; EECR = 0; ADCSRA = 0;

  1659. 	TIMSK0 = 0; TIMSK1 = 0; TIMSK2 = 0; TIMSK3 = 0; UCSR1B = 0; TWCR = 0;

  1660. 	DDRA = 0; DDRB = 0; DDRC = 0; DDRD = 0; DDRE = 0; DDRF = 0;

  1661. 	PORTA = 0; PORTB = 0; PORTC = 0; PORTD = 0; PORTE = 0; PORTF = 0;

  1662. 	#endif

  1663. }

  1664. 

  1665. 

  1666. void _reboot_Teensyduino_(void)

  1667. {

  1668. 	cli();

  1669. 	delayMicroseconds(5000);

  1670. 	UDCON = 1;

  1671. 	USBCON = (1<<FRZCLK);

  1672. 	delayMicroseconds(15000);

  1673. 	disable_peripherals();

  1674. 	#if defined(__AVR_AT90USB162__)

  1675. 	asm volatile("jmp 0x3E00");

  1676. 	#elif defined(__AVR_ATmega32U4__)

  1677. 	asm volatile("jmp 0x7E00");

  1678. 	#elif defined(__AVR_AT90USB646__)

  1679. 	asm volatile("jmp 0xFC00");

  1680. 	#elif defined(__AVR_AT90USB1286__)

  1681. 	asm volatile("jmp 0x1FC00");

  1682. 	#endif

  1683. 	//__builtin_unreachable();  // available in gcc 4.5

  1684. 	while (1) ;

  1685. }

  1686. 

  1687. void _restart_Teensyduino_(void)

  1688. {

  1689. 	cli();

  1690. 	disable_peripherals();  // but leave USB intact

  1691. 	delayMicroseconds(15000);

  1692. 	asm volatile("jmp 0");

  1693. 	//__builtin_unreachable();  // available in gcc 4.5

  1694. 	while (1) ;

  1695. }

  1696. 

  1697. 

  1698. 

  1699. #if F_CPU == 16000000L

  1700.   #define TIMER0_MILLIS_INC  	1

  1701.   #define TIMER0_FRACT_INC	3

  1702.   #define TIMER0_MICROS_INC  	4

  1703. #elif F_CPU == 8000000L

  1704.   #define TIMER0_MILLIS_INC  	2

  1705.   #define TIMER0_FRACT_INC	6

  1706.   #define TIMER0_MICROS_INC  	8

  1707. #elif F_CPU == 4000000L

  1708.   #define TIMER0_MILLIS_INC  	4

  1709.   #define TIMER0_FRACT_INC	12

  1710.   #define TIMER0_MICROS_INC  	16

  1711. #elif F_CPU == 2000000L

  1712.   #define TIMER0_MILLIS_INC  	8

  1713.   #define TIMER0_FRACT_INC	24

  1714.   #define TIMER0_MICROS_INC  	32

  1715. #elif F_CPU == 1000000L

  1716.   #define TIMER0_MILLIS_INC  	16

  1717.   #define TIMER0_FRACT_INC	48

  1718.   #define TIMER0_MICROS_INC  	64

  1719. #endif

  1720. 

  1721. volatile unsigned long timer0_micros_count = 0;

  1722. volatile unsigned long timer0_millis_count = 0;

  1723. volatile unsigned char timer0_fract_count = 0;

  1724. 

  1725. void TIMER0_OVF_vect() __attribute__((naked));

  1726. void TIMER0_OVF_vect()

  1727. {

  1728. 	asm volatile(

  1729. 		"push	r24"				"\n\t"

  1730. 		"in	r24, __SREG__"			"\n\t"

  1731. 		"push	r24"				"\n\t"

  1732. 

  1733. 		"lds	r24, timer0_fract_count"	"\n\t"

  1734. 		"subi	r24, 256 - %0"			"\n\t"

  1735. 		"cpi	r24, 125"			"\n\t"

  1736. 		"brsh	L_%=_fract_roll"		"\n\t"

  1737. 

  1738. 	"L_%=_fract_noroll:"				"\n\t"

  1739. 		"sts	timer0_fract_count, r24"	"\n\t"

  1740. 		"lds	r24, timer0_millis_count"	"\n\t"

  1741. 		"subi	r24, 256 - %1"			"\n\t"

  1742. 		"sts	timer0_millis_count, r24"	"\n\t"

  1743. 		"brcs	L_%=_ovcount"			"\n\t"

  1744. 

  1745. 	"L_%=_millis_inc_sext:"

  1746. 		"lds	r24, timer0_millis_count+1"	"\n\t"

  1747. 		"sbci	r24, 255"			"\n\t"

  1748. 		"sts	timer0_millis_count+1, r24"	"\n\t"

  1749. 		"brcs	L_%=_ovcount"			"\n\t"

  1750. 		"lds	r24, timer0_millis_count+2"	"\n\t"

  1751. 		"sbci	r24, 255"			"\n\t"

  1752. 		"sts	timer0_millis_count+2, r24"	"\n\t"

  1753. 		"brcs	L_%=_ovcount"			"\n\t"

  1754. 		"lds	r24, timer0_millis_count+3"	"\n\t"

  1755. 		"sbci	r24, 255"			"\n\t"

  1756. 		"sts	timer0_millis_count+3, r24"	"\n\t"

  1757. 		"rjmp	L_%=_ovcount"			"\n\t"

  1758. 

  1759. 	"L_%=_fract_roll:"				"\n\t"

  1760. 		"subi	r24, 125"			"\n\t"

  1761. 		"sts	timer0_fract_count, r24"	"\n\t"

  1762. 		"lds	r24, timer0_millis_count"	"\n\t"

  1763. 		"subi	r24, 256 - %1 - 1"		"\n\t"

  1764. 		"sts	timer0_millis_count, r24"	"\n\t"

  1765. 		"brcc	L_%=_millis_inc_sext"		"\n\t"

  1766. 

  1767. 	"L_%=_ovcount:"

  1768. 		"lds	r24, timer0_micros_count"	"\n\t"

  1769. 		"subi	r24, 256 - %2"			"\n\t"

  1770. 		"sts	timer0_micros_count, r24"	"\n\t"

  1771. 		"brcs	L_%=_end"			"\n\t"

  1772. 		"lds	r24, timer0_micros_count+1"	"\n\t"

  1773. 		"sbci	r24, 255"			"\n\t"

  1774. 		"sts	timer0_micros_count+1, r24"	"\n\t"

  1775. 		"brcs	L_%=_end"			"\n\t"

  1776. 		"lds	r24, timer0_micros_count+2"	"\n\t"

  1777. 		"sbci	r24, 255"			"\n\t"

  1778. 		"sts	timer0_micros_count+2, r24"	"\n\t"

  1779. 

  1780. 	"L_%=_end:"

  1781. 		"pop	r24"				"\n\t"

  1782. 		"out	__SREG__, r24"			"\n\t"

  1783. 		"pop	r24"				"\n\t"

  1784. 		"reti"

  1785. 		: 

  1786. 		: "M" (TIMER0_FRACT_INC), "M" (TIMER0_MILLIS_INC),

  1787. 		  "M" (TIMER0_MICROS_INC)

  1788. 	);

  1789. }

  1790. 

  1791. 

  1792. void delay(uint32_t ms)

  1793. {

  1794. 	uint16_t start = (uint16_t)micros();

  1795. 

  1796. 	while (ms > 0) {

  1797. 		if (((uint16_t)micros() - start) >= 1000) {

  1798. 			ms--;

  1799. 			start += 1000;

  1800. 		}

  1801. 	}

  1802. #if 0

  1803. 	// This doesn't save a lot of power on Teensy, which

  1804. 	// lacks the power saving flash memory of some newer

  1805. 	// chips, and also usually consumes lots of power for

  1806. 	// the USB port.  There is also some strange (probably

  1807. 	// hardware) bug involving the A/D mux for the first

  1808. 	// conversion after the processor wakes from idle mode.

  1809. 	uint32_t start;

  1810. 	if (!(SREG & 0x80)) {

  1811. 		// if interrupts are disabled, busy loop

  1812. 		while (ms--) delayMicroseconds(1000);

  1813. 		return;

  1814. 	}

  1815. 	// if interrupt are enabled, use low power idle mode

  1816. 	cli();

  1817. 	start = timer0_millis_count;

  1818. 	do {

  1819. 		_SLEEP_CONTROL_REG = SLEEP_MODE_IDLE | _SLEEP_ENABLE_MASK;

  1820. 		sei();

  1821. 		sleep_cpu();

  1822. 		_SLEEP_CONTROL_REG = SLEEP_MODE_IDLE;

  1823. 		cli();

  1824. 	} while (timer0_millis_count - start <= ms);

  1825. 	sei();

  1826. #endif

  1827. }

  1828. 

  1829. 

  1830. uint32_t _micros(void)

  1831. {

  1832. 	register uint32_t out asm("r22");

  1833. 	asm volatile(

  1834. 		"in	__tmp_reg__, __SREG__"		"\n\t"

  1835. 		"cli"					"\n\t"

  1836. 		"in	%A0, %2"			"\n\t"

  1837. 		"in	__zero_reg__, %3"		"\n\t"

  1838. 		"lds	%B0, timer0_micros_count"	"\n\t"

  1839. 		"lds	%C0, timer0_micros_count+1"	"\n\t"

  1840. 		"lds	%D0, timer0_micros_count+2"	"\n\t"

  1841. 		"out	__SREG__, __tmp_reg__"		"\n\t"

  1842. 		"sbrs	__zero_reg__, %4"		"\n\t"

  1843. 		"rjmp	L_%=_skip"			"\n\t"

  1844. 		"cpi	%A0, 255"			"\n\t"

  1845. 		"breq	L_%=_skip"			"\n\t"

  1846. 		"subi	%B0, 256 - %1"			"\n\t"

  1847. 		"sbci	%C0, 255"			"\n\t"

  1848. 		"sbci	%D0, 255"			"\n\t"

  1849. 	"L_%=_skip:"

  1850. 		"clr	__zero_reg__"			"\n\t"

  1851. 		"clr	__tmp_reg__"			"\n\t"

  1852. #if F_CPU == 16000000L || F_CPU == 8000000L || F_CPU == 4000000L

  1853. 		"lsl	%A0"				"\n\t"

  1854. 		"rol	__tmp_reg__"			"\n\t"

  1855. 		"lsl	%A0"				"\n\t"

  1856. 		"rol	__tmp_reg__"			"\n\t"

  1857. #if F_CPU == 8000000L || F_CPU == 4000000L

  1858. 		"lsl	%A0"				"\n\t"

  1859. 		"rol	__tmp_reg__"			"\n\t"

  1860. #endif

  1861. #if F_CPU == 4000000L

  1862. 		"lsl	%A0"				"\n\t"

  1863. 		"rol	__tmp_reg__"			"\n\t"

  1864. #endif

  1865. 		"or	%B0, __tmp_reg__"		"\n\t"

  1866. #endif

  1867. #if F_CPU == 1000000L || F_CPU == 2000000L

  1868. 		"lsr	%A0"				"\n\t"

  1869. 		"ror	__tmp_reg__"			"\n\t"

  1870. 		"lsr	%A0"				"\n\t"

  1871. 		"ror	__tmp_reg__"			"\n\t"

  1872. #if F_CPU == 2000000L

  1873. 		"lsr	%A0"				"\n\t"

  1874. 		"ror	__tmp_reg__"			"\n\t"

  1875. #endif

  1876. 		"or	%B0, %A0"			"\n\t"

  1877. 		"mov	%A0, __tmp_reg__"		"\n\t"

  1878. #endif

  1879. 		: "=d" (out)

  1880. 		: "M" (TIMER0_MICROS_INC),

  1881. 		  "I" (_SFR_IO_ADDR(TCNT0)),

  1882. 		  "I" (_SFR_IO_ADDR(TIFR0)),

  1883. 		  "I" (TOV0)

  1884. 		: "r0"

  1885. 	);

  1886. 	return out;

  1887. }

  1888. 

  1889.