Teensy 4.1 core updated for C++20
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  1. /* Teensyduino Core Library
  2. * http://www.pjrc.com/teensy/
  3. * Copyright (c) 2019 PJRC.COM, LLC.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining
  6. * a copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sublicense, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * 1. The above copyright notice and this permission notice shall be
  14. * included in all copies or substantial portions of the Software.
  15. *
  16. * 2. If the Software is incorporated into a build system that allows
  17. * selection among a list of target devices, then similar target
  18. * devices manufactured by PJRC.COM must be included in the list of
  19. * target devices and selectable in the same manner.
  20. *
  21. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  24. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  25. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  26. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  27. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  28. * SOFTWARE.
  29. */
  30. #include "HardwareSerial.h"
  31. #include "core_pins.h"
  32. #include "Arduino.h"
  33. //#include "debug/printf.h"
  34. /*typedef struct {
  35. const uint32_t VERID;
  36. const uint32_t PARAM;
  37. volatile uint32_t GLOBAL;
  38. volatile uint32_t PINCFG;
  39. volatile uint32_t BAUD;
  40. volatile uint32_t STAT;
  41. volatile uint32_t CTRL;
  42. volatile uint32_t DATA;
  43. volatile uint32_t MATCH;
  44. volatile uint32_t MODIR;
  45. volatile uint32_t FIFO;
  46. volatile uint32_t WATER;
  47. } IMXRT_LPUART_t; */
  48. //. From Onewire utility files
  49. #define PIN_TO_BASEREG(pin) (portOutputRegister(pin))
  50. #define PIN_TO_BITMASK(pin) (digitalPinToBitMask(pin))
  51. #define IO_REG_TYPE uint32_t
  52. #define IO_REG_BASE_ATTR
  53. #define IO_REG_MASK_ATTR
  54. #define DIRECT_READ(base, mask) ((*((base)+2) & (mask)) ? 1 : 0)
  55. #define DIRECT_MODE_INPUT(base, mask) (*((base)+1) &= ~(mask))
  56. #define DIRECT_MODE_OUTPUT(base, mask) (*((base)+1) |= (mask))
  57. #define DIRECT_WRITE_LOW(base, mask) (*((base)+34) = (mask))
  58. #define DIRECT_WRITE_HIGH(base, mask) (*((base)+33) = (mask))
  59. #define UART_CLOCK 24000000
  60. SerialEventCheckingFunctionPointer HardwareSerial::serial_event_handler_checks[8] = {nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr};
  61. uint8_t HardwareSerial::serial_event_handlers_active = 0;
  62. #define CTRL_ENABLE (LPUART_CTRL_TE | LPUART_CTRL_RE | LPUART_CTRL_RIE | LPUART_CTRL_ILIE)
  63. #define CTRL_TX_ACTIVE (CTRL_ENABLE | LPUART_CTRL_TIE)
  64. #define CTRL_TX_COMPLETING (CTRL_ENABLE | LPUART_CTRL_TCIE)
  65. #define CTRL_TX_INACTIVE CTRL_ENABLE
  66. // Copied from T3.x - probably should move to other location.
  67. int nvic_execution_priority(void)
  68. {
  69. uint32_t priority=256;
  70. uint32_t primask, faultmask, basepri, ipsr;
  71. // full algorithm in ARM DDI0403D, page B1-639
  72. // this isn't quite complete, but hopefully good enough
  73. __asm__ volatile("mrs %0, faultmask\n" : "=r" (faultmask)::);
  74. if (faultmask) return -1;
  75. __asm__ volatile("mrs %0, primask\n" : "=r" (primask)::);
  76. if (primask) return 0;
  77. __asm__ volatile("mrs %0, ipsr\n" : "=r" (ipsr)::);
  78. if (ipsr) {
  79. if (ipsr < 16) priority = 0; // could be non-zero
  80. else priority = NVIC_GET_PRIORITY(ipsr - 16);
  81. }
  82. __asm__ volatile("mrs %0, basepri\n" : "=r" (basepri)::);
  83. if (basepri > 0 && basepri < priority) priority = basepri;
  84. return priority;
  85. }
  86. void HardwareSerial::begin(uint32_t baud, uint16_t format)
  87. {
  88. //printf("HardwareSerial begin\n");
  89. float base = (float)UART_CLOCK / (float)baud;
  90. float besterr = 1e20;
  91. int bestdiv = 1;
  92. int bestosr = 4;
  93. for (int osr=4; osr <= 32; osr++) {
  94. float div = base / (float)osr;
  95. int divint = (int)(div + 0.5f);
  96. if (divint < 1) divint = 1;
  97. else if (divint > 8191) divint = 8191;
  98. float err = ((float)divint - div) / div;
  99. if (err < 0.0f) err = -err;
  100. if (err <= besterr) {
  101. besterr = err;
  102. bestdiv = divint;
  103. bestosr = osr;
  104. }
  105. }
  106. //printf(" baud %d: osr=%d, div=%d\n", baud, bestosr, bestdiv);
  107. rx_buffer_head_ = 0;
  108. rx_buffer_tail_ = 0;
  109. tx_buffer_head_ = 0;
  110. tx_buffer_tail_ = 0;
  111. rts_low_watermark_ = rx_buffer_total_size_ - hardware->rts_low_watermark;
  112. rts_high_watermark_ = rx_buffer_total_size_ - hardware->rts_high_watermark;
  113. transmitting_ = 0;
  114. hardware->ccm_register |= hardware->ccm_value;
  115. uint32_t fastio = IOMUXC_PAD_SRE | IOMUXC_PAD_DSE(3) | IOMUXC_PAD_SPEED(3);
  116. *(portControlRegister(hardware->rx_pin)) = fastio;
  117. *(portControlRegister(hardware->tx_pin)) = fastio;
  118. *(portConfigRegister(hardware->rx_pin)) = hardware->rx_mux_val;
  119. *(portConfigRegister(hardware->tx_pin)) = hardware->tx_mux_val;
  120. //hardware->rx_mux_register = hardware->rx_mux_val;
  121. //hardware->tx_mux_register = hardware->tx_mux_val;
  122. hardware->rx_select_input_register = hardware->rx_select_val;
  123. port->BAUD = LPUART_BAUD_OSR(bestosr - 1) | LPUART_BAUD_SBR(bestdiv);
  124. port->PINCFG = 0;
  125. // Enable the transmitter, receiver and enable receiver interrupt
  126. attachInterruptVector(hardware->irq, hardware->irq_handler);
  127. NVIC_SET_PRIORITY(hardware->irq, hardware->irq_priority); // maybe should put into hardware...
  128. NVIC_ENABLE_IRQ(hardware->irq);
  129. uint16_t tx_fifo_size = (((port->FIFO >> 4) & 0x7) << 2);
  130. uint8_t tx_water = (tx_fifo_size < 16) ? tx_fifo_size >> 1 : 7;
  131. uint16_t rx_fifo_size = (((port->FIFO >> 0) & 0x7) << 2);
  132. uint8_t rx_water = (rx_fifo_size < 16) ? rx_fifo_size >> 1 : 7;
  133. /*
  134. Serial.printf("SerialX::begin stat:%x ctrl:%x fifo:%x water:%x\n", port->STAT, port->CTRL, port->FIFO, port->WATER );
  135. Serial.printf(" FIFO sizes: tx:%d rx:%d\n",tx_fifo_size, rx_fifo_size);
  136. Serial.printf(" Watermark tx:%d, rx: %d\n", tx_water, rx_water);
  137. */
  138. port->WATER = LPUART_WATER_RXWATER(rx_water) | LPUART_WATER_TXWATER(tx_water);
  139. port->FIFO |= LPUART_FIFO_TXFE | LPUART_FIFO_RXFE;
  140. // lets configure up our CTRL register value
  141. uint32_t ctrl = CTRL_TX_INACTIVE;
  142. // Now process the bits in the Format value passed in
  143. // Bits 0-2 - Parity plus 9 bit.
  144. ctrl |= (format & (LPUART_CTRL_PT | LPUART_CTRL_PE) ); // configure parity - turn off PT, PE, M and configure PT, PE
  145. if (format & 0x04) ctrl |= LPUART_CTRL_M; // 9 bits (might include parity)
  146. if ((format & 0x0F) == 0x04) ctrl |= LPUART_CTRL_R9T8; // 8N2 is 9 bit with 9th bit always 1
  147. // Bit 5 TXINVERT
  148. if (format & 0x20) ctrl |= LPUART_CTRL_TXINV; // tx invert
  149. // write out computed CTRL
  150. port->CTRL = ctrl;
  151. // Bit 3 10 bit - Will assume that begin already cleared it.
  152. // process some other bits which change other registers.
  153. if (format & 0x08) port->BAUD |= LPUART_BAUD_M10;
  154. // Bit 4 RXINVERT
  155. uint32_t c = port->STAT & ~LPUART_STAT_RXINV;
  156. if (format & 0x10) c |= LPUART_STAT_RXINV; // rx invert
  157. port->STAT = c;
  158. // bit 8 can turn on 2 stop bit mote
  159. if ( format & 0x100) port->BAUD |= LPUART_BAUD_SBNS;
  160. //Serial.printf(" stat:%x ctrl:%x fifo:%x water:%x\n", port->STAT, port->CTRL, port->FIFO, port->WATER );
  161. enableSerialEvents(); // Enable the processing of serialEvent for this object
  162. };
  163. inline void HardwareSerial::rts_assert()
  164. {
  165. DIRECT_WRITE_LOW(rts_pin_baseReg_, rts_pin_bitmask_);
  166. }
  167. inline void HardwareSerial::rts_deassert()
  168. {
  169. DIRECT_WRITE_HIGH(rts_pin_baseReg_, rts_pin_bitmask_);
  170. }
  171. void HardwareSerial::end(void)
  172. {
  173. if (!(hardware->ccm_register & hardware->ccm_value)) return;
  174. while (transmitting_) yield(); // wait for buffered data to send
  175. port->CTRL = 0; // disable the TX and RX ...
  176. // Not sure if this is best, but I think most IO pins default to Mode 5? which appears to be digital IO?
  177. *(portConfigRegister(hardware->rx_pin)) = 5;
  178. *(portConfigRegister(hardware->tx_pin)) = 5;
  179. // Might need to clear out other areas as well?
  180. rx_buffer_head_ = 0;
  181. rx_buffer_tail_ = 0;
  182. if (rts_pin_baseReg_) rts_deassert();
  183. //
  184. disableSerialEvents(); // disable the processing of serialEvent for this object
  185. }
  186. void HardwareSerial::transmitterEnable(uint8_t pin)
  187. {
  188. while (transmitting_) ;
  189. pinMode(pin, OUTPUT);
  190. transmit_pin_baseReg_ = PIN_TO_BASEREG(pin);
  191. transmit_pin_bitmask_ = PIN_TO_BITMASK(pin);
  192. DIRECT_WRITE_LOW(transmit_pin_baseReg_, transmit_pin_bitmask_);
  193. }
  194. void HardwareSerial::setRX(uint8_t pin)
  195. {
  196. // Currently none of these have multiple
  197. // possible RX pins
  198. }
  199. void HardwareSerial::setTX(uint8_t pin, bool opendrain)
  200. {
  201. // While all of our TX pins only have one defined pin, we can choose to
  202. // turn on or off opendrain mode.
  203. if (pin == hardware->tx_pin) {
  204. if (opendrain)
  205. *(portControlRegister(hardware->tx_pin)) = IOMUXC_PAD_ODE | IOMUXC_PAD_DSE(3) | IOMUXC_PAD_SPEED(3);
  206. else
  207. *(portControlRegister(hardware->tx_pin)) = IOMUXC_PAD_SRE | IOMUXC_PAD_DSE(3) | IOMUXC_PAD_SPEED(3);
  208. }
  209. }
  210. bool HardwareSerial::attachRts(uint8_t pin)
  211. {
  212. if (!(hardware->ccm_register & hardware->ccm_value)) return 0;
  213. if (pin < CORE_NUM_DIGITAL) {
  214. rts_pin_baseReg_ = PIN_TO_BASEREG(pin);
  215. rts_pin_bitmask_ = PIN_TO_BITMASK(pin);
  216. pinMode(pin, OUTPUT);
  217. rts_assert();
  218. } else {
  219. rts_pin_baseReg_ = NULL;
  220. return 0;
  221. }
  222. return 1;
  223. }
  224. bool HardwareSerial::attachCts(uint8_t pin)
  225. {
  226. if (!(hardware->ccm_register & hardware->ccm_value)) return false;
  227. if ((pin != 0xff) && (pin == hardware->cts_pin)) {
  228. // Setup the IO pin as weak PULL down.
  229. *(portControlRegister(pin)) = IOMUXC_PAD_DSE(7) | IOMUXC_PAD_PKE | IOMUXC_PAD_PUE | IOMUXC_PAD_PUS(0) | IOMUXC_PAD_HYS;
  230. *(portConfigRegister(hardware->cts_pin)) = hardware->cts_mux_val;
  231. port->MODIR |= LPUART_MODIR_TXCTSE;
  232. return true;
  233. } else {
  234. port->MODIR &= ~LPUART_MODIR_TXCTSE;
  235. return false;
  236. }
  237. }
  238. void HardwareSerial::clear(void)
  239. {
  240. // BUGBUG:: deal with FIFO
  241. rx_buffer_head_ = rx_buffer_tail_;
  242. if (rts_pin_baseReg_) rts_assert();
  243. }
  244. int HardwareSerial::availableForWrite(void)
  245. {
  246. uint32_t head, tail;
  247. head = tx_buffer_head_;
  248. tail = tx_buffer_tail_;
  249. if (head >= tail) return tx_buffer_total_size_ - 1 - head + tail;
  250. return tail - head - 1;
  251. }
  252. int HardwareSerial::available(void)
  253. {
  254. uint32_t head, tail;
  255. head = rx_buffer_head_;
  256. tail = rx_buffer_tail_;
  257. if (head >= tail) return head - tail;
  258. return rx_buffer_total_size_ + head - tail;
  259. }
  260. void HardwareSerial::addStorageForRead(void *buffer, size_t length)
  261. {
  262. rx_buffer_storage_ = (BUFTYPE*)buffer;
  263. if (buffer) {
  264. rx_buffer_total_size_ = rx_buffer_total_size_ + length;
  265. } else {
  266. rx_buffer_total_size_ = rx_buffer_total_size_;
  267. }
  268. rts_low_watermark_ = rx_buffer_total_size_ - hardware->rts_low_watermark;
  269. rts_high_watermark_ = rx_buffer_total_size_ - hardware->rts_high_watermark;
  270. }
  271. void HardwareSerial::addStorageForWrite(void *buffer, size_t length)
  272. {
  273. tx_buffer_storage_ = (BUFTYPE*)buffer;
  274. if (buffer) {
  275. tx_buffer_total_size_ = tx_buffer_total_size_ + length;
  276. } else {
  277. tx_buffer_total_size_ = tx_buffer_total_size_;
  278. }
  279. }
  280. int HardwareSerial::peek(void)
  281. {
  282. uint32_t head, tail;
  283. head = rx_buffer_head_;
  284. tail = rx_buffer_tail_;
  285. if (head == tail) return -1;
  286. if (++tail >= rx_buffer_total_size_) tail = 0;
  287. if (tail < rx_buffer_size_) {
  288. return rx_buffer_[tail];
  289. } else {
  290. return rx_buffer_storage_[tail-rx_buffer_size_];
  291. }
  292. }
  293. int HardwareSerial::read(void)
  294. {
  295. uint32_t head, tail;
  296. int c;
  297. head = rx_buffer_head_;
  298. tail = rx_buffer_tail_;
  299. if (head == tail) return -1;
  300. if (++tail >= rx_buffer_total_size_) tail = 0;
  301. if (tail < rx_buffer_size_) {
  302. c = rx_buffer_[tail];
  303. } else {
  304. c = rx_buffer_storage_[tail-rx_buffer_size_];
  305. }
  306. rx_buffer_tail_ = tail;
  307. if (rts_pin_baseReg_) {
  308. uint32_t avail;
  309. if (head >= tail) avail = head - tail;
  310. else avail = rx_buffer_total_size_ + head - tail;
  311. if (avail <= rts_low_watermark_) rts_assert();
  312. }
  313. return c;
  314. }
  315. void HardwareSerial::flush(void)
  316. {
  317. while (transmitting_) yield(); // wait
  318. }
  319. size_t HardwareSerial::write(uint8_t c)
  320. {
  321. // use the 9 bit version (maybe 10 bit) do do the work.
  322. return write9bit(c);
  323. }
  324. size_t HardwareSerial::write9bit(uint32_t c)
  325. {
  326. uint32_t head, n;
  327. //digitalWrite(3, HIGH);
  328. //digitalWrite(5, HIGH);
  329. if (transmit_pin_baseReg_) DIRECT_WRITE_HIGH(transmit_pin_baseReg_, transmit_pin_bitmask_);
  330. head = tx_buffer_head_;
  331. if (++head >= tx_buffer_total_size_) head = 0;
  332. while (tx_buffer_tail_ == head) {
  333. int priority = nvic_execution_priority();
  334. if (priority <= hardware->irq_priority) {
  335. if ((port->STAT & LPUART_STAT_TDRE)) {
  336. uint32_t tail = tx_buffer_tail_;
  337. if (++tail >= tx_buffer_total_size_) tail = 0;
  338. if (tail < tx_buffer_size_) {
  339. n = tx_buffer_[tail];
  340. } else {
  341. n = tx_buffer_storage_[tail-tx_buffer_size_];
  342. }
  343. port->DATA = n;
  344. tx_buffer_tail_ = tail;
  345. }
  346. } else if (priority >= 256)
  347. {
  348. yield(); // wait
  349. }
  350. }
  351. //digitalWrite(5, LOW);
  352. //Serial.printf("WR %x %d %d %d %x %x\n", c, head, tx_buffer_size_, tx_buffer_total_size_, (uint32_t)tx_buffer_, (uint32_t)tx_buffer_storage_);
  353. if (head < tx_buffer_size_) {
  354. tx_buffer_[head] = c;
  355. } else {
  356. tx_buffer_storage_[head - tx_buffer_size_] = c;
  357. }
  358. __disable_irq();
  359. transmitting_ = 1;
  360. tx_buffer_head_ = head;
  361. port->CTRL |= LPUART_CTRL_TIE; // (may need to handle this issue)BITBAND_SET_BIT(LPUART0_CTRL, TIE_BIT);
  362. __enable_irq();
  363. //digitalWrite(3, LOW);
  364. return 1;
  365. }
  366. void HardwareSerial::IRQHandler()
  367. {
  368. //digitalWrite(4, HIGH);
  369. uint32_t head, tail, n;
  370. uint32_t ctrl;
  371. // See if we have stuff to read in.
  372. // Todo - Check idle.
  373. if (port->STAT & (LPUART_STAT_RDRF | LPUART_STAT_IDLE)) {
  374. // See how many bytes or pending.
  375. //digitalWrite(5, HIGH);
  376. uint8_t avail = (port->WATER >> 24) & 0x7;
  377. if (avail) {
  378. uint32_t newhead;
  379. head = rx_buffer_head_;
  380. tail = rx_buffer_tail_;
  381. do {
  382. n = port->DATA & 0x3ff; // Use only up to 10 bits of data
  383. newhead = head + 1;
  384. if (newhead >= rx_buffer_total_size_) newhead = 0;
  385. if (newhead != rx_buffer_tail_) {
  386. head = newhead;
  387. if (newhead < rx_buffer_size_) {
  388. rx_buffer_[head] = n;
  389. } else {
  390. rx_buffer_storage_[head-rx_buffer_size_] = n;
  391. }
  392. }
  393. } while (--avail > 0) ;
  394. rx_buffer_head_ = head;
  395. if (rts_pin_baseReg_) {
  396. uint32_t avail;
  397. if (head >= tail) avail = head - tail;
  398. else avail = rx_buffer_total_size_ + head - tail;
  399. if (avail >= rts_high_watermark_) rts_deassert();
  400. }
  401. }
  402. // If it was an idle status clear the idle
  403. if (port->STAT & LPUART_STAT_IDLE) {
  404. port->STAT |= LPUART_STAT_IDLE; // writing a 1 to idle should clear it.
  405. }
  406. //digitalWrite(5, LOW);
  407. }
  408. // See if we are transmitting and room in buffer.
  409. ctrl = port->CTRL;
  410. if ((ctrl & LPUART_CTRL_TIE) && (port->STAT & LPUART_STAT_TDRE))
  411. {
  412. //digitalWrite(3, HIGH);
  413. head = tx_buffer_head_;
  414. tail = tx_buffer_tail_;
  415. do {
  416. if (head == tail) break;
  417. if (++tail >= tx_buffer_total_size_) tail = 0;
  418. if (tail < tx_buffer_size_) {
  419. n = tx_buffer_[tail];
  420. } else {
  421. n = tx_buffer_storage_[tail-tx_buffer_size_];
  422. }
  423. port->DATA = n;
  424. } while (((port->WATER >> 8) & 0x7) < 4); // need to computer properly
  425. tx_buffer_tail_ = tail;
  426. if (head == tail) {
  427. port->CTRL &= ~LPUART_CTRL_TIE;
  428. port->CTRL |= LPUART_CTRL_TCIE; // Actually wondering if we can just leave this one on...
  429. }
  430. //digitalWrite(3, LOW);
  431. }
  432. if ((ctrl & LPUART_CTRL_TCIE) && (port->STAT & LPUART_STAT_TC))
  433. {
  434. transmitting_ = 0;
  435. if (transmit_pin_baseReg_) DIRECT_WRITE_LOW(transmit_pin_baseReg_, transmit_pin_bitmask_);
  436. port->CTRL &= ~LPUART_CTRL_TCIE;
  437. }
  438. //digitalWrite(4, LOW);
  439. }
  440. void HardwareSerial::processSerialEvents()
  441. {
  442. if (!serial_event_handlers_active) return; // bail quick if no one processing SerialEvents.
  443. uint8_t handlers_still_to_process = serial_event_handlers_active;
  444. for (uint8_t i = 0; i < 8; i++) {
  445. if (serial_event_handler_checks[i]) {
  446. (*serial_event_handler_checks[i])();
  447. if (--handlers_still_to_process == 0) return;
  448. }
  449. }
  450. }
  451. void HardwareSerial::enableSerialEvents()
  452. {
  453. if (!serial_event_handler_checks[hardware->serial_index]) {
  454. serial_event_handler_checks[hardware->serial_index] = hardware->serial_event_handler_check; // clear it out
  455. serial_event_handlers_active++;
  456. }
  457. }
  458. void HardwareSerial::disableSerialEvents()
  459. {
  460. if (serial_event_handler_checks[hardware->serial_index]) {
  461. serial_event_handler_checks[hardware->serial_index] = nullptr; // clear it out
  462. serial_event_handlers_active--;
  463. }
  464. }