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Teensy 4.1 core updated for C++20
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teensy-core-4.1/teensy4/startup.c

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  1. #include "imxrt.h"

  2. #include "wiring.h"

  3. #include "usb_dev.h"

  4. #include "avr/pgmspace.h"

  5. #include "smalloc.h"

  6. #include <string.h>

  7. 

  8. #include "debug/printf.h"

  9. 

  10. // from the linker

  11. extern unsigned long _stextload;

  12. extern unsigned long _stext;

  13. extern unsigned long _etext;

  14. extern unsigned long _sdataload;

  15. extern unsigned long _sdata;

  16. extern unsigned long _edata;

  17. extern unsigned long _sbss;

  18. extern unsigned long _ebss;

  19. extern unsigned long _flexram_bank_config;

  20. extern unsigned long _estack;

  21. extern unsigned long _extram_start;

  22. extern unsigned long _extram_end;

  23. 

  24. __attribute__ ((used, aligned(1024)))

  25. void (* _VectorsRam[NVIC_NUM_INTERRUPTS+16])(void);

  26. 

  27. static void memory_copy(uint32_t *dest, const uint32_t *src, uint32_t *dest_end);

  28. static void memory_clear(uint32_t *dest, uint32_t *dest_end);

  29. static void configure_systick(void);

  30. static void reset_PFD();

  31. extern void systick_isr(void);

  32. extern void pendablesrvreq_isr(void);

  33. void configure_cache(void);

  34. void configure_external_ram(void);

  35. void unused_interrupt_vector(void);

  36. void usb_pll_start();

  37. extern void analog_init(void); // analog.c

  38. extern void pwm_init(void); // pwm.c

  39. extern void tempmon_init(void);  //tempmon.c

  40. uint32_t set_arm_clock(uint32_t frequency); // clockspeed.c

  41. extern void __libc_init_array(void); // C++ standard library

  42. 

  43. uint8_t external_psram_size = 0;

  44. #ifdef ARDUINO_TEENSY41

  45. struct smalloc_pool extmem_smalloc_pool;

  46. #endif

  47. 

  48. extern int main (void);

  49. void startup_default_early_hook(void) {}

  50. void startup_early_hook(void)		__attribute__ ((weak, alias("startup_default_early_hook")));

  51. void startup_default_late_hook(void) {}

  52. void startup_late_hook(void)		__attribute__ ((weak, alias("startup_default_late_hook")));

  53. __attribute__((section(".startup"), optimize("no-tree-loop-distribute-patterns")))

  54. void ResetHandler(void)

  55. {

  56. 	unsigned int i;

  57. 

  58. #if defined(__IMXRT1062__)

  59. 	IOMUXC_GPR_GPR17 = (uint32_t)&_flexram_bank_config;

  60. 	IOMUXC_GPR_GPR16 = 0x00200007;

  61. 	IOMUXC_GPR_GPR14 = 0x00AA0000;

  62. 	__asm__ volatile("mov sp, %0" : : "r" ((uint32_t)&_estack) : );

  63. #endif

  64. 	PMU_MISC0_SET = 1<<3; //Use bandgap-based bias currents for best performance (Page 1175)

  65. 	// pin 13 - if startup crashes, use this to turn on the LED early for troubleshooting

  66. 	//IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 5;

  67. 	//IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = IOMUXC_PAD_DSE(7);

  68. 	//IOMUXC_GPR_GPR27 = 0xFFFFFFFF;

  69. 	//GPIO7_GDIR |= (1<<3);

  70. 	//GPIO7_DR_SET = (1<<3); // digitalWrite(13, HIGH);

  71. 

  72. 	// Initialize memory

  73. 	memory_copy(&_stext, &_stextload, &_etext);

  74. 	memory_copy(&_sdata, &_sdataload, &_edata);

  75. 	memory_clear(&_sbss, &_ebss);

  76. 

  77. 	// enable FPU

  78. 	SCB_CPACR = 0x00F00000;

  79. 

  80. 	// set up blank interrupt & exception vector table

  81. 	for (i=0; i < NVIC_NUM_INTERRUPTS + 16; i++) _VectorsRam[i] = &unused_interrupt_vector;

  82. 	for (i=0; i < NVIC_NUM_INTERRUPTS; i++) NVIC_SET_PRIORITY(i, 128);

  83. 	SCB_VTOR = (uint32_t)_VectorsRam;

  84. 

  85. 	reset_PFD();

  86. 	

  87. 	// Configure clocks

  88. 	// TODO: make sure all affected peripherals are turned off!

  89. 	// PIT & GPT timers to run from 24 MHz clock (independent of CPU speed)

  90. 	CCM_CSCMR1 = (CCM_CSCMR1 & ~CCM_CSCMR1_PERCLK_PODF(0x3F)) | CCM_CSCMR1_PERCLK_CLK_SEL;

  91. 	// UARTs run from 24 MHz clock (works if PLL3 off or bypassed)

  92. 	CCM_CSCDR1 = (CCM_CSCDR1 & ~CCM_CSCDR1_UART_CLK_PODF(0x3F)) | CCM_CSCDR1_UART_CLK_SEL;

  93. 

  94. #if defined(__IMXRT1062__)

  95. 	// Use fast GPIO6, GPIO7, GPIO8, GPIO9

  96. 	IOMUXC_GPR_GPR26 = 0xFFFFFFFF;

  97. 	IOMUXC_GPR_GPR27 = 0xFFFFFFFF;

  98. 	IOMUXC_GPR_GPR28 = 0xFFFFFFFF;

  99. 	IOMUXC_GPR_GPR29 = 0xFFFFFFFF;

  100. #endif

  101. 

  102. 	// must enable PRINT_DEBUG_STUFF in debug/print.h

  103. 	printf_debug_init();

  104. 	printf("\n***********IMXRT Startup**********\n");

  105. 	printf("test %d %d %d\n", 1, -1234567, 3);

  106. 

  107. 	configure_cache();

  108. 	configure_systick();

  109. 	usb_pll_start();	

  110. 	reset_PFD(); //TODO: is this really needed?

  111. #ifdef F_CPU

  112. 	set_arm_clock(F_CPU);

  113. #endif

  114. 

  115. 	// Undo PIT timer usage by ROM startup

  116. 	CCM_CCGR1 |= CCM_CCGR1_PIT(CCM_CCGR_ON);

  117. 	PIT_MCR = 0;

  118. 	PIT_TCTRL0 = 0;

  119. 	PIT_TCTRL1 = 0;

  120. 	PIT_TCTRL2 = 0;

  121. 	PIT_TCTRL3 = 0;

  122. 

  123. 	// initialize RTC

  124. 	if (!(SNVS_LPCR & SNVS_LPCR_SRTC_ENV)) {

  125. 		// if SRTC isn't running, start it with default Jan 1, 2019

  126. 		SNVS_LPSRTCLR = 1546300800u << 15;

  127. 		SNVS_LPSRTCMR = 1546300800u >> 17;

  128. 		SNVS_LPCR |= SNVS_LPCR_SRTC_ENV;

  129. 	}

  130. 	SNVS_HPCR |= SNVS_HPCR_RTC_EN | SNVS_HPCR_HP_TS;

  131. 

  132. #ifdef ARDUINO_TEENSY41

  133. 	configure_external_ram();

  134. #endif

  135. 	startup_early_hook();

  136. 	while (millis() < 20) ; // wait at least 20ms before starting USB

  137. 	usb_init();

  138. 	analog_init();

  139. 	pwm_init();

  140. 	tempmon_init();

  141. 

  142. 	startup_late_hook();

  143. 	while (millis() < 300) ; // wait at least 300ms before calling user code

  144. 	//printf("before C++ constructors\n");

  145. 	__libc_init_array();

  146. 	//printf("after C++ constructors\n");

  147. 	//printf("before setup\n");

  148. 	main();

  149. 	

  150. 	while (1) asm("WFI");

  151. }

  152. 

  153. 

  154. 

  155. 

  156. // ARM SysTick is used for most Ardiuno timing functions, delay(), millis(),

  157. // micros().  SysTick can run from either the ARM core clock, or from an

  158. // "external" clock.  NXP documents it as "24 MHz XTALOSC can be the external

  159. // clock source of SYSTICK" (RT1052 ref manual, rev 1, page 411).  However,

  160. // NXP actually hid an undocumented divide-by-240 circuit in the hardware, so

  161. // the external clock is really 100 kHz.  We use this clock rather than the

  162. // ARM clock, to allow SysTick to maintain correct timing even when we change

  163. // the ARM clock to run at different speeds.

  164. #define SYSTICK_EXT_FREQ 100000

  165. 

  166. extern volatile uint32_t systick_cycle_count;

  167. static void configure_systick(void)

  168. {

  169. 	_VectorsRam[14] = pendablesrvreq_isr;

  170. 	_VectorsRam[15] = systick_isr;

  171. 	SYST_RVR = (SYSTICK_EXT_FREQ / 1000) - 1;

  172. 	SYST_CVR = 0;

  173. 	SYST_CSR = SYST_CSR_TICKINT | SYST_CSR_ENABLE;

  174. 	SCB_SHPR3 = 0x20200000;  // Systick, pendablesrvreq_isr = priority 32;

  175. 	ARM_DEMCR |= ARM_DEMCR_TRCENA;

  176. 	ARM_DWT_CTRL |= ARM_DWT_CTRL_CYCCNTENA; // turn on cycle counter

  177. 	systick_cycle_count = ARM_DWT_CYCCNT; // compiled 0, corrected w/1st systick

  178. }

  179. 

  180. 

  181. // concise defines for SCB_MPU_RASR and SCB_MPU_RBAR, ARM DDI0403E, pg 696

  182. #define NOEXEC		SCB_MPU_RASR_XN

  183. #define READONLY	SCB_MPU_RASR_AP(7)

  184. #define READWRITE	SCB_MPU_RASR_AP(3)

  185. #define NOACCESS	SCB_MPU_RASR_AP(0)

  186. #define MEM_CACHE_WT	SCB_MPU_RASR_TEX(0) | SCB_MPU_RASR_C

  187. #define MEM_CACHE_WB	SCB_MPU_RASR_TEX(0) | SCB_MPU_RASR_C | SCB_MPU_RASR_B

  188. #define MEM_CACHE_WBWA	SCB_MPU_RASR_TEX(1) | SCB_MPU_RASR_C | SCB_MPU_RASR_B

  189. #define MEM_NOCACHE	SCB_MPU_RASR_TEX(1)

  190. #define DEV_NOCACHE	SCB_MPU_RASR_TEX(2)

  191. #define SIZE_32B	(SCB_MPU_RASR_SIZE(4) | SCB_MPU_RASR_ENABLE)

  192. #define SIZE_64B	(SCB_MPU_RASR_SIZE(5) | SCB_MPU_RASR_ENABLE)

  193. #define SIZE_128B	(SCB_MPU_RASR_SIZE(6) | SCB_MPU_RASR_ENABLE)

  194. #define SIZE_256B	(SCB_MPU_RASR_SIZE(7) | SCB_MPU_RASR_ENABLE)

  195. #define SIZE_512B	(SCB_MPU_RASR_SIZE(8) | SCB_MPU_RASR_ENABLE)

  196. #define SIZE_1K		(SCB_MPU_RASR_SIZE(9) | SCB_MPU_RASR_ENABLE)

  197. #define SIZE_2K		(SCB_MPU_RASR_SIZE(10) | SCB_MPU_RASR_ENABLE)

  198. #define SIZE_4K		(SCB_MPU_RASR_SIZE(11) | SCB_MPU_RASR_ENABLE)

  199. #define SIZE_8K		(SCB_MPU_RASR_SIZE(12) | SCB_MPU_RASR_ENABLE)

  200. #define SIZE_16K	(SCB_MPU_RASR_SIZE(13) | SCB_MPU_RASR_ENABLE)

  201. #define SIZE_32K	(SCB_MPU_RASR_SIZE(14) | SCB_MPU_RASR_ENABLE)

  202. #define SIZE_64K	(SCB_MPU_RASR_SIZE(15) | SCB_MPU_RASR_ENABLE)

  203. #define SIZE_128K	(SCB_MPU_RASR_SIZE(16) | SCB_MPU_RASR_ENABLE)

  204. #define SIZE_256K	(SCB_MPU_RASR_SIZE(17) | SCB_MPU_RASR_ENABLE)

  205. #define SIZE_512K	(SCB_MPU_RASR_SIZE(18) | SCB_MPU_RASR_ENABLE)

  206. #define SIZE_1M		(SCB_MPU_RASR_SIZE(19) | SCB_MPU_RASR_ENABLE)

  207. #define SIZE_2M		(SCB_MPU_RASR_SIZE(20) | SCB_MPU_RASR_ENABLE)

  208. #define SIZE_4M		(SCB_MPU_RASR_SIZE(21) | SCB_MPU_RASR_ENABLE)

  209. #define SIZE_8M		(SCB_MPU_RASR_SIZE(22) | SCB_MPU_RASR_ENABLE)

  210. #define SIZE_16M	(SCB_MPU_RASR_SIZE(23) | SCB_MPU_RASR_ENABLE)

  211. #define SIZE_32M	(SCB_MPU_RASR_SIZE(24) | SCB_MPU_RASR_ENABLE)

  212. #define SIZE_64M	(SCB_MPU_RASR_SIZE(25) | SCB_MPU_RASR_ENABLE)

  213. #define SIZE_128M	(SCB_MPU_RASR_SIZE(26) | SCB_MPU_RASR_ENABLE)

  214. #define SIZE_256M	(SCB_MPU_RASR_SIZE(27) | SCB_MPU_RASR_ENABLE)

  215. #define SIZE_512M	(SCB_MPU_RASR_SIZE(28) | SCB_MPU_RASR_ENABLE)

  216. #define SIZE_1G		(SCB_MPU_RASR_SIZE(29) | SCB_MPU_RASR_ENABLE)

  217. #define SIZE_2G		(SCB_MPU_RASR_SIZE(30) | SCB_MPU_RASR_ENABLE)

  218. #define SIZE_4G		(SCB_MPU_RASR_SIZE(31) | SCB_MPU_RASR_ENABLE)

  219. #define REGION(n)	(SCB_MPU_RBAR_REGION(n) | SCB_MPU_RBAR_VALID)

  220. 

  221. FLASHMEM void configure_cache(void)

  222. {

  223. 	//printf("MPU_TYPE = %08lX\n", SCB_MPU_TYPE);

  224. 	//printf("CCR = %08lX\n", SCB_CCR);

  225. 

  226. 	// TODO: check if caches already active - skip?

  227. 

  228. 	SCB_MPU_CTRL = 0; // turn off MPU

  229. 

  230. 	uint32_t i = 0;

  231. 	SCB_MPU_RBAR = 0x00000000 | REGION(i++); //https://developer.arm.com/docs/146793866/10/why-does-the-cortex-m7-initiate-axim-read-accesses-to-memory-addresses-that-do-not-fall-under-a-defined-mpu-region

  232. 	SCB_MPU_RASR = SCB_MPU_RASR_TEX(0) | NOACCESS | NOEXEC | SIZE_4G;

  233. 	

  234. 	SCB_MPU_RBAR = 0x00000000 | REGION(i++); // ITCM

  235. 	SCB_MPU_RASR = MEM_NOCACHE | READWRITE | SIZE_512K;

  236. 

  237. 	// TODO: trap regions should be created last, because the hardware gives

  238. 	//  priority to the higher number ones.

  239. 	SCB_MPU_RBAR = 0x00000000 | REGION(i++); // trap NULL pointer deref

  240. 	SCB_MPU_RASR =  DEV_NOCACHE | NOACCESS | SIZE_32B;

  241. 

  242. 	SCB_MPU_RBAR = 0x00200000 | REGION(i++); // Boot ROM

  243. 	SCB_MPU_RASR = MEM_CACHE_WT | READONLY | SIZE_128K;

  244. 

  245. 	SCB_MPU_RBAR = 0x20000000 | REGION(i++); // DTCM

  246. 	SCB_MPU_RASR = MEM_NOCACHE | READWRITE | NOEXEC | SIZE_512K;

  247. 	

  248. 	SCB_MPU_RBAR = ((uint32_t)&_ebss) | REGION(i++); // trap stack overflow

  249. 	SCB_MPU_RASR = SCB_MPU_RASR_TEX(0) | NOACCESS | NOEXEC | SIZE_32B;

  250. 

  251. 	SCB_MPU_RBAR = 0x20200000 | REGION(i++); // RAM (AXI bus)

  252. 	SCB_MPU_RASR = MEM_CACHE_WBWA | READWRITE | NOEXEC | SIZE_1M;

  253. 

  254. 	SCB_MPU_RBAR = 0x40000000 | REGION(i++); // Peripherals

  255. 	SCB_MPU_RASR = DEV_NOCACHE | READWRITE | NOEXEC | SIZE_64M;

  256. 

  257. 	SCB_MPU_RBAR = 0x60000000 | REGION(i++); // QSPI Flash

  258. 	SCB_MPU_RASR = MEM_CACHE_WBWA | READONLY | SIZE_16M;

  259. 

  260. 	SCB_MPU_RBAR = 0x70000000 | REGION(i++); // FlexSPI2

  261. 	SCB_MPU_RASR = MEM_CACHE_WBWA | READONLY | NOEXEC | SIZE_256M;

  262. 

  263. 	SCB_MPU_RBAR = 0x70000000 | REGION(i++); // FlexSPI2

  264. 	SCB_MPU_RASR = MEM_CACHE_WBWA | READWRITE | NOEXEC | SIZE_16M;

  265. 

  266. 	// TODO: protect access to power supply config

  267. 

  268. 	SCB_MPU_CTRL = SCB_MPU_CTRL_ENABLE;

  269. 

  270. 	// cache enable, ARM DDI0403E, pg 628

  271. 	asm("dsb");

  272. 	asm("isb");

  273. 	SCB_CACHE_ICIALLU = 0;

  274. 

  275. 	asm("dsb");

  276. 	asm("isb");

  277. 	SCB_CCR |= (SCB_CCR_IC | SCB_CCR_DC);

  278. }

  279. 

  280. #ifdef ARDUINO_TEENSY41

  281. 

  282. #define LUT0(opcode, pads, operand) (FLEXSPI_LUT_INSTRUCTION((opcode), (pads), (operand)))

  283. #define LUT1(opcode, pads, operand) (FLEXSPI_LUT_INSTRUCTION((opcode), (pads), (operand)) << 16)

  284. #define CMD_SDR         FLEXSPI_LUT_OPCODE_CMD_SDR

  285. #define ADDR_SDR        FLEXSPI_LUT_OPCODE_RADDR_SDR

  286. #define READ_SDR        FLEXSPI_LUT_OPCODE_READ_SDR

  287. #define WRITE_SDR       FLEXSPI_LUT_OPCODE_WRITE_SDR

  288. #define DUMMY_SDR       FLEXSPI_LUT_OPCODE_DUMMY_SDR

  289. #define PINS1           FLEXSPI_LUT_NUM_PADS_1

  290. #define PINS4           FLEXSPI_LUT_NUM_PADS_4

  291. 

  292. FLASHMEM static void flexspi2_command(uint32_t index, uint32_t addr)

  293. {

  294. 	FLEXSPI2_IPCR0 = addr;

  295. 	FLEXSPI2_IPCR1 = FLEXSPI_IPCR1_ISEQID(index);

  296. 	FLEXSPI2_IPCMD = FLEXSPI_IPCMD_TRG;

  297. 	while (!(FLEXSPI2_INTR & FLEXSPI_INTR_IPCMDDONE)); // wait

  298. 	FLEXSPI2_INTR = FLEXSPI_INTR_IPCMDDONE;

  299. }

  300. 

  301. FLASHMEM static uint32_t flexspi2_psram_id(uint32_t addr)

  302. {

  303. 	FLEXSPI2_IPCR0 = addr;

  304. 	FLEXSPI2_IPCR1 = FLEXSPI_IPCR1_ISEQID(3) | FLEXSPI_IPCR1_IDATSZ(4);

  305. 	FLEXSPI2_IPCMD = FLEXSPI_IPCMD_TRG;

  306. 	while (!(FLEXSPI2_INTR & FLEXSPI_INTR_IPCMDDONE)); // wait

  307. 	uint32_t id = FLEXSPI2_RFDR0;

  308. 	FLEXSPI2_INTR = FLEXSPI_INTR_IPCMDDONE | FLEXSPI_INTR_IPRXWA;

  309. 	return id & 0xFFFF;

  310. }

  311. 

  312. FLASHMEM void configure_external_ram()

  313. {

  314. 	// initialize pins

  315. 	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 = 0x1B0F9; // 100K pullup, strong drive, max speed, hyst

  316. 	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 = 0x110F9; // keeper, strong drive, max speed, hyst

  317. 	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 = 0x1B0F9; // 100K pullup, strong drive, max speed, hyst

  318. 	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 = 0x100F9; // strong drive, max speed, hyst

  319. 	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 = 0x170F9; // 47K pullup, strong drive, max speed, hyst

  320. 	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 = 0x170F9; // 47K pullup, strong drive, max speed, hyst

  321. 	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 = 0x170F9; // 47K pullup, strong drive, max speed, hyst

  322. 	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 = 0x170F9; // 47K pullup, strong drive, max speed, hyst

  323. 

  324. 	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 8 | 0x10; // ALT1 = FLEXSPI2_A_SS1_B (Flash)

  325. 	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 8 | 0x10; // ALT1 = FLEXSPI2_A_DQS

  326. 	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 8 | 0x10; // ALT1 = FLEXSPI2_A_SS0_B (RAM)

  327. 	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 8 | 0x10; // ALT1 = FLEXSPI2_A_SCLK

  328. 	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 8 | 0x10; // ALT1 = FLEXSPI2_A_DATA0

  329. 	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 8 | 0x10; // ALT1 = FLEXSPI2_A_DATA1

  330. 	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 = 8 | 0x10; // ALT1 = FLEXSPI2_A_DATA2

  331. 	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 = 8 | 0x10; // ALT1 = FLEXSPI2_A_DATA3

  332. 

  333. 	IOMUXC_FLEXSPI2_IPP_IND_DQS_FA_SELECT_INPUT = 1; // GPIO_EMC_23 for Mode: ALT8, pg 986

  334. 	IOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT0_SELECT_INPUT = 1; // GPIO_EMC_26 for Mode: ALT8

  335. 	IOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT1_SELECT_INPUT = 1; // GPIO_EMC_27 for Mode: ALT8

  336. 	IOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT2_SELECT_INPUT = 1; // GPIO_EMC_28 for Mode: ALT8

  337. 	IOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT3_SELECT_INPUT = 1; // GPIO_EMC_29 for Mode: ALT8

  338. 	IOMUXC_FLEXSPI2_IPP_IND_SCK_FA_SELECT_INPUT = 1; // GPIO_EMC_25 for Mode: ALT8

  339. 

  340. 	// turn on clock  (TODO: increase clock speed later, slow & cautious for first release)

  341. 	CCM_CBCMR = (CCM_CBCMR & ~(CCM_CBCMR_FLEXSPI2_PODF_MASK | CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK))

  342. 		| CCM_CBCMR_FLEXSPI2_PODF(5) | CCM_CBCMR_FLEXSPI2_CLK_SEL(3); // 88 MHz

  343. 	CCM_CCGR7 |= CCM_CCGR7_FLEXSPI2(CCM_CCGR_ON);

  344. 

  345. 	FLEXSPI2_MCR0 |= FLEXSPI_MCR0_MDIS;

  346. 	FLEXSPI2_MCR0 = (FLEXSPI2_MCR0 & ~(FLEXSPI_MCR0_AHBGRANTWAIT_MASK

  347. 		 | FLEXSPI_MCR0_IPGRANTWAIT_MASK | FLEXSPI_MCR0_SCKFREERUNEN

  348. 		 | FLEXSPI_MCR0_COMBINATIONEN | FLEXSPI_MCR0_DOZEEN

  349. 		 | FLEXSPI_MCR0_HSEN | FLEXSPI_MCR0_ATDFEN | FLEXSPI_MCR0_ARDFEN

  350. 		 | FLEXSPI_MCR0_RXCLKSRC_MASK | FLEXSPI_MCR0_SWRESET))

  351. 		| FLEXSPI_MCR0_AHBGRANTWAIT(0xFF) | FLEXSPI_MCR0_IPGRANTWAIT(0xFF)

  352. 		| FLEXSPI_MCR0_RXCLKSRC(1) | FLEXSPI_MCR0_MDIS;

  353. 	FLEXSPI2_MCR1 = FLEXSPI_MCR1_SEQWAIT(0xFFFF) | FLEXSPI_MCR1_AHBBUSWAIT(0xFFFF);

  354. 	FLEXSPI2_MCR2 = (FLEXSPI_MCR2 & ~(FLEXSPI_MCR2_RESUMEWAIT_MASK

  355. 		 | FLEXSPI_MCR2_SCKBDIFFOPT | FLEXSPI_MCR2_SAMEDEVICEEN

  356. 		 | FLEXSPI_MCR2_CLRLEARNPHASE | FLEXSPI_MCR2_CLRAHBBUFOPT))

  357. 		| FLEXSPI_MCR2_RESUMEWAIT(0x20) /*| FLEXSPI_MCR2_SAMEDEVICEEN*/;

  358. 

  359. 	FLEXSPI2_AHBCR = FLEXSPI2_AHBCR & ~(FLEXSPI_AHBCR_READADDROPT | FLEXSPI_AHBCR_PREFETCHEN

  360. 		| FLEXSPI_AHBCR_BUFFERABLEEN | FLEXSPI_AHBCR_CACHABLEEN);

  361. 	uint32_t mask = (FLEXSPI_AHBRXBUFCR0_PREFETCHEN | FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK

  362. 		| FLEXSPI_AHBRXBUFCR0_MSTRID_MASK | FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK);

  363. 	FLEXSPI2_AHBRXBUF0CR0 = (FLEXSPI2_AHBRXBUF0CR0 & ~mask)

  364. 		| FLEXSPI_AHBRXBUFCR0_PREFETCHEN | FLEXSPI_AHBRXBUFCR0_BUFSZ(64);

  365. 	FLEXSPI2_AHBRXBUF1CR0 = (FLEXSPI2_AHBRXBUF0CR0 & ~mask)

  366. 		| FLEXSPI_AHBRXBUFCR0_PREFETCHEN | FLEXSPI_AHBRXBUFCR0_BUFSZ(64);

  367. 	FLEXSPI2_AHBRXBUF2CR0 = mask;

  368. 	FLEXSPI2_AHBRXBUF3CR0 = mask;

  369. 

  370. 	// RX watermark = one 64 bit line

  371. 	FLEXSPI2_IPRXFCR = (FLEXSPI_IPRXFCR & 0xFFFFFFC0) | FLEXSPI_IPRXFCR_CLRIPRXF;

  372. 	// TX watermark = one 64 bit line

  373. 	FLEXSPI2_IPTXFCR = (FLEXSPI_IPTXFCR & 0xFFFFFFC0) | FLEXSPI_IPTXFCR_CLRIPTXF;

  374. 

  375. 	FLEXSPI2_INTEN = 0;

  376. 	FLEXSPI2_FLSHA1CR0 = 0x2000; // 8 MByte

  377. 	FLEXSPI2_FLSHA1CR1 = FLEXSPI_FLSHCR1_CSINTERVAL(2)

  378. 		| FLEXSPI_FLSHCR1_TCSH(3) | FLEXSPI_FLSHCR1_TCSS(3);

  379. 	FLEXSPI2_FLSHA1CR2 = FLEXSPI_FLSHCR2_AWRSEQID(6) | FLEXSPI_FLSHCR2_AWRSEQNUM(0)

  380. 		| FLEXSPI_FLSHCR2_ARDSEQID(5) | FLEXSPI_FLSHCR2_ARDSEQNUM(0);

  381. 

  382. 	FLEXSPI2_FLSHA2CR0 = 0x2000; // 8 MByte

  383. 	FLEXSPI2_FLSHA2CR1 = FLEXSPI_FLSHCR1_CSINTERVAL(2)

  384. 		| FLEXSPI_FLSHCR1_TCSH(3) | FLEXSPI_FLSHCR1_TCSS(3);

  385. 	FLEXSPI2_FLSHA2CR2 = FLEXSPI_FLSHCR2_AWRSEQID(6) | FLEXSPI_FLSHCR2_AWRSEQNUM(0)

  386. 		| FLEXSPI_FLSHCR2_ARDSEQID(5) | FLEXSPI_FLSHCR2_ARDSEQNUM(0);

  387. 

  388. 	FLEXSPI2_MCR0 &= ~FLEXSPI_MCR0_MDIS;

  389. 

  390. 	FLEXSPI2_LUTKEY = FLEXSPI_LUTKEY_VALUE;

  391. 	FLEXSPI2_LUTCR = FLEXSPI_LUTCR_UNLOCK;

  392. 	volatile uint32_t *luttable = &FLEXSPI2_LUT0;

  393. 	for (int i=0; i < 64; i++) luttable[i] = 0;

  394. 	FLEXSPI2_MCR0 |= FLEXSPI_MCR0_SWRESET;

  395. 	while (FLEXSPI2_MCR0 & FLEXSPI_MCR0_SWRESET) ; // wait

  396. 

  397. 	FLEXSPI2_LUTKEY = FLEXSPI_LUTKEY_VALUE;

  398. 	FLEXSPI2_LUTCR = FLEXSPI_LUTCR_UNLOCK;

  399. 

  400. 	// cmd index 0 = exit QPI mode

  401. 	FLEXSPI2_LUT0 = LUT0(CMD_SDR, PINS4, 0xF5);

  402. 	// cmd index 1 = reset enable

  403. 	FLEXSPI2_LUT4 = LUT0(CMD_SDR, PINS1, 0x66);

  404. 	// cmd index 2 = reset

  405. 	FLEXSPI2_LUT8 = LUT0(CMD_SDR, PINS1, 0x99);

  406. 	// cmd index 3 = read ID bytes

  407. 	FLEXSPI2_LUT12 = LUT0(CMD_SDR, PINS1, 0x9F) | LUT1(DUMMY_SDR, PINS1, 24);

  408. 	FLEXSPI2_LUT13 = LUT0(READ_SDR, PINS1, 1);

  409. 	// cmd index 4 = enter QPI mode

  410. 	FLEXSPI2_LUT16 = LUT0(CMD_SDR, PINS1, 0x35);

  411. 	// cmd index 5 = read QPI

  412. 	FLEXSPI2_LUT20 = LUT0(CMD_SDR, PINS4, 0xEB) | LUT1(ADDR_SDR, PINS4, 24);

  413. 	FLEXSPI2_LUT21 = LUT0(DUMMY_SDR, PINS4, 6) | LUT1(READ_SDR, PINS4, 1);

  414. 	// cmd index 6 = write QPI

  415. 	FLEXSPI2_LUT24 = LUT0(CMD_SDR, PINS4, 0x38) | LUT1(ADDR_SDR, PINS4, 24);

  416. 	FLEXSPI2_LUT25 = LUT0(WRITE_SDR, PINS4, 1);

  417. 

  418. 	// look for the first PSRAM chip

  419. 	flexspi2_command(0, 0); // exit quad mode

  420. 	flexspi2_command(1, 0); // reset enable

  421. 	flexspi2_command(2, 0); // reset (is this really necessary?)

  422. 	if (flexspi2_psram_id(0) == 0x5D0D) {

  423. 		// first PSRAM chip is present, look for a second PSRAM chip

  424. 		flexspi2_command(4, 0);

  425. 		flexspi2_command(0, 0x800000); // exit quad mode

  426. 		flexspi2_command(1, 0x800000); // reset enable

  427. 		flexspi2_command(2, 0x800000); // reset (is this really necessary?)

  428. 		if (flexspi2_psram_id(0x800000) == 0x5D0D) {

  429. 			flexspi2_command(4, 0x800000);

  430. 			// Two PSRAM chips are present, 16 MByte

  431. 			external_psram_size = 16;

  432. 		} else {

  433. 			// One PSRAM chip is present, 8 MByte

  434. 			external_psram_size = 8;

  435. 		}

  436. 		// TODO: zero uninitialized EXTMEM variables

  437. 		// TODO: copy from flash to initialize EXTMEM variables

  438. 		sm_set_pool(&extmem_smalloc_pool, &_extram_end,

  439. 			external_psram_size * 0x100000 -

  440. 			((uint32_t)&_extram_end - (uint32_t)&_extram_start),

  441. 			1, NULL);

  442. 	} else {

  443. 		// No PSRAM

  444. 		memset(&extmem_smalloc_pool, 0, sizeof(extmem_smalloc_pool));

  445. 	}

  446. }

  447. 

  448. #endif // ARDUINO_TEENSY41

  449. 

  450. 

  451. FLASHMEM void usb_pll_start()

  452. {

  453. 	while (1) {

  454. 		uint32_t n = CCM_ANALOG_PLL_USB1; // pg 759

  455. 		printf("CCM_ANALOG_PLL_USB1=%08lX\n", n);

  456. 		if (n & CCM_ANALOG_PLL_USB1_DIV_SELECT) {

  457. 			printf("  ERROR, 528 MHz mode!\n"); // never supposed to use this mode!

  458. 			CCM_ANALOG_PLL_USB1_CLR = 0xC000;			// bypass 24 MHz

  459. 			CCM_ANALOG_PLL_USB1_SET = CCM_ANALOG_PLL_USB1_BYPASS;	// bypass

  460. 			CCM_ANALOG_PLL_USB1_CLR = CCM_ANALOG_PLL_USB1_POWER |	// power down

  461. 				CCM_ANALOG_PLL_USB1_DIV_SELECT |		// use 480 MHz

  462. 				CCM_ANALOG_PLL_USB1_ENABLE |			// disable

  463. 				CCM_ANALOG_PLL_USB1_EN_USB_CLKS;		// disable usb

  464. 			continue;

  465. 		}

  466. 		if (!(n & CCM_ANALOG_PLL_USB1_ENABLE)) {

  467. 			printf("  enable PLL\n");

  468. 			// TODO: should this be done so early, or later??

  469. 			CCM_ANALOG_PLL_USB1_SET = CCM_ANALOG_PLL_USB1_ENABLE;

  470. 			continue;

  471. 		}

  472. 		if (!(n & CCM_ANALOG_PLL_USB1_POWER)) {

  473. 			printf("  power up PLL\n");

  474. 			CCM_ANALOG_PLL_USB1_SET = CCM_ANALOG_PLL_USB1_POWER;

  475. 			continue;

  476. 		}

  477. 		if (!(n & CCM_ANALOG_PLL_USB1_LOCK)) {

  478. 			printf("  wait for lock\n");

  479. 			continue;

  480. 		}

  481. 		if (n & CCM_ANALOG_PLL_USB1_BYPASS) {

  482. 			printf("  turn off bypass\n");

  483. 			CCM_ANALOG_PLL_USB1_CLR = CCM_ANALOG_PLL_USB1_BYPASS;

  484. 			continue;

  485. 		}

  486. 		if (!(n & CCM_ANALOG_PLL_USB1_EN_USB_CLKS)) {

  487. 			printf("  enable USB clocks\n");

  488. 			CCM_ANALOG_PLL_USB1_SET = CCM_ANALOG_PLL_USB1_EN_USB_CLKS;

  489. 			continue;

  490. 		}

  491. 		return; // everything is as it should be  :-)

  492. 	}

  493. }

  494. 

  495. FLASHMEM void reset_PFD()

  496. {	

  497. 	//Reset PLL2 PFDs, set default frequencies:

  498. 	CCM_ANALOG_PFD_528_SET = (1 << 31) | (1 << 23) | (1 << 15) | (1 << 7);

  499. 	CCM_ANALOG_PFD_528 = 0x2018101B; // PFD0:352, PFD1:594, PFD2:396, PFD3:297 MHz 	

  500. 	//PLL3:

  501. 	CCM_ANALOG_PFD_480_SET = (1 << 31) | (1 << 23) | (1 << 15) | (1 << 7);	

  502. 	CCM_ANALOG_PFD_480 = 0x13110D0C; // PFD0:720, PFD1:664, PFD2:508, PFD3:454 MHz

  503. }

  504. 

  505. // Stack frame

  506. //  xPSR

  507. //  ReturnAddress

  508. //  LR (R14) - typically FFFFFFF9 for IRQ or Exception

  509. //  R12

  510. //  R3

  511. //  R2

  512. //  R1

  513. //  R0

  514. // Code from :: https://community.nxp.com/thread/389002

  515. __attribute__((naked))

  516. void unused_interrupt_vector(void)

  517. {

  518.   __asm( ".syntax unified\n"

  519.          "MOVS R0, #4 \n"

  520.          "MOV R1, LR \n"

  521.          "TST R0, R1 \n"

  522.          "BEQ _MSP \n"

  523.          "MRS R0, PSP \n"

  524.          "B HardFault_HandlerC \n"

  525.          "_MSP: \n"

  526.          "MRS R0, MSP \n"

  527.          "B HardFault_HandlerC \n"

  528.          ".syntax divided\n") ;

  529. }

  530. 

  531. __attribute__((weak))

  532. void HardFault_HandlerC(unsigned int *hardfault_args)

  533. {

  534.   volatile unsigned int nn ;

  535. #ifdef PRINT_DEBUG_STUFF

  536.   volatile unsigned int stacked_r0 ;

  537.   volatile unsigned int stacked_r1 ;

  538.   volatile unsigned int stacked_r2 ;

  539.   volatile unsigned int stacked_r3 ;

  540.   volatile unsigned int stacked_r12 ;

  541.   volatile unsigned int stacked_lr ;

  542.   volatile unsigned int stacked_pc ;

  543.   volatile unsigned int stacked_psr ;

  544.   volatile unsigned int _CFSR ;

  545.   volatile unsigned int _HFSR ;

  546.   volatile unsigned int _DFSR ;

  547.   volatile unsigned int _AFSR ;

  548.   volatile unsigned int _BFAR ;

  549.   volatile unsigned int _MMAR ;

  550.   volatile unsigned int addr ;

  551. 

  552.   stacked_r0 = ((unsigned int)hardfault_args[0]) ;

  553.   stacked_r1 = ((unsigned int)hardfault_args[1]) ;

  554.   stacked_r2 = ((unsigned int)hardfault_args[2]) ;

  555.   stacked_r3 = ((unsigned int)hardfault_args[3]) ;

  556.   stacked_r12 = ((unsigned int)hardfault_args[4]) ;

  557.   stacked_lr = ((unsigned int)hardfault_args[5]) ;

  558.   stacked_pc = ((unsigned int)hardfault_args[6]) ;

  559.   stacked_psr = ((unsigned int)hardfault_args[7]) ;

  560.   // Configurable Fault Status Register

  561.   // Consists of MMSR, BFSR and UFSR

  562.   //(n & ( 1 << k )) >> k

  563.   _CFSR = (*((volatile unsigned int *)(0xE000ED28))) ;  

  564.   // Hard Fault Status Register

  565.   _HFSR = (*((volatile unsigned int *)(0xE000ED2C))) ;

  566.   // Debug Fault Status Register

  567.   _DFSR = (*((volatile unsigned int *)(0xE000ED30))) ;

  568.   // Auxiliary Fault Status Register

  569.   _AFSR = (*((volatile unsigned int *)(0xE000ED3C))) ;

  570.   // Read the Fault Address Registers. These may not contain valid values.

  571.   // Check BFARVALID/MMARVALID to see if they are valid values

  572.   // MemManage Fault Address Register

  573.   _MMAR = (*((volatile unsigned int *)(0xE000ED34))) ;

  574.   // Bus Fault Address Register

  575.   _BFAR = (*((volatile unsigned int *)(0xE000ED38))) ;

  576.   //__asm("BKPT #0\n") ; // Break into the debugger // NO Debugger here.

  577. 

  578.   asm volatile("mrs %0, ipsr\n" : "=r" (addr)::);

  579.   printf("\nFault irq %d\n", addr & 0x1FF);

  580.   printf(" stacked_r0 ::  %x\n", stacked_r0);

  581.   printf(" stacked_r1 ::  %x\n", stacked_r1);

  582.   printf(" stacked_r2 ::  %x\n", stacked_r2);

  583.   printf(" stacked_r3 ::  %x\n", stacked_r3);

  584.   printf(" stacked_r12 ::  %x\n", stacked_r12);

  585.   printf(" stacked_lr ::  %x\n", stacked_lr);

  586.   printf(" stacked_pc ::  %x\n", stacked_pc);

  587.   printf(" stacked_psr ::  %x\n", stacked_psr);

  588.   printf(" _CFSR ::  %x\n", _CFSR);

  589.  

  590.   if(_CFSR > 0){

  591. 	  //Memory Management Faults

  592. 	  if((_CFSR & 1) == 1){

  593. 		printf("      (IACCVIOL) Instruction Access Violation\n");

  594. 	  } else  if(((_CFSR & (0x02))>>1) == 1){

  595. 		printf("      (DACCVIOL) Data Access Violation\n");

  596. 	  } else if(((_CFSR & (0x08))>>3) == 1){

  597. 		printf("      (MUNSTKERR) MemMange Fault on Unstacking\n");

  598. 	  } else if(((_CFSR & (0x10))>>4) == 1){

  599. 		printf("      (MSTKERR) MemMange Fault on stacking\n");

  600. 	  } else if(((_CFSR & (0x20))>>5) == 1){

  601. 		printf("      (MLSPERR) MemMange Fault on FP Lazy State\n");

  602. 	  }

  603. 	  if(((_CFSR & (0x80))>>7) == 1){

  604. 		printf("      (MMARVALID) MemMange Fault Address Valid\n");

  605. 	  }

  606. 	  //Bus Fault Status Register

  607. 	  if(((_CFSR & 0x100)>>8) == 1){

  608. 		printf("      (IBUSERR) Instruction Bus Error\n");

  609. 	  } else  if(((_CFSR & (0x200))>>9) == 1){

  610. 		printf("      (PRECISERR) Data bus error(address in BFAR)\n");

  611. 	  } else if(((_CFSR & (0x400))>>10) == 1){

  612. 		printf("      (IMPRECISERR) Data bus error but address not related to instruction\n");

  613. 	  } else if(((_CFSR & (0x800))>>11) == 1){

  614. 		printf("      (UNSTKERR) Bus Fault on unstacking for a return from exception \n");

  615. 	  } else if(((_CFSR & (0x1000))>>12) == 1){

  616. 		printf("      (STKERR) Bus Fault on stacking for exception entry\n");

  617. 	  } else if(((_CFSR & (0x2000))>>13) == 1){

  618. 		printf("      (LSPERR) Bus Fault on FP lazy state preservation\n");

  619. 	  }

  620. 	  if(((_CFSR & (0x8000))>>15) == 1){

  621. 		printf("      (BFARVALID) Bus Fault Address Valid\n");

  622. 	  }  

  623. 	  //Usuage Fault Status Register

  624. 	  if(((_CFSR & 0x10000)>>16) == 1){

  625. 		printf("      (UNDEFINSTR) Undefined instruction\n");

  626. 	  } else  if(((_CFSR & (0x20000))>>17) == 1){

  627. 		printf("      (INVSTATE) Instruction makes illegal use of EPSR)\n");

  628. 	  } else if(((_CFSR & (0x40000))>>18) == 1){

  629. 		printf("      (INVPC) Usage fault: invalid EXC_RETURN\n");

  630. 	  } else if(((_CFSR & (0x80000))>>19) == 1){

  631. 		printf("      (NOCP) No Coprocessor \n");

  632. 	  } else if(((_CFSR & (0x1000000))>>24) == 1){

  633. 		printf("      (UNALIGNED) Unaligned access UsageFault\n");

  634. 	  } else if(((_CFSR & (0x2000000))>>25) == 1){

  635. 		printf("      (DIVBYZERO) Divide by zero\n");

  636. 	  }

  637.   }

  638.   printf(" _HFSR ::  %x\n", _HFSR);

  639.   if(_HFSR > 0){

  640. 	  //Memory Management Faults

  641. 	  if(((_HFSR & (0x02))>>1) == 1){

  642. 		printf("      (VECTTBL) Bus Fault on Vec Table Read\n");

  643. 	  } else if(((_HFSR & (0x40000000))>>30) == 1){

  644. 		printf("      (FORCED) Forced Hard Fault\n");

  645. 	  } else if(((_HFSR & (0x80000000))>>31) == 31){

  646. 		printf("      (DEBUGEVT) Reserved for Debug\n");

  647. 	  } 

  648.   }

  649.   printf(" _DFSR ::  %x\n", _DFSR);

  650.   printf(" _AFSR ::  %x\n", _AFSR);

  651.   printf(" _BFAR ::  %x\n", _BFAR);

  652.   printf(" _MMAR ::  %x\n", _MMAR);

  653. #endif

  654. 

  655.   IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 5; // pin 13

  656.   IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = IOMUXC_PAD_DSE(7);

  657.   GPIO2_GDIR |= (1 << 3);

  658.   GPIO2_DR_SET = (1 << 3);

  659.   GPIO2_DR_CLEAR = (1 << 3); //digitalWrite(13, LOW);

  660. 

  661.   if ( F_CPU_ACTUAL >= 600000000 )

  662.     set_arm_clock(300000000);

  663. 

  664.   while (1)

  665.   {

  666.     GPIO2_DR_SET = (1 << 3); //digitalWrite(13, HIGH);

  667.     // digitalWrite(13, HIGH);

  668.     for (nn = 0; nn < 2000000/2; nn++) ;

  669.     GPIO2_DR_CLEAR = (1 << 3); //digitalWrite(13, LOW);

  670.     // digitalWrite(13, LOW);

  671.     for (nn = 0; nn < 18000000/2; nn++) ;

  672.   }

  673. }

  674. 

  675. __attribute__((weak))

  676. void userDebugDump(){

  677. 	volatile unsigned int nn;

  678. 	printf("\nuserDebugDump() in startup.c ___ \n");

  679. 

  680.   while (1)

  681.   {

  682.     GPIO2_DR_SET = (1 << 3); //digitalWrite(13, HIGH);

  683.     // digitalWrite(13, HIGH);

  684.     for (nn = 0; nn < 2000000; nn++) ;

  685.     GPIO2_DR_CLEAR = (1 << 3); //digitalWrite(13, LOW);

  686. 	// digitalWrite(13, LOW);

  687.     for (nn = 0; nn < 18000000; nn++) ;

  688.     GPIO2_DR_SET = (1 << 3); //digitalWrite(13, HIGH);

  689.     // digitalWrite(13, HIGH);

  690.     for (nn = 0; nn < 20000000; nn++) ;

  691.     GPIO2_DR_CLEAR = (1 << 3); //digitalWrite(13, LOW);

  692. 	// digitalWrite(13, LOW);

  693.     for (nn = 0; nn < 10000000; nn++) ;

  694.   }

  695. }

  696. 

  697. __attribute__((weak))

  698. void PJRCunused_interrupt_vector(void)

  699. {

  700. 	// TODO: polling Serial to complete buffered transmits

  701. #ifdef PRINT_DEBUG_STUFF

  702. 	uint32_t addr;

  703. 	asm volatile("mrs %0, ipsr\n" : "=r" (addr)::);

  704. 	printf("\nirq %d\n", addr & 0x1FF);

  705. 	asm("ldr %0, [sp, #52]" : "=r" (addr) ::);

  706. 	printf(" %x\n", addr);

  707. 	asm("ldr %0, [sp, #48]" : "=r" (addr) ::);

  708. 	printf(" %x\n", addr);

  709. 	asm("ldr %0, [sp, #44]" : "=r" (addr) ::);

  710. 	printf(" %x\n", addr);

  711. 	asm("ldr %0, [sp, #40]" : "=r" (addr) ::);

  712. 	printf(" %x\n", addr);

  713. 	asm("ldr %0, [sp, #36]" : "=r" (addr) ::);

  714. 	printf(" %x\n", addr);

  715. 	asm("ldr %0, [sp, #33]" : "=r" (addr) ::);

  716. 	printf(" %x\n", addr);

  717. 	asm("ldr %0, [sp, #34]" : "=r" (addr) ::);

  718. 	printf(" %x\n", addr);

  719. 	asm("ldr %0, [sp, #28]" : "=r" (addr) ::);

  720. 	printf(" %x\n", addr);

  721. 	asm("ldr %0, [sp, #24]" : "=r" (addr) ::);

  722. 	printf(" %x\n", addr);

  723. 	asm("ldr %0, [sp, #20]" : "=r" (addr) ::);

  724. 	printf(" %x\n", addr);

  725. 	asm("ldr %0, [sp, #16]" : "=r" (addr) ::);

  726. 	printf(" %x\n", addr);

  727. 	asm("ldr %0, [sp, #12]" : "=r" (addr) ::);

  728. 	printf(" %x\n", addr);

  729. 	asm("ldr %0, [sp, #8]" : "=r" (addr) ::);

  730. 	printf(" %x\n", addr);

  731. 	asm("ldr %0, [sp, #4]" : "=r" (addr) ::);

  732. 	printf(" %x\n", addr);

  733. 	asm("ldr %0, [sp, #0]" : "=r" (addr) ::);

  734. 	printf(" %x\n", addr);

  735. #endif

  736. #if 1

  737. 	if ( F_CPU_ACTUAL >= 600000000 )

  738. 		set_arm_clock(100000000);

  739. 	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 5; // pin 13

  740. 	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = IOMUXC_PAD_DSE(7);

  741. 	GPIO2_GDIR |= (1<<3);

  742. 	GPIO2_DR_SET = (1<<3);

  743. 	while (1) {

  744. 		volatile uint32_t n;

  745. 		GPIO2_DR_SET = (1<<3); //digitalWrite(13, HIGH);

  746. 		for (n=0; n < 2000000/6; n++) ;

  747. 		GPIO2_DR_CLEAR = (1<<3); //digitalWrite(13, LOW);

  748. 		for (n=0; n < 1500000/6; n++) ;

  749. 	}

  750. #else

  751. 	if ( F_CPU_ACTUAL >= 600000000 )

  752. 		set_arm_clock(100000000);

  753. 	while (1) asm ("WFI");

  754. #endif

  755. }

  756. 

  757. __attribute__((section(".startup"), optimize("no-tree-loop-distribute-patterns")))

  758. static void memory_copy(uint32_t *dest, const uint32_t *src, uint32_t *dest_end)

  759. {

  760. 	if (dest == src) return;

  761. 	while (dest < dest_end) {

  762. 		*dest++ = *src++;

  763. 	}

  764. }

  765. 

  766. __attribute__((section(".startup"), optimize("no-tree-loop-distribute-patterns")))

  767. static void memory_clear(uint32_t *dest, uint32_t *dest_end)

  768. {

  769. 	while (dest < dest_end) {

  770. 		*dest++ = 0;

  771. 	}

  772. }

  773. 

  774. 

  775. 

  776. // syscall functions need to be in the same C file as the entry point "ResetVector"

  777. // otherwise the linker will discard them in some cases.

  778. 

  779. #include <errno.h>

  780. 

  781. // from the linker script

  782. extern unsigned long _heap_start;

  783. extern unsigned long _heap_end;

  784. 

  785. char *__brkval = (char *)&_heap_start;

  786. 

  787. void * _sbrk(int incr)

  788. {

  789.         char *prev = __brkval;

  790.         if (incr != 0) {

  791.                 if (prev + incr > (char *)&_heap_end) {

  792.                         errno = ENOMEM;

  793.                         return (void *)-1;

  794.                 }

  795.                 __brkval = prev + incr;

  796.         }

  797.         return prev;

  798. }

  799. 

  800. __attribute__((weak))

  801. int _read(int file, char *ptr, int len)

  802. {

  803. 	return 0;

  804. }

  805. 

  806. __attribute__((weak))

  807. int _close(int fd)

  808. {

  809. 	return -1;

  810. }

  811. 

  812. #include <sys/stat.h>

  813. 

  814. __attribute__((weak))

  815. int _fstat(int fd, struct stat *st)

  816. {

  817. 	st->st_mode = S_IFCHR;

  818. 	return 0;

  819. }

  820. 

  821. __attribute__((weak))

  822. int _isatty(int fd)

  823. {

  824. 	return 1;

  825. }

  826. 

  827. __attribute__((weak))

  828. int _lseek(int fd, long long offset, int whence)

  829. {

  830. 	return -1;

  831. }

  832. 

  833. __attribute__((weak))

  834. void _exit(int status)

  835. {

  836. 	while (1) asm ("WFI");

  837. }

  838. 

  839. __attribute__((weak))

  840. void __cxa_pure_virtual()

  841. {

  842. 	while (1) asm ("WFI");

  843. }

  844. 

  845. __attribute__((weak))

  846. int __cxa_guard_acquire (char *g)

  847. {

  848. 	return !(*g);

  849. }

  850. 

  851. __attribute__((weak))

  852. void __cxa_guard_release(char *g)

  853. {

  854. 	*g = 1;

  855. }

  856. 

  857. __attribute__((weak))

  858. void abort(void)

  859. {

  860. 	while (1) asm ("WFI");

  861. }