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Teensy 4.1 core updated for C++20
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teensy-core-4.1/teensy4/digital.c

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  1. 

  2. #include "core_pins.h"

  3. 

  4. /*

  5. struct digital_pin_bitband_and_config_table_struct {

  6.         volatile uint32_t *reg;

  7.         volatile uint32_t *mux;

  8.         volatile uint32_t *pad;

  9.         uint32_t mask;

  10. };

  11. extern const struct digital_pin_bitband_and_config_table_struct digital_pin_to_info_PGM[];

  12. #define digitalPinToPort(pin)    (pin)

  13. #define digitalPinToBitMask(pin) (digital_pin_to_info_PGM[(pin)].mask)

  14. #define portOutputRegister(pin)  ((digital_pin_to_info_PGM[(pin)].reg))

  15. #define portSetRegister(pin)     ((digital_pin_to_info_PGM[(pin)].reg + 0x21))

  16. #define portClearRegister(pin)   ((digital_pin_to_info_PGM[(pin)].reg + 0x22))

  17. #define portToggleRegister(pin)  ((digital_pin_to_info_PGM[(pin)].reg + 0x23))

  18. #define portInputRegister(pin)   ((digital_pin_to_info_PGM[(pin)].reg + 2))

  19. #define portModeRegister(pin)    ((digital_pin_to_info_PGM[(pin)].reg + 1))

  20. #define portConfigRegister(pin)  ((digital_pin_to_info_PGM[(pin)].max))

  21. #define digitalPinToPortReg(pin) (portOutputRegister(pin))

  22. */

  23. 

  24. const struct digital_pin_bitband_and_config_table_struct digital_pin_to_info_PGM[] = {

  25. 	{&CORE_PIN0_PORTREG, &CORE_PIN0_CONFIG, &CORE_PIN0_PADCONFIG, CORE_PIN0_BITMASK},

  26. 	{&CORE_PIN1_PORTREG, &CORE_PIN1_CONFIG, &CORE_PIN1_PADCONFIG, CORE_PIN1_BITMASK},

  27. 	{&CORE_PIN2_PORTREG, &CORE_PIN2_CONFIG, &CORE_PIN2_PADCONFIG, CORE_PIN2_BITMASK},

  28. 	{&CORE_PIN3_PORTREG, &CORE_PIN3_CONFIG, &CORE_PIN3_PADCONFIG, CORE_PIN3_BITMASK},

  29. 	{&CORE_PIN4_PORTREG, &CORE_PIN4_CONFIG, &CORE_PIN4_PADCONFIG, CORE_PIN4_BITMASK},

  30. 	{&CORE_PIN5_PORTREG, &CORE_PIN5_CONFIG, &CORE_PIN5_PADCONFIG, CORE_PIN5_BITMASK},

  31. 	{&CORE_PIN6_PORTREG, &CORE_PIN6_CONFIG, &CORE_PIN6_PADCONFIG, CORE_PIN6_BITMASK},

  32. 	{&CORE_PIN7_PORTREG, &CORE_PIN7_CONFIG, &CORE_PIN7_PADCONFIG, CORE_PIN7_BITMASK},

  33. 	{&CORE_PIN8_PORTREG, &CORE_PIN8_CONFIG, &CORE_PIN8_PADCONFIG, CORE_PIN8_BITMASK},

  34. 	{&CORE_PIN9_PORTREG, &CORE_PIN9_CONFIG, &CORE_PIN9_PADCONFIG, CORE_PIN9_BITMASK},

  35. 	{&CORE_PIN10_PORTREG, &CORE_PIN10_CONFIG, &CORE_PIN10_PADCONFIG, CORE_PIN10_BITMASK},

  36. 	{&CORE_PIN11_PORTREG, &CORE_PIN11_CONFIG, &CORE_PIN11_PADCONFIG, CORE_PIN11_BITMASK},

  37. 	{&CORE_PIN12_PORTREG, &CORE_PIN12_CONFIG, &CORE_PIN12_PADCONFIG, CORE_PIN12_BITMASK},

  38. 	{&CORE_PIN13_PORTREG, &CORE_PIN13_CONFIG, &CORE_PIN13_PADCONFIG, CORE_PIN13_BITMASK},

  39. 	{&CORE_PIN14_PORTREG, &CORE_PIN14_CONFIG, &CORE_PIN14_PADCONFIG, CORE_PIN14_BITMASK},

  40. 	{&CORE_PIN15_PORTREG, &CORE_PIN15_CONFIG, &CORE_PIN15_PADCONFIG, CORE_PIN15_BITMASK},

  41. 	{&CORE_PIN16_PORTREG, &CORE_PIN16_CONFIG, &CORE_PIN16_PADCONFIG, CORE_PIN16_BITMASK},

  42. 	{&CORE_PIN17_PORTREG, &CORE_PIN17_CONFIG, &CORE_PIN17_PADCONFIG, CORE_PIN17_BITMASK},

  43. 	{&CORE_PIN18_PORTREG, &CORE_PIN18_CONFIG, &CORE_PIN18_PADCONFIG, CORE_PIN18_BITMASK},

  44. 	{&CORE_PIN19_PORTREG, &CORE_PIN19_CONFIG, &CORE_PIN19_PADCONFIG, CORE_PIN19_BITMASK},

  45. 	{&CORE_PIN20_PORTREG, &CORE_PIN20_CONFIG, &CORE_PIN20_PADCONFIG, CORE_PIN20_BITMASK},

  46. 	{&CORE_PIN21_PORTREG, &CORE_PIN21_CONFIG, &CORE_PIN21_PADCONFIG, CORE_PIN21_BITMASK},

  47. 	{&CORE_PIN22_PORTREG, &CORE_PIN22_CONFIG, &CORE_PIN22_PADCONFIG, CORE_PIN22_BITMASK},

  48. 	{&CORE_PIN23_PORTREG, &CORE_PIN23_CONFIG, &CORE_PIN23_PADCONFIG, CORE_PIN23_BITMASK},

  49. 	{&CORE_PIN24_PORTREG, &CORE_PIN24_CONFIG, &CORE_PIN24_PADCONFIG, CORE_PIN24_BITMASK},

  50. 	{&CORE_PIN25_PORTREG, &CORE_PIN25_CONFIG, &CORE_PIN25_PADCONFIG, CORE_PIN25_BITMASK},

  51. 	{&CORE_PIN26_PORTREG, &CORE_PIN26_CONFIG, &CORE_PIN26_PADCONFIG, CORE_PIN26_BITMASK},

  52. 	{&CORE_PIN27_PORTREG, &CORE_PIN27_CONFIG, &CORE_PIN27_PADCONFIG, CORE_PIN27_BITMASK},

  53. 	{&CORE_PIN28_PORTREG, &CORE_PIN28_CONFIG, &CORE_PIN28_PADCONFIG, CORE_PIN28_BITMASK},

  54. 	{&CORE_PIN29_PORTREG, &CORE_PIN29_CONFIG, &CORE_PIN29_PADCONFIG, CORE_PIN29_BITMASK},

  55. 	{&CORE_PIN30_PORTREG, &CORE_PIN30_CONFIG, &CORE_PIN30_PADCONFIG, CORE_PIN30_BITMASK},

  56. 	{&CORE_PIN31_PORTREG, &CORE_PIN31_CONFIG, &CORE_PIN31_PADCONFIG, CORE_PIN31_BITMASK},

  57. 	{&CORE_PIN32_PORTREG, &CORE_PIN32_CONFIG, &CORE_PIN32_PADCONFIG, CORE_PIN32_BITMASK},

  58. 	{&CORE_PIN33_PORTREG, &CORE_PIN33_CONFIG, &CORE_PIN33_PADCONFIG, CORE_PIN33_BITMASK},

  59. 	{&CORE_PIN34_PORTREG, &CORE_PIN34_CONFIG, &CORE_PIN34_PADCONFIG, CORE_PIN34_BITMASK},

  60. 	{&CORE_PIN35_PORTREG, &CORE_PIN35_CONFIG, &CORE_PIN35_PADCONFIG, CORE_PIN35_BITMASK},

  61. 	{&CORE_PIN36_PORTREG, &CORE_PIN36_CONFIG, &CORE_PIN36_PADCONFIG, CORE_PIN36_BITMASK},

  62. 	{&CORE_PIN37_PORTREG, &CORE_PIN37_CONFIG, &CORE_PIN37_PADCONFIG, CORE_PIN37_BITMASK},

  63. 	{&CORE_PIN38_PORTREG, &CORE_PIN38_CONFIG, &CORE_PIN38_PADCONFIG, CORE_PIN38_BITMASK},

  64. 	{&CORE_PIN39_PORTREG, &CORE_PIN39_CONFIG, &CORE_PIN39_PADCONFIG, CORE_PIN39_BITMASK},

  65. #if defined(ARDUINO_TEENSY41)

  66. 	{&CORE_PIN40_PORTREG, &CORE_PIN40_CONFIG, &CORE_PIN40_PADCONFIG, CORE_PIN40_BITMASK},

  67. 	{&CORE_PIN41_PORTREG, &CORE_PIN41_CONFIG, &CORE_PIN41_PADCONFIG, CORE_PIN41_BITMASK},

  68. 	{&CORE_PIN42_PORTREG, &CORE_PIN42_CONFIG, &CORE_PIN42_PADCONFIG, CORE_PIN42_BITMASK},

  69. 	{&CORE_PIN43_PORTREG, &CORE_PIN43_CONFIG, &CORE_PIN43_PADCONFIG, CORE_PIN43_BITMASK},

  70. 	{&CORE_PIN44_PORTREG, &CORE_PIN44_CONFIG, &CORE_PIN44_PADCONFIG, CORE_PIN44_BITMASK},

  71. 	{&CORE_PIN45_PORTREG, &CORE_PIN45_CONFIG, &CORE_PIN45_PADCONFIG, CORE_PIN45_BITMASK},

  72. 	{&CORE_PIN46_PORTREG, &CORE_PIN46_CONFIG, &CORE_PIN46_PADCONFIG, CORE_PIN46_BITMASK},

  73. 	{&CORE_PIN47_PORTREG, &CORE_PIN47_CONFIG, &CORE_PIN47_PADCONFIG, CORE_PIN47_BITMASK},

  74. #endif

  75. };

  76. 

  77. void digitalWrite(uint8_t pin, uint8_t val)

  78. {

  79. 	const struct digital_pin_bitband_and_config_table_struct *p;

  80. 	uint32_t pinmode, mask;

  81. 

  82. 	if (pin >= CORE_NUM_DIGITAL) return;

  83. 	p = digital_pin_to_info_PGM + pin;

  84. 	pinmode = *(p->reg + 1);

  85. 	mask = p->mask;

  86. 	if (pinmode & mask) {

  87. 		// pin is configured for output mode

  88. 		if (val) {

  89. 			*(p->reg + 0x21) = mask; // set register

  90. 		} else {

  91. 			*(p->reg + 0x22) = mask; // clear register

  92. 		}

  93. 	} else {

  94. 		// pin is configured for input mode

  95. 		// writing controls pullup resistor

  96. 

  97. 		// TODO....

  98. 	}

  99. }

  100. 

  101. uint8_t digitalRead(uint8_t pin)

  102. {

  103. 	const struct digital_pin_bitband_and_config_table_struct *p;

  104. 

  105. 	if (pin >= CORE_NUM_DIGITAL) return 0;

  106. 	p = digital_pin_to_info_PGM + pin;

  107. 	return (*(p->reg + 2) & p->mask) ? 1 : 0;

  108. }

  109. 

  110. void pinMode(uint8_t pin, uint8_t mode)

  111. {

  112. 	const struct digital_pin_bitband_and_config_table_struct *p;

  113. 

  114. 	if (pin >= CORE_NUM_DIGITAL) return;

  115. 	p = digital_pin_to_info_PGM + pin;

  116. 	if (mode == OUTPUT || mode == OUTPUT_OPENDRAIN) {

  117. 		*(p->reg + 1) |= p->mask; // TODO: atomic

  118. 		if (mode == OUTPUT) {

  119. 			*(p->pad) = IOMUXC_PAD_DSE(7);

  120. 		} else { // OUTPUT_OPENDRAIN

  121. 			*(p->pad) = IOMUXC_PAD_DSE(7) | IOMUXC_PAD_ODE;

  122. 		}

  123. 	} else {

  124. 		*(p->reg + 1) &= ~(p->mask); // TODO: atomic

  125. 		if (mode == INPUT) {

  126. 			*(p->pad) = IOMUXC_PAD_DSE(7);

  127. 		} else if (mode == INPUT_PULLUP) {

  128. 			*(p->pad) = IOMUXC_PAD_DSE(7) | IOMUXC_PAD_PKE | IOMUXC_PAD_PUE | IOMUXC_PAD_PUS(3) | IOMUXC_PAD_HYS;

  129. 		} else if (mode == INPUT_PULLDOWN) {

  130. 			*(p->pad) = IOMUXC_PAD_DSE(7) | IOMUXC_PAD_PKE | IOMUXC_PAD_PUE | IOMUXC_PAD_PUS(0) | IOMUXC_PAD_HYS;

  131. 		} else { // INPUT_DISABLE

  132. 			*(p->pad) = IOMUXC_PAD_DSE(7) | IOMUXC_PAD_HYS;

  133. 		}

  134. 	}

  135. 	*(p->mux) = 5 | 0x10;

  136. }

  137. 

  138. void _shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t value)

  139. {

  140.         if (bitOrder == LSBFIRST) {

  141.                 shiftOut_lsbFirst(dataPin, clockPin, value);

  142.         } else {

  143.                 shiftOut_msbFirst(dataPin, clockPin, value);

  144.         }

  145. }

  146. 

  147. void shiftOut_lsbFirst(uint8_t dataPin, uint8_t clockPin, uint8_t value)

  148. {

  149.         uint8_t mask;

  150.         for (mask=0x01; mask; mask <<= 1) {

  151.                 digitalWrite(dataPin, value & mask);

  152.                 digitalWrite(clockPin, HIGH);

  153.                 digitalWrite(clockPin, LOW);

  154.         }

  155. }

  156. 

  157. void shiftOut_msbFirst(uint8_t dataPin, uint8_t clockPin, uint8_t value)

  158. {

  159.         uint8_t mask;

  160.         for (mask=0x80; mask; mask >>= 1) {

  161.                 digitalWrite(dataPin, value & mask);

  162.                 digitalWrite(clockPin, HIGH);

  163.                 digitalWrite(clockPin, LOW);

  164.         }

  165. }

  166. 

  167. uint8_t _shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder)

  168. {

  169.         if (bitOrder == LSBFIRST) {

  170.                 return shiftIn_lsbFirst(dataPin, clockPin);

  171.         } else {

  172.                 return shiftIn_msbFirst(dataPin, clockPin);

  173.         }

  174. }

  175. 

  176. uint8_t shiftIn_lsbFirst(uint8_t dataPin, uint8_t clockPin)

  177. {

  178.         uint8_t mask, value=0;

  179.         for (mask=0x01; mask; mask <<= 1) {

  180.                 digitalWrite(clockPin, HIGH);

  181.                 if (digitalRead(dataPin)) value |= mask;

  182.                 digitalWrite(clockPin, LOW);

  183.         }

  184.         return value;

  185. }

  186. 

  187. uint8_t shiftIn_msbFirst(uint8_t dataPin, uint8_t clockPin)

  188. {

  189.         uint8_t mask, value=0;

  190.         for (mask=0x80; mask; mask >>= 1) {

  191.                 digitalWrite(clockPin, HIGH);

  192.                 if (digitalRead(dataPin)) value |= mask;

  193.                 digitalWrite(clockPin, LOW);

  194.         }

  195.         return value;

  196. }

  197. 

  198. //(*portInputRegister(pin) & digitalPinToBitMask(pin))

  199. uint32_t pulseIn_high(uint8_t pin, uint32_t timeout)

  200. {

  201. 	const struct digital_pin_bitband_and_config_table_struct *p;

  202. 	p = digital_pin_to_info_PGM + pin;

  203. 

  204. 	uint32_t usec_start, usec_stop;

  205. 

  206. 	// wait for any previous pulse to end

  207. 	usec_start = micros();

  208. 	while ((*(p->reg + 2) & p->mask)) {

  209. 		if (micros()-usec_start > timeout) return 0;

  210. 	}

  211. 	// wait for the pulse to start

  212. 	usec_start = micros();

  213. 	while (!(*(p->reg + 2) & p->mask)) {

  214. 		if (micros()-usec_start > timeout) return 0;

  215. 	}

  216. 	usec_start = micros();

  217. 	// wait for the pulse to stop

  218. 	while ((*(p->reg + 2) & p->mask)) {

  219. 		if (micros()-usec_start > timeout) return 0;

  220. 	}

  221. 	usec_stop = micros();

  222. 	return usec_stop - usec_start;

  223. }

  224. 

  225. uint32_t pulseIn_low(uint8_t pin, uint32_t timeout)

  226. {

  227. 	const struct digital_pin_bitband_and_config_table_struct *p;

  228. 	p = digital_pin_to_info_PGM + pin;

  229. 

  230. 	uint32_t usec_start, usec_stop;

  231. 

  232. 	// wait for any previous pulse to end

  233. 	usec_start = micros();

  234. 	while (!(*(p->reg + 2) & p->mask)) {

  235. 		if (micros() - usec_start > timeout) return 0;

  236. 	}

  237. 	// wait for the pulse to start

  238. 	usec_start = micros();

  239. 	while ((*(p->reg + 2) & p->mask)) {

  240. 		if (micros() - usec_start > timeout) return 0;

  241. 	}

  242. 	usec_start = micros();

  243. 	// wait for the pulse to stop

  244. 	while (!(*(p->reg + 2) & p->mask)) {

  245. 		if (micros() - usec_start > timeout) return 0;

  246. 	}

  247. 	usec_stop = micros();

  248. 	return usec_stop - usec_start;

  249. }

  250. 

  251. // TODO: an inline version should handle the common case where state is const

  252. uint32_t pulseIn(uint8_t pin, uint8_t state, uint32_t timeout)

  253. {

  254. 	if (pin >= CORE_NUM_DIGITAL) return 0;

  255. 	if (state) return pulseIn_high(pin, timeout);

  256. 	return pulseIn_low(pin, timeout);

  257. }