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Teensy 4.1 core updated for C++20
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teensy-core-4.1/teensy3/mk20dx128.c

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  1. /* Teensyduino Core Library

  2.  * http://www.pjrc.com/teensy/

  3.  * Copyright (c) 2013 PJRC.COM, LLC.

  4.  *

  5.  * Permission is hereby granted, free of charge, to any person obtaining

  6.  * a copy of this software and associated documentation files (the

  7.  * "Software"), to deal in the Software without restriction, including

  8.  * without limitation the rights to use, copy, modify, merge, publish,

  9.  * distribute, sublicense, and/or sell copies of the Software, and to

  10.  * permit persons to whom the Software is furnished to do so, subject to

  11.  * the following conditions:

  12.  *

  13.  * 1. The above copyright notice and this permission notice shall be 

  14.  * included in all copies or substantial portions of the Software.

  15.  *

  16.  * 2. If the Software is incorporated into a build system that allows 

  17.  * selection among a list of target devices, then similar target

  18.  * devices manufactured by PJRC.COM must be included in the list of

  19.  * target devices and selectable in the same manner.

  20.  *

  21.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

  22.  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

  23.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

  24.  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS

  25.  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN

  26.  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

  27.  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

  28.  * SOFTWARE.

  29.  */

  30. 

  31. #include "kinetis.h"

  32. //#include "core_pins.h" // testing only

  33. //#include "ser_print.h" // testing only

  34. 

  35. extern unsigned long _stext;

  36. extern unsigned long _etext;

  37. extern unsigned long _sdata;

  38. extern unsigned long _edata;

  39. extern unsigned long _sbss;

  40. extern unsigned long _ebss;

  41. extern unsigned long _estack;

  42. //extern void __init_array_start(void);

  43. //extern void __init_array_end(void);

  44. 

  45. 

  46. 

  47. extern int main (void);

  48. void ResetHandler(void);

  49. void _init_Teensyduino_internal_(void);

  50. void __libc_init_array(void);

  51. 

  52. 

  53. void fault_isr(void)

  54. {

  55. #if 0

  56. 	uint32_t addr;

  57. 	digitalWriteFast(15, HIGH);

  58. 	ser_print("\nfault: \n??: ");

  59.         asm("ldr %0, [sp, #52]" : "=r" (addr) ::);

  60.         ser_print_hex32(addr);

  61.         ser_print("\n??: ");

  62.         asm("ldr %0, [sp, #48]" : "=r" (addr) ::);

  63.         ser_print_hex32(addr);

  64.         ser_print("\n??: ");

  65.         asm("ldr %0, [sp, #44]" : "=r" (addr) ::);

  66.         ser_print_hex32(addr);

  67.         ser_print("\npsr:");

  68.         asm("ldr %0, [sp, #40]" : "=r" (addr) ::);

  69.         ser_print_hex32(addr);

  70.         ser_print("\nadr:");

  71.         asm("ldr %0, [sp, #36]" : "=r" (addr) ::);

  72.         ser_print_hex32(addr);

  73.         ser_print("\nlr: ");

  74.         asm("ldr %0, [sp, #32]" : "=r" (addr) ::);

  75.         ser_print_hex32(addr);

  76.         ser_print("\nr12:");

  77.         asm("ldr %0, [sp, #28]" : "=r" (addr) ::);

  78.         ser_print_hex32(addr);

  79.         ser_print("\nr3: ");

  80.         asm("ldr %0, [sp, #24]" : "=r" (addr) ::);

  81.         ser_print_hex32(addr);

  82.         ser_print("\nr2: ");

  83.         asm("ldr %0, [sp, #20]" : "=r" (addr) ::);

  84.         ser_print_hex32(addr);

  85.         ser_print("\nr1: ");

  86.         asm("ldr %0, [sp, #16]" : "=r" (addr) ::);

  87.         ser_print_hex32(addr);

  88.         ser_print("\nr0: ");

  89.         asm("ldr %0, [sp, #12]" : "=r" (addr) ::);

  90.         ser_print_hex32(addr);

  91.         ser_print("\nr4: ");

  92.         asm("ldr %0, [sp, #8]" : "=r" (addr) ::);

  93.         ser_print_hex32(addr);

  94.         ser_print("\nlr: ");

  95.         asm("ldr %0, [sp, #4]" : "=r" (addr) ::);

  96.         ser_print_hex32(addr);

  97.         ser_print("\n");

  98.         asm("ldr %0, [sp, #0]" : "=r" (addr) ::);

  99. #endif

  100. 	while (1) {

  101. 		// keep polling some communication while in fault

  102. 		// mode, so we don't completely die.

  103. 		if (SIM_SCGC4 & SIM_SCGC4_USBOTG) usb_isr();

  104. 		if (SIM_SCGC4 & SIM_SCGC4_UART0) uart0_status_isr();

  105. 		if (SIM_SCGC4 & SIM_SCGC4_UART1) uart1_status_isr();

  106. 		if (SIM_SCGC4 & SIM_SCGC4_UART2) uart2_status_isr();

  107. 	}

  108. }

  109. 

  110. void unused_isr(void)

  111. {

  112. 	fault_isr();

  113. }

  114. 

  115. extern volatile uint32_t systick_millis_count;

  116. void systick_default_isr(void)

  117. {

  118. 	systick_millis_count++;

  119. }

  120. 

  121. void nmi_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  122. void hard_fault_isr(void)	__attribute__ ((weak, alias("fault_isr")));

  123. void memmanage_fault_isr(void)	__attribute__ ((weak, alias("fault_isr")));

  124. void bus_fault_isr(void)	__attribute__ ((weak, alias("fault_isr")));

  125. void usage_fault_isr(void)	__attribute__ ((weak, alias("fault_isr")));

  126. void svcall_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  127. void debugmonitor_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  128. void pendablesrvreq_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  129. void systick_isr(void)		__attribute__ ((weak, alias("systick_default_isr")));

  130. 

  131. void dma_ch0_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  132. void dma_ch1_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  133. void dma_ch2_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  134. void dma_ch3_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  135. void dma_ch4_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  136. void dma_ch5_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  137. void dma_ch6_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  138. void dma_ch7_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  139. void dma_ch8_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  140. void dma_ch9_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  141. void dma_ch10_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  142. void dma_ch11_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  143. void dma_ch12_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  144. void dma_ch13_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  145. void dma_ch14_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  146. void dma_ch15_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  147. void dma_error_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  148. void mcm_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  149. void flash_cmd_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  150. void flash_error_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  151. void low_voltage_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  152. void wakeup_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  153. void watchdog_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  154. void i2c0_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  155. void i2c1_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  156. void i2c2_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  157. void spi0_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  158. void spi1_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  159. void spi2_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  160. void sdhc_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  161. void can0_message_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  162. void can0_bus_off_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  163. void can0_error_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  164. void can0_tx_warn_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  165. void can0_rx_warn_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  166. void can0_wakeup_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  167. void i2s0_tx_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  168. void i2s0_rx_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  169. void i2s0_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  170. void uart0_lon_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  171. void uart0_status_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  172. void uart0_error_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  173. void uart1_status_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  174. void uart1_error_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  175. void uart2_status_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  176. void uart2_error_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  177. void uart3_status_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  178. void uart3_error_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  179. void uart4_status_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  180. void uart4_error_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  181. void uart5_status_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  182. void uart5_error_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  183. void adc0_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  184. void adc1_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  185. void cmp0_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  186. void cmp1_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  187. void cmp2_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  188. void ftm0_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  189. void ftm1_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  190. void ftm2_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  191. void ftm3_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  192. void cmt_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  193. void rtc_alarm_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  194. void rtc_seconds_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  195. void pit_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  196. void pit0_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  197. void pit1_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  198. void pit2_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  199. void pit3_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  200. void pdb_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  201. void usb_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  202. void usb_charge_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  203. void dac0_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  204. void dac1_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  205. void tsi0_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  206. void mcg_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  207. void lptmr_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  208. void porta_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  209. void portb_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  210. void portc_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  211. void portd_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  212. void porte_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  213. void portcd_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  214. void software_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  215. 

  216. #if defined(__MK20DX128__)

  217. __attribute__ ((section(".dmabuffers"), used, aligned(256)))

  218. #elif defined(__MK20DX256__)

  219. __attribute__ ((section(".dmabuffers"), used, aligned(512)))

  220. #elif defined(__MKL26Z64__)

  221. __attribute__ ((section(".dmabuffers"), used, aligned(256)))

  222. #endif

  223. void (* _VectorsRam[NVIC_NUM_INTERRUPTS+16])(void);

  224. 

  225. __attribute__ ((section(".vectors"), used))

  226. void (* const _VectorsFlash[NVIC_NUM_INTERRUPTS+16])(void) =

  227. {

  228. 	(void (*)(void))((unsigned long)&_estack),	//  0 ARM: Initial Stack Pointer

  229. 	ResetHandler,					//  1 ARM: Initial Program Counter

  230. 	nmi_isr,					//  2 ARM: Non-maskable Interrupt (NMI)

  231. 	hard_fault_isr,					//  3 ARM: Hard Fault

  232. 	memmanage_fault_isr,				//  4 ARM: MemManage Fault

  233. 	bus_fault_isr,					//  5 ARM: Bus Fault

  234. 	usage_fault_isr,				//  6 ARM: Usage Fault

  235. 	fault_isr,					//  7 --

  236. 	fault_isr,					//  8 --

  237. 	fault_isr,					//  9 --

  238. 	fault_isr,					// 10 --

  239. 	svcall_isr,					// 11 ARM: Supervisor call (SVCall)

  240. 	debugmonitor_isr,				// 12 ARM: Debug Monitor

  241. 	fault_isr,					// 13 --

  242. 	pendablesrvreq_isr,				// 14 ARM: Pendable req serv(PendableSrvReq)

  243. 	systick_isr,					// 15 ARM: System tick timer (SysTick)

  244. #if defined(__MK20DX128__)

  245. 	dma_ch0_isr,					// 16 DMA channel 0 transfer complete

  246. 	dma_ch1_isr,					// 17 DMA channel 1 transfer complete

  247. 	dma_ch2_isr,					// 18 DMA channel 2 transfer complete

  248. 	dma_ch3_isr,					// 19 DMA channel 3 transfer complete

  249. 	dma_error_isr,					// 20 DMA error interrupt channel

  250. 	unused_isr,					// 21 DMA --

  251. 	flash_cmd_isr,					// 22 Flash Memory Command complete

  252. 	flash_error_isr,				// 23 Flash Read collision

  253. 	low_voltage_isr,				// 24 Low-voltage detect/warning

  254. 	wakeup_isr,					// 25 Low Leakage Wakeup

  255. 	watchdog_isr,					// 26 Both EWM and WDOG interrupt

  256. 	i2c0_isr,					// 27 I2C0

  257. 	spi0_isr,					// 28 SPI0

  258. 	i2s0_tx_isr,					// 29 I2S0 Transmit

  259. 	i2s0_rx_isr,					// 30 I2S0 Receive

  260. 	uart0_lon_isr,					// 31 UART0 CEA709.1-B (LON) status

  261. 	uart0_status_isr,				// 32 UART0 status

  262. 	uart0_error_isr,				// 33 UART0 error

  263. 	uart1_status_isr,				// 34 UART1 status

  264. 	uart1_error_isr,				// 35 UART1 error

  265. 	uart2_status_isr,				// 36 UART2 status

  266. 	uart2_error_isr,				// 37 UART2 error

  267. 	adc0_isr,					// 38 ADC0

  268. 	cmp0_isr,					// 39 CMP0

  269. 	cmp1_isr,					// 40 CMP1

  270. 	ftm0_isr,					// 41 FTM0

  271. 	ftm1_isr,					// 42 FTM1

  272. 	cmt_isr,					// 43 CMT

  273. 	rtc_alarm_isr,					// 44 RTC Alarm interrupt

  274. 	rtc_seconds_isr,				// 45 RTC Seconds interrupt

  275. 	pit0_isr,					// 46 PIT Channel 0

  276. 	pit1_isr,					// 47 PIT Channel 1

  277. 	pit2_isr,					// 48 PIT Channel 2

  278. 	pit3_isr,					// 49 PIT Channel 3

  279. 	pdb_isr,					// 50 PDB Programmable Delay Block

  280. 	usb_isr,					// 51 USB OTG

  281. 	usb_charge_isr,					// 52 USB Charger Detect

  282. 	tsi0_isr,					// 53 TSI0

  283. 	mcg_isr,					// 54 MCG

  284. 	lptmr_isr,					// 55 Low Power Timer

  285. 	porta_isr,					// 56 Pin detect (Port A)

  286. 	portb_isr,					// 57 Pin detect (Port B)

  287. 	portc_isr,					// 58 Pin detect (Port C)

  288. 	portd_isr,					// 59 Pin detect (Port D)

  289. 	porte_isr,					// 60 Pin detect (Port E)

  290. 	software_isr,					// 61 Software interrupt

  291. #elif defined(__MK20DX256__)

  292. 	dma_ch0_isr,					// 16 DMA channel 0 transfer complete

  293. 	dma_ch1_isr,					// 17 DMA channel 1 transfer complete

  294. 	dma_ch2_isr,					// 18 DMA channel 2 transfer complete

  295. 	dma_ch3_isr,					// 19 DMA channel 3 transfer complete

  296. 	dma_ch4_isr,					// 20 DMA channel 4 transfer complete

  297. 	dma_ch5_isr,					// 21 DMA channel 5 transfer complete

  298. 	dma_ch6_isr,					// 22 DMA channel 6 transfer complete

  299. 	dma_ch7_isr,					// 23 DMA channel 7 transfer complete

  300. 	dma_ch8_isr,					// 24 DMA channel 8 transfer complete

  301. 	dma_ch9_isr,					// 25 DMA channel 9 transfer complete

  302. 	dma_ch10_isr,					// 26 DMA channel 10 transfer complete

  303. 	dma_ch11_isr,					// 27 DMA channel 10 transfer complete

  304. 	dma_ch12_isr,					// 28 DMA channel 10 transfer complete

  305. 	dma_ch13_isr,					// 29 DMA channel 10 transfer complete

  306. 	dma_ch14_isr,					// 30 DMA channel 10 transfer complete

  307. 	dma_ch15_isr,					// 31 DMA channel 10 transfer complete

  308. 	dma_error_isr,					// 32 DMA error interrupt channel

  309. 	unused_isr,					// 33 --

  310. 	flash_cmd_isr,					// 34 Flash Memory Command complete

  311. 	flash_error_isr,				// 35 Flash Read collision

  312. 	low_voltage_isr,				// 36 Low-voltage detect/warning

  313. 	wakeup_isr,					// 37 Low Leakage Wakeup

  314. 	watchdog_isr,					// 38 Both EWM and WDOG interrupt

  315. 	unused_isr,					// 39 --

  316. 	i2c0_isr,					// 40 I2C0

  317. 	i2c1_isr,					// 41 I2C1

  318. 	spi0_isr,					// 42 SPI0

  319. 	spi1_isr,					// 43 SPI1

  320. 	unused_isr,					// 44 --

  321. 	can0_message_isr,				// 45 CAN OR'ed Message buffer (0-15)

  322. 	can0_bus_off_isr,				// 46 CAN Bus Off

  323. 	can0_error_isr,					// 47 CAN Error

  324. 	can0_tx_warn_isr,				// 48 CAN Transmit Warning

  325. 	can0_rx_warn_isr,				// 49 CAN Receive Warning

  326. 	can0_wakeup_isr,				// 50 CAN Wake Up

  327. 	i2s0_tx_isr,					// 51 I2S0 Transmit

  328. 	i2s0_rx_isr,					// 52 I2S0 Receive

  329. 	unused_isr,					// 53 --

  330. 	unused_isr,					// 54 --

  331. 	unused_isr,					// 55 --

  332. 	unused_isr,					// 56 --

  333. 	unused_isr,					// 57 --

  334. 	unused_isr,					// 58 --

  335. 	unused_isr,					// 59 --

  336. 	uart0_lon_isr,					// 60 UART0 CEA709.1-B (LON) status

  337. 	uart0_status_isr,				// 61 UART0 status

  338. 	uart0_error_isr,				// 62 UART0 error

  339. 	uart1_status_isr,				// 63 UART1 status

  340. 	uart1_error_isr,				// 64 UART1 error

  341. 	uart2_status_isr,				// 65 UART2 status

  342. 	uart2_error_isr,				// 66 UART2 error

  343. 	unused_isr,					// 67 --

  344. 	unused_isr,					// 68 --

  345. 	unused_isr,					// 69 --

  346. 	unused_isr,					// 70 --

  347. 	unused_isr,					// 71 --

  348. 	unused_isr,					// 72 --

  349. 	adc0_isr,					// 73 ADC0

  350. 	adc1_isr,					// 74 ADC1

  351. 	cmp0_isr,					// 75 CMP0

  352. 	cmp1_isr,					// 76 CMP1

  353. 	cmp2_isr,					// 77 CMP2

  354. 	ftm0_isr,					// 78 FTM0

  355. 	ftm1_isr,					// 79 FTM1

  356. 	ftm2_isr,					// 80 FTM2

  357. 	cmt_isr,					// 81 CMT

  358. 	rtc_alarm_isr,					// 82 RTC Alarm interrupt

  359. 	rtc_seconds_isr,				// 83 RTC Seconds interrupt

  360. 	pit0_isr,					// 84 PIT Channel 0

  361. 	pit1_isr,					// 85 PIT Channel 1

  362. 	pit2_isr,					// 86 PIT Channel 2

  363. 	pit3_isr,					// 87 PIT Channel 3

  364. 	pdb_isr,					// 88 PDB Programmable Delay Block

  365. 	usb_isr,					// 89 USB OTG

  366. 	usb_charge_isr,					// 90 USB Charger Detect

  367. 	unused_isr,					// 91 --

  368. 	unused_isr,					// 92 --

  369. 	unused_isr,					// 93 --

  370. 	unused_isr,					// 94 --

  371. 	unused_isr,					// 95 --

  372. 	unused_isr,					// 96 --

  373. 	dac0_isr,					// 97 DAC0

  374. 	unused_isr,					// 98 --

  375. 	tsi0_isr,					// 99 TSI0

  376. 	mcg_isr,					// 100 MCG

  377. 	lptmr_isr,					// 101 Low Power Timer

  378. 	unused_isr,					// 102 --

  379. 	porta_isr,					// 103 Pin detect (Port A)

  380. 	portb_isr,					// 104 Pin detect (Port B)

  381. 	portc_isr,					// 105 Pin detect (Port C)

  382. 	portd_isr,					// 106 Pin detect (Port D)

  383. 	porte_isr,					// 107 Pin detect (Port E)

  384. 	unused_isr,					// 108 --

  385. 	unused_isr,					// 109 --

  386. 	software_isr,					// 110 Software interrupt

  387. #elif defined(__MKL26Z64__)

  388. 	dma_ch0_isr,					// 16 DMA channel 0 transfer complete

  389. 	dma_ch1_isr,					// 17 DMA channel 1 transfer complete

  390. 	dma_ch2_isr,					// 18 DMA channel 2 transfer complete

  391. 	dma_ch3_isr,					// 19 DMA channel 3 transfer complete

  392. 	unused_isr,					// 20 --

  393. 	flash_cmd_isr,					// 21 Flash Memory Command complete

  394. 	low_voltage_isr,				// 22 Low-voltage detect/warning

  395. 	wakeup_isr,					// 23 Low Leakage Wakeup

  396. 	i2c0_isr,					// 24 I2C0

  397. 	i2c1_isr,					// 25 I2C1

  398. 	spi0_isr,					// 26 SPI0

  399. 	spi1_isr,					// 27 SPI1

  400. 	uart0_status_isr,				// 28 UART0 status & error

  401. 	uart1_status_isr,				// 29 UART1 status & error

  402. 	uart2_status_isr,				// 30 UART2 status & error

  403. 	adc0_isr,					// 31 ADC0

  404. 	cmp0_isr,					// 32 CMP0

  405. 	ftm0_isr,					// 33 FTM0

  406. 	ftm1_isr,					// 34 FTM1

  407. 	ftm2_isr,					// 35 FTM2

  408. 	rtc_alarm_isr,					// 36 RTC Alarm interrupt

  409. 	rtc_seconds_isr,				// 37 RTC Seconds interrupt

  410. 	pit_isr,					// 38 PIT Both Channels

  411. 	i2s0_isr,					// 39 I2S0 Transmit & Receive

  412. 	usb_isr,					// 40 USB OTG

  413. 	dac0_isr,					// 41 DAC0

  414. 	tsi0_isr,					// 42 TSI0

  415. 	mcg_isr,					// 43 MCG

  416. 	lptmr_isr,					// 44 Low Power Timer

  417. 	software_isr,					// 45 Software interrupt

  418. 	porta_isr,					// 46 Pin detect (Port A)

  419. 	portcd_isr,					// 47 Pin detect (Port C and D)

  420. #endif

  421. };

  422. 

  423. 

  424. __attribute__ ((section(".flashconfig"), used))

  425. const uint8_t flashconfigbytes[16] = {

  426. 	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,

  427. 	0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF

  428. };

  429. 

  430. 

  431. // Automatically initialize the RTC.  When the build defines the compile

  432. // time, and the user has added a crystal, the RTC will automatically

  433. // begin at the time of the first upload.

  434. #ifndef TIME_T

  435. #define TIME_T 1349049600 // default 1 Oct 2012 (never used, Arduino sets this)

  436. #endif

  437. extern void rtc_set(unsigned long t);

  438. 

  439. 

  440. static void startup_default_early_hook(void) {

  441. #if defined(KINETISK)

  442. 	WDOG_STCTRLH = WDOG_STCTRLH_ALLOWUPDATE;

  443. #elif defined(KINETISL)

  444. 	SIM_COPC = 0;  // disable the watchdog

  445. #endif

  446. }

  447. static void startup_default_late_hook(void) {}

  448. void startup_early_hook(void)		__attribute__ ((weak, alias("startup_default_early_hook")));

  449. void startup_late_hook(void)		__attribute__ ((weak, alias("startup_default_late_hook")));

  450. 

  451. 

  452. __attribute__ ((section(".startup")))

  453. void ResetHandler(void)

  454. {

  455. 	uint32_t *src = &_etext;

  456. 	uint32_t *dest = &_sdata;

  457. 	unsigned int i;

  458. #if F_CPU <= 2000000

  459. 	volatile int n;

  460. #endif

  461. 	//volatile int count;

  462. 

  463. #ifdef KINETISK

  464. 	WDOG_UNLOCK = WDOG_UNLOCK_SEQ1;

  465. 	WDOG_UNLOCK = WDOG_UNLOCK_SEQ2;

  466. 	__asm__ volatile ("nop");

  467. 	__asm__ volatile ("nop");

  468. #endif

  469. 	// programs using the watchdog timer or needing to initialize hardware as

  470. 	// early as possible can implement startup_early_hook()

  471. 	startup_early_hook();

  472. 

  473. 	// enable clocks to always-used peripherals

  474. #if defined(__MK20DX128__)

  475. 	SIM_SCGC5 = 0x00043F82;		// clocks active to all GPIO

  476. 	SIM_SCGC6 = SIM_SCGC6_RTC | SIM_SCGC6_FTM0 | SIM_SCGC6_FTM1 | SIM_SCGC6_ADC0 | SIM_SCGC6_FTFL;

  477. #elif defined(__MK20DX256__)

  478. 	SIM_SCGC3 = SIM_SCGC3_ADC1 | SIM_SCGC3_FTM2;

  479. 	SIM_SCGC5 = 0x00043F82;		// clocks active to all GPIO

  480. 	SIM_SCGC6 = SIM_SCGC6_RTC | SIM_SCGC6_FTM0 | SIM_SCGC6_FTM1 | SIM_SCGC6_ADC0 | SIM_SCGC6_FTFL;

  481. #elif defined(__MKL26Z64__)

  482. 	SIM_SCGC4 = SIM_SCGC4_USBOTG | 0xF0000030;

  483. 	SIM_SCGC5 = 0x00003F82;		// clocks active to all GPIO

  484. 	SIM_SCGC6 = SIM_SCGC6_ADC0 | SIM_SCGC6_TPM0 | SIM_SCGC6_TPM1 | SIM_SCGC6_TPM2 | SIM_SCGC6_FTFL;

  485. #endif

  486. #if 0

  487. 	// testing only, enable ser_print

  488. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV4(1);

  489. 	MCG_C4 |= MCG_C4_DMX32 | MCG_C4_DRST_DRS(1);

  490. 	SIM_SOPT2 = SIM_SOPT2_UART0SRC(1) | SIM_SOPT2_TPMSRC(1);

  491. 	SIM_SCGC4 |= 0x00000400;

  492. 	UART0_BDH = 0;

  493. 	UART0_BDL = 26; // 115200 at 48 MHz

  494. 	UART0_C2 = UART_C2_TE;

  495. 	PORTB_PCR17 = PORT_PCR_MUX(3);

  496. #endif

  497. #ifdef KINETISK

  498. 	// if the RTC oscillator isn't enabled, get it started early

  499. 	if (!(RTC_CR & RTC_CR_OSCE)) {

  500. 		RTC_SR = 0;

  501. 		RTC_CR = RTC_CR_SC16P | RTC_CR_SC4P | RTC_CR_OSCE;

  502. 	}

  503. #endif

  504. 	// release I/O pins hold, if we woke up from VLLS mode

  505. 	if (PMC_REGSC & PMC_REGSC_ACKISO) PMC_REGSC |= PMC_REGSC_ACKISO;

  506. 

  507.     // since this is a write once register, make it visible to all F_CPU's

  508.     // so we can into other sleep modes in the future at any speed

  509. 	SMC_PMPROT = SMC_PMPROT_AVLP | SMC_PMPROT_ALLS | SMC_PMPROT_AVLLS;

  510.     

  511. 	// TODO: do this while the PLL is waiting to lock....

  512. 	while (dest < &_edata) *dest++ = *src++;

  513. 	dest = &_sbss;

  514. 	while (dest < &_ebss) *dest++ = 0;

  515. 

  516. 	// default all interrupts to medium priority level

  517. 	for (i=0; i < NVIC_NUM_INTERRUPTS + 16; i++) _VectorsRam[i] = _VectorsFlash[i];

  518. 	for (i=0; i < NVIC_NUM_INTERRUPTS; i++) NVIC_SET_PRIORITY(i, 128);

  519. 	SCB_VTOR = (uint32_t)_VectorsRam;	// use vector table in RAM

  520. 

  521. 	// hardware always starts in FEI mode

  522. 	//  C1[CLKS] bits are written to 00

  523. 	//  C1[IREFS] bit is written to 1

  524. 	//  C6[PLLS] bit is written to 0

  525. // MCG_SC[FCDIV] defaults to divide by two for internal ref clock

  526. // I tried changing MSG_SC to divide by 1, it didn't work for me

  527. #if F_CPU <= 2000000

  528. 	// use the internal oscillator

  529. 	MCG_C1 = MCG_C1_CLKS(1) | MCG_C1_IREFS;

  530. 	// wait for MCGOUT to use oscillator

  531. 	while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(1)) ;

  532. 	for (n=0; n<10; n++) ; // TODO: why do we get 2 mA extra without this delay?

  533. 	MCG_C2 = MCG_C2_IRCS;

  534. 	while (!(MCG_S & MCG_S_IRCST)) ;

  535. 	// now in FBI mode:

  536. 	//  C1[CLKS] bits are written to 01

  537. 	//  C1[IREFS] bit is written to 1

  538. 	//  C6[PLLS] is written to 0

  539. 	//  C2[LP] is written to 0

  540. 	MCG_C2 = MCG_C2_IRCS | MCG_C2_LP;

  541. 	// now in BLPI mode:

  542. 	//  C1[CLKS] bits are written to 01

  543. 	//  C1[IREFS] bit is written to 1

  544. 	//  C6[PLLS] bit is written to 0

  545. 	//  C2[LP] bit is written to 1

  546. #else

  547. 	// enable capacitors for crystal

  548. 	OSC0_CR = OSC_SC8P | OSC_SC2P;

  549. 	// enable osc, 8-32 MHz range, low power mode

  550. 	MCG_C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS;

  551. 	// switch to crystal as clock source, FLL input = 16 MHz / 512

  552. 	MCG_C1 =  MCG_C1_CLKS(2) | MCG_C1_FRDIV(4);

  553. 	// wait for crystal oscillator to begin

  554. 	while ((MCG_S & MCG_S_OSCINIT0) == 0) ;

  555. 	// wait for FLL to use oscillator

  556. 	while ((MCG_S & MCG_S_IREFST) != 0) ;

  557. 	// wait for MCGOUT to use oscillator

  558. 	while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2)) ;

  559. 

  560. 	// now in FBE mode

  561. 	//  C1[CLKS] bits are written to 10

  562. 	//  C1[IREFS] bit is written to 0

  563. 	//  C1[FRDIV] must be written to divide xtal to 31.25-39 kHz

  564. 	//  C6[PLLS] bit is written to 0

  565. 	//  C2[LP] is written to 0

  566.   #if F_CPU <= 16000000

  567. 	// if the crystal is fast enough, use it directly (no FLL or PLL)

  568. 	MCG_C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS | MCG_C2_LP;

  569. 	// BLPE mode:

  570. 	//   C1[CLKS] bits are written to 10

  571. 	//   C1[IREFS] bit is written to 0

  572. 	//   C2[LP] bit is written to 1

  573.   #else

  574. 	// if we need faster than the crystal, turn on the PLL

  575.     #if F_CPU == 72000000

  576. 	MCG_C5 = MCG_C5_PRDIV0(5);		 // config PLL input for 16 MHz Crystal / 6 = 2.667 Hz

  577.     #else

  578. 	MCG_C5 = MCG_C5_PRDIV0(3);		 // config PLL input for 16 MHz Crystal / 4 = 4 MHz

  579.     #endif

  580.     #if F_CPU == 168000000

  581. 	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(18); // config PLL for 168 MHz output

  582.     #elif F_CPU == 144000000

  583. 	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(12); // config PLL for 144 MHz output

  584.     #elif F_CPU == 120000000

  585. 	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(6); // config PLL for 120 MHz output

  586.     #elif F_CPU == 72000000

  587. 	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(3); // config PLL for 72 MHz output

  588.     #else

  589. 	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0); // config PLL for 96 MHz output

  590.     #endif

  591. 	// wait for PLL to start using xtal as its input

  592. 	while (!(MCG_S & MCG_S_PLLST)) ;

  593. 	// wait for PLL to lock

  594. 	while (!(MCG_S & MCG_S_LOCK0)) ;

  595. 	// now we're in PBE mode

  596.   #endif

  597. #endif

  598. 	// now program the clock dividers

  599. #if F_CPU == 168000000

  600. 	// config divisors: 168 MHz core, 56 MHz bus, 33.6 MHz flash, USB = 168 * 2 / 7

  601. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(2) |	 SIM_CLKDIV1_OUTDIV4(4);

  602. 	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(6) | SIM_CLKDIV2_USBFRAC;

  603. #elif F_CPU == 144000000

  604. 	// config divisors: 144 MHz core, 48 MHz bus, 28.8 MHz flash, USB = 144 / 3

  605. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(2) |	 SIM_CLKDIV1_OUTDIV4(4);

  606. 	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(2);

  607. #elif F_CPU == 120000000

  608. 	// config divisors: 120 MHz core, 60 MHz bus, 24 MHz flash, USB = 128 * 2 / 5

  609. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) |	 SIM_CLKDIV1_OUTDIV4(4);

  610. 	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC;

  611. #elif F_CPU == 96000000

  612. 	// config divisors: 96 MHz core, 48 MHz bus, 24 MHz flash, USB = 96 / 2

  613. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) |	 SIM_CLKDIV1_OUTDIV4(3);

  614. 	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1);

  615. #elif F_CPU == 72000000

  616. 	// config divisors: 72 MHz core, 36 MHz bus, 24 MHz flash, USB = 72 * 2 / 3

  617. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) |	 SIM_CLKDIV1_OUTDIV4(2);

  618. 	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC;

  619. #elif F_CPU == 48000000

  620. 	// config divisors: 48 MHz core, 48 MHz bus, 24 MHz flash, USB = 96 / 2

  621. 	#if defined(KINETISK)

  622. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV2(1) |	 SIM_CLKDIV1_OUTDIV4(3);

  623. 	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1);

  624. 	#elif defined(KINETISL)

  625. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV4(1);

  626. 	#endif

  627. #elif F_CPU == 24000000

  628. 	// config divisors: 24 MHz core, 24 MHz bus, 24 MHz flash, USB = 96 / 2

  629. 	#if defined(KINETISK)

  630. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV2(3) |	 SIM_CLKDIV1_OUTDIV4(3);

  631. 	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1);

  632. 	#elif defined(KINETISL)

  633. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV4(0);

  634. 	#endif

  635. #elif F_CPU == 16000000

  636. 	// config divisors: 16 MHz core, 16 MHz bus, 16 MHz flash

  637. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) |	 SIM_CLKDIV1_OUTDIV4(0);

  638. #elif F_CPU == 8000000

  639. 	// config divisors: 8 MHz core, 8 MHz bus, 8 MHz flash

  640. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV2(1) |	 SIM_CLKDIV1_OUTDIV4(1);

  641. #elif F_CPU == 4000000

  642.     // config divisors: 4 MHz core, 4 MHz bus, 2 MHz flash

  643.     // since we are running from external clock 16MHz

  644.     // fix outdiv too -> cpu 16/4, bus 16/4, flash 16/4

  645.     // here we can go into vlpr?

  646. 	// config divisors: 4 MHz core, 4 MHz bus, 4 MHz flash

  647. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV2(3) |	 SIM_CLKDIV1_OUTDIV4(3);

  648. #elif F_CPU == 2000000

  649.     // since we are running from the fast internal reference clock 4MHz

  650.     // but is divided down by 2 so we actually have a 2MHz, MCG_SC[FCDIV] default is 2

  651.     // fix outdiv -> cpu 2/1, bus 2/1, flash 2/2

  652. 	// config divisors: 2 MHz core, 2 MHz bus, 1 MHz flash

  653. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) |	 SIM_CLKDIV1_OUTDIV4(1);

  654. #else

  655. #error "Error, F_CPU must be 168, 144, 120, 96, 72, 48, 24, 16, 8, 4, or 2 MHz"

  656. #endif

  657. 

  658. #if F_CPU > 16000000

  659. 	// switch to PLL as clock source, FLL input = 16 MHz / 512

  660. 	MCG_C1 = MCG_C1_CLKS(0) | MCG_C1_FRDIV(4);

  661. 	// wait for PLL clock to be used

  662. 	while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(3)) ;

  663. 	// now we're in PEE mode

  664. 	// USB uses PLL clock, trace is CPU clock, CLKOUT=OSCERCLK0

  665. 	#if defined(KINETISK)

  666. 	SIM_SOPT2 = SIM_SOPT2_USBSRC | SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_TRACECLKSEL

  667. 		| SIM_SOPT2_CLKOUTSEL(6);

  668. 	#elif defined(KINETISL)

  669. 	SIM_SOPT2 = SIM_SOPT2_USBSRC | SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_CLKOUTSEL(6)

  670. 		| SIM_SOPT2_UART0SRC(1) | SIM_SOPT2_TPMSRC(1);

  671. 	#endif

  672. #else

  673. 	SIM_SOPT2 = SIM_SOPT2_TRACECLKSEL | SIM_SOPT2_CLKOUTSEL(3);

  674. #endif

  675. 

  676. #if F_CPU <= 2000000

  677.     // since we are not going into "stop mode" i removed it

  678. 	SMC_PMCTRL = SMC_PMCTRL_RUNM(2); // VLPR mode :-)

  679. #endif

  680. 

  681. 	// initialize the SysTick counter

  682. 	SYST_RVR = (F_CPU / 1000) - 1;

  683. 	SYST_CSR = SYST_CSR_CLKSOURCE | SYST_CSR_TICKINT | SYST_CSR_ENABLE;

  684. 

  685. 	//init_pins();

  686. 	__enable_irq();

  687. 

  688. 	_init_Teensyduino_internal_();

  689. #if defined(KINETISK)

  690. 	if (RTC_SR & RTC_SR_TIF) {

  691. 		// TODO: this should probably set the time more agressively, if

  692. 		// we could reliably detect the first reboot after programming.

  693. 		rtc_set(TIME_T);

  694. 	}

  695. #endif

  696. 	__libc_init_array();

  697. 

  698. 	startup_late_hook();

  699. 	main();

  700. 	while (1) ;

  701. }

  702. 

  703. char *__brkval = (char *)&_ebss;

  704. 

  705. void * _sbrk(int incr)

  706. {

  707. 	char *prev = __brkval;

  708. 	__brkval += incr;

  709. 	return prev;

  710. }

  711. 

  712. __attribute__((weak)) 

  713. int _read(int file, char *ptr, int len)

  714. {

  715. 	return 0;

  716. }

  717. 

  718. __attribute__((weak)) 

  719. int _close(int fd)

  720. {

  721. 	return -1;

  722. }

  723. 

  724. #include <sys/stat.h>

  725. 

  726. __attribute__((weak)) 

  727. int _fstat(int fd, struct stat *st)

  728. {

  729. 	st->st_mode = S_IFCHR;

  730. 	return 0;

  731. }

  732. 

  733. __attribute__((weak)) 

  734. int _isatty(int fd)

  735. {

  736. 	return 1;

  737. }

  738. 

  739. __attribute__((weak)) 

  740. int _lseek(int fd, long long offset, int whence)

  741. {

  742. 	return -1;

  743. }

  744. 

  745. __attribute__((weak)) 

  746. void _exit(int status)

  747. {

  748. 	while (1);

  749. }

  750. 

  751. __attribute__((weak)) 

  752. void __cxa_pure_virtual()

  753. {

  754. 	while (1);

  755. }

  756. 

  757. __attribute__((weak)) 

  758. int __cxa_guard_acquire (char *g) 

  759. {

  760. 	return !(*g);

  761. }

  762. 

  763. __attribute__((weak)) 

  764. void __cxa_guard_release(char *g)

  765. {

  766. 	*g = 1;

  767. }

  768. 

  769. int nvic_execution_priority(void)

  770. {

  771. 	int priority=256;

  772. 	uint32_t primask, faultmask, basepri, ipsr;

  773. 

  774. 	// full algorithm in ARM DDI0403D, page B1-639

  775. 	// this isn't quite complete, but hopefully good enough

  776. 	__asm__ volatile("mrs %0, faultmask\n" : "=r" (faultmask)::);

  777. 	if (faultmask) return -1;

  778. 	__asm__ volatile("mrs %0, primask\n" : "=r" (primask)::);

  779. 	if (primask) return 0;

  780. 	__asm__ volatile("mrs %0, ipsr\n" : "=r" (ipsr)::);

  781. 	if (ipsr) {

  782. 		if (ipsr < 16) priority = 0; // could be non-zero

  783. 		else priority = NVIC_GET_PRIORITY(ipsr - 16);

  784. 	}

  785. 	__asm__ volatile("mrs %0, basepri\n" : "=r" (basepri)::);

  786. 	if (basepri > 0 && basepri < priority) priority = basepri;

  787. 	return priority;

  788. }