Teensy 4.1 core updated for C++20
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  1. #ifndef DMAChannel_h_
  2. #define DMAChannel_h_
  3. #include "kinetis.h"
  4. // This code is a work-in-progress. It's incomplete and not usable yet...
  5. //
  6. // http://forum.pjrc.com/threads/25778-Could-there-be-something-like-an-ISR-template-function/page3
  7. // known libraries with DMA usage (in need of porting to this new scheme):
  8. //
  9. // https://github.com/PaulStoffregen/Audio
  10. // https://github.com/PaulStoffregen/OctoWS2811
  11. // https://github.com/pedvide/ADC
  12. // https://github.com/duff2013/SerialEvent
  13. // https://github.com/pixelmatix/SmartMatrix
  14. // https://github.com/crteensy/DmaSpi
  15. #ifdef __cplusplus
  16. #define DMACHANNEL_HAS_BEGIN
  17. class DMABaseClass {
  18. public:
  19. typedef struct __attribute__((packed)) {
  20. volatile const void * volatile SADDR;
  21. int16_t SOFF;
  22. union { uint16_t ATTR;
  23. struct { uint8_t ATTR_DST; uint8_t ATTR_SRC; }; };
  24. union { uint32_t NBYTES; uint32_t NBYTES_MLNO;
  25. uint32_t NBYTES_MLOFFNO; uint32_t NBYTES_MLOFFYES; };
  26. int32_t SLAST;
  27. volatile void * volatile DADDR;
  28. int16_t DOFF;
  29. union { volatile uint16_t CITER;
  30. volatile uint16_t CITER_ELINKYES; volatile uint16_t CITER_ELINKNO; };
  31. int32_t DLASTSGA;
  32. volatile uint16_t CSR;
  33. union { volatile uint16_t BITER;
  34. volatile uint16_t BITER_ELINKYES; volatile uint16_t BITER_ELINKNO; };
  35. } TCD_t;
  36. TCD_t *TCD;
  37. /***************************************/
  38. /** Data Transfer **/
  39. /***************************************/
  40. // Use a single variable as the data source. Typically a register
  41. // for receiving data from one of the hardware peripherals is used.
  42. void source(volatile const signed char &p) { source(*(volatile const uint8_t *)&p); }
  43. void source(volatile const unsigned char &p) {
  44. TCD->SADDR = &p;
  45. TCD->SOFF = 0;
  46. TCD->ATTR_SRC = 0;
  47. if ((uint32_t)&p < 0x40000000 || TCD->NBYTES == 0) TCD->NBYTES = 1;
  48. TCD->SLAST = 0;
  49. }
  50. void source(volatile const signed short &p) { source(*(volatile const uint16_t *)&p); }
  51. void source(volatile const unsigned short &p) {
  52. TCD->SADDR = &p;
  53. TCD->SOFF = 0;
  54. TCD->ATTR_SRC = 1;
  55. if ((uint32_t)&p < 0x40000000 || TCD->NBYTES == 0) TCD->NBYTES = 2;
  56. TCD->SLAST = 0;
  57. }
  58. void source(volatile const signed int &p) { source(*(volatile const uint32_t *)&p); }
  59. void source(volatile const unsigned int &p) { source(*(volatile const uint32_t *)&p); }
  60. void source(volatile const signed long &p) { source(*(volatile const uint32_t *)&p); }
  61. void source(volatile const unsigned long &p) {
  62. TCD->SADDR = &p;
  63. TCD->SOFF = 0;
  64. TCD->ATTR_SRC = 2;
  65. if ((uint32_t)&p < 0x40000000 || TCD->NBYTES == 0) TCD->NBYTES = 4;
  66. TCD->SLAST = 0;
  67. }
  68. // Use a buffer (array of data) as the data source. Typically a
  69. // buffer for transmitting data is used.
  70. void sourceBuffer(volatile const signed char p[], unsigned int len) {
  71. sourceBuffer((volatile const uint8_t *)p, len); }
  72. void sourceBuffer(volatile const unsigned char p[], unsigned int len) {
  73. TCD->SADDR = p;
  74. TCD->SOFF = 1;
  75. TCD->ATTR_SRC = 0;
  76. TCD->NBYTES = 1;
  77. TCD->SLAST = -len;
  78. TCD->BITER = len;
  79. TCD->CITER = len;
  80. }
  81. void sourceBuffer(volatile const signed short p[], unsigned int len) {
  82. sourceBuffer((volatile const uint16_t *)p, len); }
  83. void sourceBuffer(volatile const unsigned short p[], unsigned int len) {
  84. TCD->SADDR = p;
  85. TCD->SOFF = 2;
  86. TCD->ATTR_SRC = 1;
  87. TCD->NBYTES = 2;
  88. TCD->SLAST = -len;
  89. TCD->BITER = len / 2;
  90. TCD->CITER = len / 2;
  91. }
  92. void sourceBuffer(volatile const signed int p[], unsigned int len) {
  93. sourceBuffer((volatile const uint32_t *)p, len); }
  94. void sourceBuffer(volatile const unsigned int p[], unsigned int len) {
  95. sourceBuffer((volatile const uint32_t *)p, len); }
  96. void sourceBuffer(volatile const signed long p[], unsigned int len) {
  97. sourceBuffer((volatile const uint32_t *)p, len); }
  98. void sourceBuffer(volatile const unsigned long p[], unsigned int len) {
  99. TCD->SADDR = p;
  100. TCD->SOFF = 4;
  101. TCD->ATTR_SRC = 2;
  102. TCD->NBYTES = 4;
  103. TCD->SLAST = -len;
  104. TCD->BITER = len / 4;
  105. TCD->CITER = len / 4;
  106. }
  107. // Use a circular buffer as the data source
  108. void sourceCircular(volatile const signed char p[], unsigned int len) {
  109. sourceCircular((volatile const uint8_t *)p, len); }
  110. void sourceCircular(volatile const unsigned char p[], unsigned int len) {
  111. TCD->SADDR = p;
  112. TCD->SOFF = 1;
  113. TCD->ATTR_SRC = ((31 - __builtin_clz(len)) << 3);
  114. TCD->NBYTES = 1;
  115. TCD->SLAST = 0;
  116. TCD->BITER = len;
  117. TCD->CITER = len;
  118. }
  119. void sourceCircular(volatile const signed short p[], unsigned int len) {
  120. sourceCircular((volatile const uint16_t *)p, len); }
  121. void sourceCircular(volatile const unsigned short p[], unsigned int len) {
  122. TCD->SADDR = p;
  123. TCD->SOFF = 2;
  124. TCD->ATTR_SRC = ((31 - __builtin_clz(len)) << 3) | 1;
  125. TCD->NBYTES = 2;
  126. TCD->SLAST = 0;
  127. TCD->BITER = len / 2;
  128. TCD->CITER = len / 2;
  129. }
  130. void sourceCircular(volatile const signed int p[], unsigned int len) {
  131. sourceCircular((volatile const uint32_t *)p, len); }
  132. void sourceCircular(volatile const unsigned int p[], unsigned int len) {
  133. sourceCircular((volatile const uint32_t *)p, len); }
  134. void sourceCircular(volatile const signed long p[], unsigned int len) {
  135. sourceCircular((volatile const uint32_t *)p, len); }
  136. void sourceCircular(volatile const unsigned long p[], unsigned int len) {
  137. TCD->SADDR = p;
  138. TCD->SOFF = 4;
  139. TCD->ATTR_SRC = ((31 - __builtin_clz(len)) << 3) | 2;
  140. TCD->NBYTES = 4;
  141. TCD->SLAST = 0;
  142. TCD->BITER = len / 4;
  143. TCD->CITER = len / 4;
  144. }
  145. // Use a single variable as the data destination. Typically a register
  146. // for transmitting data to one of the hardware peripherals is used.
  147. void destination(volatile signed char &p) { destination(*(volatile uint8_t *)&p); }
  148. void destination(volatile unsigned char &p) {
  149. TCD->DADDR = &p;
  150. TCD->DOFF = 0;
  151. TCD->ATTR_DST = 0;
  152. if ((uint32_t)&p < 0x40000000 || TCD->NBYTES == 0) TCD->NBYTES = 1;
  153. TCD->DLASTSGA = 0;
  154. }
  155. void destination(volatile signed short &p) { destination(*(volatile uint16_t *)&p); }
  156. void destination(volatile unsigned short &p) {
  157. TCD->DADDR = &p;
  158. TCD->DOFF = 0;
  159. TCD->ATTR_DST = 1;
  160. if ((uint32_t)&p < 0x40000000 || TCD->NBYTES == 0) TCD->NBYTES = 2;
  161. TCD->DLASTSGA = 0;
  162. }
  163. void destination(volatile signed int &p) { destination(*(volatile uint32_t *)&p); }
  164. void destination(volatile unsigned int &p) { destination(*(volatile uint32_t *)&p); }
  165. void destination(volatile signed long &p) { destination(*(volatile uint32_t *)&p); }
  166. void destination(volatile unsigned long &p) {
  167. TCD->DADDR = &p;
  168. TCD->DOFF = 0;
  169. TCD->ATTR_DST = 2;
  170. if ((uint32_t)&p < 0x40000000 || TCD->NBYTES == 0) TCD->NBYTES = 4;
  171. TCD->DLASTSGA = 0;
  172. }
  173. // Use a buffer (array of data) as the data destination. Typically a
  174. // buffer for receiving data is used.
  175. void destinationBuffer(volatile signed char p[], unsigned int len) {
  176. destinationBuffer((volatile uint8_t *)p, len); }
  177. void destinationBuffer(volatile unsigned char p[], unsigned int len) {
  178. TCD->DADDR = p;
  179. TCD->DOFF = 1;
  180. TCD->ATTR_DST = 0;
  181. TCD->NBYTES = 1;
  182. TCD->DLASTSGA = -len;
  183. TCD->BITER = len;
  184. TCD->CITER = len;
  185. }
  186. void destinationBuffer(volatile signed short p[], unsigned int len) {
  187. destinationBuffer((volatile uint16_t *)p, len); }
  188. void destinationBuffer(volatile unsigned short p[], unsigned int len) {
  189. TCD->DADDR = p;
  190. TCD->DOFF = 2;
  191. TCD->ATTR_DST = 1;
  192. TCD->NBYTES = 2;
  193. TCD->DLASTSGA = -len;
  194. TCD->BITER = len / 2;
  195. TCD->CITER = len / 2;
  196. }
  197. void destinationBuffer(volatile signed int p[], unsigned int len) {
  198. destinationBuffer((volatile uint32_t *)p, len); }
  199. void destinationBuffer(volatile unsigned int p[], unsigned int len) {
  200. destinationBuffer((volatile uint32_t *)p, len); }
  201. void destinationBuffer(volatile signed long p[], unsigned int len) {
  202. destinationBuffer((volatile uint32_t *)p, len); }
  203. void destinationBuffer(volatile unsigned long p[], unsigned int len) {
  204. TCD->DADDR = p;
  205. TCD->DOFF = 4;
  206. TCD->ATTR_DST = 2;
  207. TCD->NBYTES = 4;
  208. TCD->DLASTSGA = -len;
  209. TCD->BITER = len / 4;
  210. TCD->CITER = len / 4;
  211. }
  212. // Use a circular buffer as the data destination
  213. void destinationCircular(volatile signed char p[], unsigned int len) {
  214. destinationCircular((volatile uint8_t *)p, len); }
  215. void destinationCircular(volatile unsigned char p[], unsigned int len) {
  216. TCD->DADDR = p;
  217. TCD->DOFF = 1;
  218. TCD->ATTR_DST = ((31 - __builtin_clz(len)) << 3);
  219. TCD->NBYTES = 1;
  220. TCD->DLASTSGA = 0;
  221. TCD->BITER = len;
  222. TCD->CITER = len;
  223. }
  224. void destinationCircular(volatile signed short p[], unsigned int len) {
  225. destinationCircular((volatile uint16_t *)p, len); }
  226. void destinationCircular(volatile unsigned short p[], unsigned int len) {
  227. TCD->DADDR = p;
  228. TCD->DOFF = 2;
  229. TCD->ATTR_DST = ((31 - __builtin_clz(len)) << 3) | 1;
  230. TCD->NBYTES = 2;
  231. TCD->DLASTSGA = 0;
  232. TCD->BITER = len / 2;
  233. TCD->CITER = len / 2;
  234. }
  235. void destinationCircular(volatile signed int p[], unsigned int len) {
  236. destinationCircular((volatile uint32_t *)p, len); }
  237. void destinationCircular(volatile unsigned int p[], unsigned int len) {
  238. destinationCircular((volatile uint32_t *)p, len); }
  239. void destinationCircular(volatile signed long p[], unsigned int len) {
  240. destinationCircular((volatile uint32_t *)p, len); }
  241. void destinationCircular(volatile unsigned long p[], unsigned int len) {
  242. TCD->DADDR = p;
  243. TCD->DOFF = 4;
  244. TCD->ATTR_DST = ((31 - __builtin_clz(len)) << 3) | 2;
  245. TCD->NBYTES = 4;
  246. TCD->DLASTSGA = 0;
  247. TCD->BITER = len / 4;
  248. TCD->CITER = len / 4;
  249. }
  250. /*************************************************/
  251. /** Quantity of Data to Transfer **/
  252. /*************************************************/
  253. // Set the data size used for each triggered transfer
  254. void transferSize(unsigned int len) {
  255. if (len == 4) {
  256. TCD->NBYTES = 4;
  257. if (TCD->SOFF != 0) TCD->SOFF = 4;
  258. if (TCD->DOFF != 0) TCD->DOFF = 4;
  259. TCD->ATTR = (TCD->ATTR & 0xF8F8) | 0x0202;
  260. } else if (len == 2) {
  261. TCD->NBYTES = 2;
  262. if (TCD->SOFF != 0) TCD->SOFF = 2;
  263. if (TCD->DOFF != 0) TCD->DOFF = 2;
  264. TCD->ATTR = (TCD->ATTR & 0xF8F8) | 0x0101;
  265. } else {
  266. TCD->NBYTES = 1;
  267. if (TCD->SOFF != 0) TCD->SOFF = 1;
  268. if (TCD->DOFF != 0) TCD->DOFF = 1;
  269. TCD->ATTR = TCD->ATTR & 0xF8F8;
  270. }
  271. }
  272. // Set the number of transfers (number of triggers until complete)
  273. void transferCount(unsigned int len) {
  274. if (len > 32767) return;
  275. if (len >= 512) {
  276. TCD->BITER = len;
  277. TCD->CITER = len;
  278. } else {
  279. TCD->BITER = (TCD->BITER & 0xFE00) | len;
  280. TCD->CITER = (TCD->CITER & 0xFE00) | len;
  281. }
  282. }
  283. /*************************************************/
  284. /** Special Options / Features **/
  285. /*************************************************/
  286. void interruptAtCompletion(void) {
  287. TCD->CSR |= DMA_TCD_CSR_INTMAJOR;
  288. }
  289. void interruptAtHalf(void) {
  290. TCD->CSR |= DMA_TCD_CSR_INTHALF;
  291. }
  292. void disableOnCompletion(void) {
  293. TCD->CSR |= DMA_TCD_CSR_DREQ;
  294. }
  295. void replaceSettingsOnCompletion(const DMABaseClass &settings) {
  296. TCD->DLASTSGA = (int32_t)(settings.TCD);
  297. TCD->CSR &= ~DMA_TCD_CSR_DONE;
  298. TCD->CSR |= DMA_TCD_CSR_ESG;
  299. }
  300. protected:
  301. // users should not be able to create instances of DMABaseClass, which
  302. // require the inheriting class to initialize the TCD pointer.
  303. DMABaseClass() {}
  304. static inline void copy_tcd(TCD_t *dst, const TCD_t *src) {
  305. const uint32_t *p = (const uint32_t *)src;
  306. uint32_t *q = (uint32_t *)dst;
  307. uint32_t t1, t2, t3, t4;
  308. t1 = *p++; t2 = *p++; t3 = *p++; t4 = *p++;
  309. *q++ = t1; *q++ = t2; *q++ = t3; *q++ = t4;
  310. t1 = *p++; t2 = *p++; t3 = *p++; t4 = *p++;
  311. *q++ = t1; *q++ = t2; *q++ = t3; *q++ = t4;
  312. }
  313. };
  314. // DMASetting represents settings stored only in memory, which can be
  315. // applied to any DMA channel.
  316. class DMASetting : public DMABaseClass {
  317. public:
  318. DMASetting() {
  319. TCD = &tcddata;
  320. }
  321. DMASetting(const DMASetting &c) {
  322. TCD = &tcddata;
  323. *this = c;
  324. }
  325. DMASetting(const DMABaseClass &c) {
  326. TCD = &tcddata;
  327. *this = c;
  328. }
  329. DMASetting & operator = (const DMABaseClass &rhs) {
  330. copy_tcd(TCD, rhs.TCD);
  331. return *this;
  332. }
  333. private:
  334. TCD_t tcddata __attribute__((aligned(32)));
  335. };
  336. // DMAChannel reprents an actual DMA channel and its current settings
  337. class DMAChannel : public DMABaseClass {
  338. public:
  339. /*************************************************/
  340. /** Channel Allocation **/
  341. /*************************************************/
  342. DMAChannel() {
  343. begin();
  344. }
  345. DMAChannel(const DMAChannel &c) {
  346. TCD = c.TCD;
  347. channel = c.channel;
  348. }
  349. DMAChannel(const DMASetting &c) {
  350. begin();
  351. copy_tcd(TCD, c.TCD);
  352. }
  353. DMAChannel & operator = (const DMAChannel &rhs) {
  354. if (channel != rhs.channel) {
  355. release();
  356. TCD = rhs.TCD;
  357. channel = rhs.channel;
  358. }
  359. return *this;
  360. }
  361. DMAChannel & operator = (const DMASetting &rhs) {
  362. copy_tcd(TCD, rhs.TCD);
  363. return *this;
  364. }
  365. ~DMAChannel() {
  366. release();
  367. }
  368. void begin(void);
  369. private:
  370. void release(void);
  371. public:
  372. /***************************************/
  373. /** Triggering **/
  374. /***************************************/
  375. // Triggers cause the DMA channel to actually move data. Each
  376. // trigger moves a single data unit, which is typically 8, 16 or
  377. // 32 bits. If a channel is configured for 200 transfers
  378. // Use a hardware trigger to make the DMA channel run
  379. void triggerAtHardwareEvent(uint8_t source) {
  380. volatile uint8_t *mux;
  381. mux = (volatile uint8_t *)&(DMAMUX0_CHCFG0) + channel;
  382. *mux = 0;
  383. *mux = (source & 63) | DMAMUX_ENABLE;
  384. }
  385. // Use another DMA channel as the trigger, causing this
  386. // channel to trigger after each transfer is makes, except
  387. // the its last transfer. This effectively makes the 2
  388. // channels run in parallel until the last transfer
  389. void triggerAtTransfersOf(DMABaseClass &ch) {
  390. ch.TCD->BITER = (ch.TCD->BITER & ~DMA_TCD_BITER_ELINKYES_LINKCH_MASK)
  391. | DMA_TCD_BITER_ELINKYES_LINKCH(channel) | DMA_TCD_BITER_ELINKYES_ELINK;
  392. ch.TCD->CITER = ch.TCD->BITER ;
  393. }
  394. // Use another DMA channel as the trigger, causing this
  395. // channel to trigger when the other channel completes.
  396. void triggerAtCompletionOf(DMABaseClass &ch) {
  397. ch.TCD->CSR = (ch.TCD->CSR & ~(DMA_TCD_CSR_MAJORLINKCH_MASK|DMA_TCD_CSR_DONE))
  398. | DMA_TCD_CSR_MAJORLINKCH(channel) | DMA_TCD_CSR_MAJORELINK;
  399. }
  400. // Cause this DMA channel to be continuously triggered, so
  401. // it will move data as rapidly as possible, without waiting.
  402. // Normally this would be used with disableOnCompletion().
  403. void triggerContinuously(void) {
  404. volatile uint8_t *mux = (volatile uint8_t *)&DMAMUX0_CHCFG0;
  405. mux[channel] = 0;
  406. #if DMAMUX_NUM_SOURCE_ALWAYS >= DMA_NUM_CHANNELS
  407. mux[channel] = DMAMUX_SOURCE_ALWAYS0 + channel;
  408. #else
  409. // search for an unused "always on" source
  410. unsigned int i = DMAMUX_SOURCE_ALWAYS0;
  411. for (i = DMAMUX_SOURCE_ALWAYS0;
  412. i < DMAMUX_SOURCE_ALWAYS0 + DMAMUX_NUM_SOURCE_ALWAYS; i++) {
  413. unsigned int ch;
  414. for (ch=0; ch < DMA_NUM_CHANNELS; ch++) {
  415. if (mux[ch] == i) break;
  416. }
  417. if (ch >= DMA_NUM_CHANNELS) {
  418. mux[channel] = (i | DMAMUX_ENABLE);
  419. return;
  420. }
  421. }
  422. #endif
  423. }
  424. // Manually trigger the DMA channel.
  425. void triggerManual(void) {
  426. DMA_SSRT = channel;
  427. }
  428. /***************************************/
  429. /** Interrupts **/
  430. /***************************************/
  431. // An interrupt routine can be run when the DMA channel completes
  432. // the entire transfer, and also optionally when half of the
  433. // transfer is completed.
  434. void attachInterrupt(void (*isr)(void)) {
  435. _VectorsRam[channel + IRQ_DMA_CH0 + 16] = isr;
  436. NVIC_ENABLE_IRQ(IRQ_DMA_CH0 + channel);
  437. }
  438. void detachInterrupt(void) {
  439. NVIC_DISABLE_IRQ(IRQ_DMA_CH0 + channel);
  440. }
  441. void clearInterrupt(void) {
  442. DMA_CINT = channel;
  443. }
  444. /***************************************/
  445. /** Enable / Disable **/
  446. /***************************************/
  447. void enable(void) {
  448. DMA_SERQ = channel;
  449. }
  450. void disable(void) {
  451. DMA_CERQ = channel;
  452. }
  453. /***************************************/
  454. /** Status **/
  455. /***************************************/
  456. bool complete(void) {
  457. if (TCD->CSR & DMA_TCD_CSR_DONE) return true;
  458. return false;
  459. }
  460. void clearComplete(void) {
  461. DMA_CDNE = channel;
  462. }
  463. bool error(void) {
  464. if (DMA_ERR & (1<<channel)) return true;
  465. return false;
  466. }
  467. void clearError(void) {
  468. DMA_CERR = channel;
  469. }
  470. void * sourceAddress(void) {
  471. return (void *)(TCD->SADDR);
  472. }
  473. void * destinationAddress(void) {
  474. return (void *)(TCD->DADDR);
  475. }
  476. /***************************************/
  477. /** Direct Hardware Access **/
  478. /***************************************/
  479. // For complex and unusual configurations not possible with the above
  480. // functions, the Transfer Control Descriptor (TCD) and channel number
  481. // can be used directly. This leads to less portable and less readable
  482. // code, but direct control of all parameters is possible.
  483. uint8_t channel;
  484. // TCD is accessible due to inheritance from DMABaseClass
  485. /* usage cases:
  486. ************************
  487. OctoWS2811:
  488. ************************
  489. // enable clocks to the DMA controller and DMAMUX
  490. SIM_SCGC7 |= SIM_SCGC7_DMA;
  491. SIM_SCGC6 |= SIM_SCGC6_DMAMUX;
  492. DMA_CR = 0;
  493. DMA_CERQ = 1;
  494. DMA_CERQ = 2;
  495. DMA_CERQ = 3;
  496. // DMA channel #1 sets WS2811 high at the beginning of each cycle
  497. DMA_TCD1_SADDR = &ones;
  498. DMA_TCD1_SOFF = 0;
  499. DMA_TCD1_ATTR = DMA_TCD_ATTR_SSIZE(0) | DMA_TCD_ATTR_DSIZE(0);
  500. DMA_TCD1_NBYTES_MLNO = 1;
  501. DMA_TCD1_SLAST = 0;
  502. DMA_TCD1_DADDR = &GPIOD_PSOR;
  503. DMA_TCD1_DOFF = 0;
  504. DMA_TCD1_CITER_ELINKNO = bufsize;
  505. DMA_TCD1_DLASTSGA = 0;
  506. DMA_TCD1_CSR = DMA_TCD_CSR_DREQ;
  507. DMA_TCD1_BITER_ELINKNO = bufsize;
  508. dma1.source(ones);
  509. dma1.destination(GPIOD_PSOR);
  510. dma1.size(1);
  511. dma1.count(bufsize);
  512. dma1.disableOnCompletion();
  513. // DMA channel #2 writes the pixel data at 20% of the cycle
  514. DMA_TCD2_SADDR = frameBuffer;
  515. DMA_TCD2_SOFF = 1;
  516. DMA_TCD2_ATTR = DMA_TCD_ATTR_SSIZE(0) | DMA_TCD_ATTR_DSIZE(0);
  517. DMA_TCD2_NBYTES_MLNO = 1;
  518. DMA_TCD2_SLAST = -bufsize;
  519. DMA_TCD2_DADDR = &GPIOD_PDOR;
  520. DMA_TCD2_DOFF = 0;
  521. DMA_TCD2_CITER_ELINKNO = bufsize;
  522. DMA_TCD2_DLASTSGA = 0;
  523. DMA_TCD2_CSR = DMA_TCD_CSR_DREQ;
  524. DMA_TCD2_BITER_ELINKNO = bufsize;
  525. dma2.source(frameBuffer, sizeof(frameBuffer));
  526. dma2.destination(GPIOD_PDOR);
  527. dma2.size(1);
  528. dma2.count(bufsize);
  529. dma2.disableOnCompletion();
  530. // DMA channel #3 clear all the pins low at 48% of the cycle
  531. DMA_TCD3_SADDR = &ones;
  532. DMA_TCD3_SOFF = 0;
  533. DMA_TCD3_ATTR = DMA_TCD_ATTR_SSIZE(0) | DMA_TCD_ATTR_DSIZE(0);
  534. DMA_TCD3_NBYTES_MLNO = 1;
  535. DMA_TCD3_SLAST = 0;
  536. DMA_TCD3_DADDR = &GPIOD_PCOR;
  537. DMA_TCD3_DOFF = 0;
  538. DMA_TCD3_CITER_ELINKNO = bufsize;
  539. DMA_TCD3_DLASTSGA = 0;
  540. DMA_TCD3_CSR = DMA_TCD_CSR_DREQ | DMA_TCD_CSR_INTMAJOR;
  541. DMA_TCD3_BITER_ELINKNO = bufsize;
  542. dma3.source(ones);
  543. dma3.destination(GPIOD_PCOR);
  544. dma3.size(1);
  545. dma3.count(bufsize);
  546. dma3.disableOnCompletion();
  547. ************************
  548. Audio, DAC
  549. ************************
  550. DMA_CR = 0;
  551. DMA_TCD4_SADDR = dac_buffer;
  552. DMA_TCD4_SOFF = 2;
  553. DMA_TCD4_ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
  554. DMA_TCD4_NBYTES_MLNO = 2;
  555. DMA_TCD4_SLAST = -sizeof(dac_buffer);
  556. DMA_TCD4_DADDR = &DAC0_DAT0L;
  557. DMA_TCD4_DOFF = 0;
  558. DMA_TCD4_CITER_ELINKNO = sizeof(dac_buffer) / 2;
  559. DMA_TCD4_DLASTSGA = 0;
  560. DMA_TCD4_BITER_ELINKNO = sizeof(dac_buffer) / 2;
  561. DMA_TCD4_CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
  562. DMAMUX0_CHCFG4 = DMAMUX_DISABLE;
  563. DMAMUX0_CHCFG4 = DMAMUX_SOURCE_PDB | DMAMUX_ENABLE;
  564. ************************
  565. Audio, I2S
  566. ************************
  567. DMA_CR = 0;
  568. DMA_TCD0_SADDR = i2s_tx_buffer;
  569. DMA_TCD0_SOFF = 2;
  570. DMA_TCD0_ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
  571. DMA_TCD0_NBYTES_MLNO = 2;
  572. DMA_TCD0_SLAST = -sizeof(i2s_tx_buffer);
  573. DMA_TCD0_DADDR = &I2S0_TDR0;
  574. DMA_TCD0_DOFF = 0;
  575. DMA_TCD0_CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
  576. DMA_TCD0_DLASTSGA = 0;
  577. DMA_TCD0_BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
  578. DMA_TCD0_CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
  579. DMAMUX0_CHCFG0 = DMAMUX_DISABLE;
  580. DMAMUX0_CHCFG0 = DMAMUX_SOURCE_I2S0_TX | DMAMUX_ENABLE;
  581. ************************
  582. ADC lib, Pedro Villanueva
  583. ************************
  584. DMA_CR = 0; // normal mode of operation
  585. *DMAMUX0_CHCFG = DMAMUX_DISABLE; // disable before changing
  586. *DMA_TCD_ATTR = DMA_TCD_ATTR_SSIZE(DMA_TCD_ATTR_SIZE_16BIT) |
  587. DMA_TCD_ATTR_DSIZE(DMA_TCD_ATTR_SIZE_16BIT) |
  588. DMA_TCD_ATTR_DMOD(4); // src and dst data is 16 bit (2 bytes), buffer size 2^^4 bytes = 8 values
  589. *DMA_TCD_NBYTES_MLNO = 2; // Minor Byte Transfer Count 2 bytes = 16 bits (we transfer 2 bytes each minor loop)
  590. *DMA_TCD_SADDR = ADC_RA; // source address
  591. *DMA_TCD_SOFF = 0; // don't change the address when minor loop finishes
  592. *DMA_TCD_SLAST = 0; // don't change src address after major loop completes
  593. *DMA_TCD_DADDR = elems; // destination address
  594. *DMA_TCD_DOFF = 2; // increment 2 bytes each minor loop
  595. *DMA_TCD_DLASTSGA = 0; // modulus feature takes care of going back to first element
  596. *DMA_TCD_CITER_ELINKNO = 1; // Current Major Iteration Count with channel linking disabled
  597. *DMA_TCD_BITER_ELINKNO = 1; // Starting Major Iteration Count with channel linking disabled
  598. *DMA_TCD_CSR = DMA_TCD_CSR_INTMAJOR; // Control and status: interrupt when major counter is complete
  599. DMA_CERQ = DMA_CERQ_CERQ(DMA_channel); // clear all past request
  600. DMA_CINT = DMA_channel; // clear interrupts
  601. uint8_t DMAMUX_SOURCE_ADC = DMAMUX_SOURCE_ADC0;
  602. if(ADC_number==1){
  603. DMAMUX_SOURCE_ADC = DMAMUX_SOURCE_ADC1;
  604. }
  605. *DMAMUX0_CHCFG = DMAMUX_SOURCE_ADC | DMAMUX_ENABLE; // enable mux and set channel DMA_channel to ADC0
  606. DMA_SERQ = DMA_SERQ_SERQ(DMA_channel); // enable DMA request
  607. NVIC_ENABLE_IRQ(IRQ_DMA_CH); // enable interrupts
  608. ************************
  609. SmartMatrix
  610. ************************
  611. // enable minor loop mapping so addresses can get reset after minor loops
  612. DMA_CR = 1 << 7;
  613. // DMA channel #0 - on latch rising edge, read address from fixed address temporary buffer, and output address on GPIO
  614. // using combo of writes to set+clear registers, to only modify the address pins and not other GPIO pins
  615. // address temporary buffer is refreshed before each DMA trigger (by DMA channel #2)
  616. // only use single major loop, never disable channel
  617. #define ADDRESS_ARRAY_REGISTERS_TO_UPDATE 2
  618. DMA_TCD0_SADDR = &gpiosync.gpio_pcor;
  619. DMA_TCD0_SOFF = (int)&gpiosync.gpio_psor - (int)&gpiosync.gpio_pcor;
  620. DMA_TCD0_SLAST = (ADDRESS_ARRAY_REGISTERS_TO_UPDATE * ((int)&ADDX_GPIO_CLEAR_REGISTER - (int)&ADDX_GPIO_SET_REGISTER));
  621. DMA_TCD0_ATTR = DMA_TCD_ATTR_SSIZE(2) | DMA_TCD_ATTR_DSIZE(2);
  622. // Destination Minor Loop Offset Enabled - transfer appropriate number of bytes per minor loop, and put DADDR back to original value when minor loop is complete
  623. // Source Minor Loop Offset Enabled - source buffer is same size and offset as destination so values reset after each minor loop
  624. DMA_TCD0_NBYTES_MLOFFYES = DMA_TCD_NBYTES_SMLOE | DMA_TCD_NBYTES_DMLOE |
  625. ((ADDRESS_ARRAY_REGISTERS_TO_UPDATE * ((int)&ADDX_GPIO_CLEAR_REGISTER - (int)&ADDX_GPIO_SET_REGISTER)) << 10) |
  626. (ADDRESS_ARRAY_REGISTERS_TO_UPDATE * sizeof(gpiosync.gpio_psor));
  627. // start on higher value of two registers, and make offset decrement to avoid negative number in NBYTES_MLOFFYES (TODO: can switch order by masking negative offset)
  628. DMA_TCD0_DADDR = &ADDX_GPIO_CLEAR_REGISTER;
  629. // update destination address so the second update per minor loop is ADDX_GPIO_SET_REGISTER
  630. DMA_TCD0_DOFF = (int)&ADDX_GPIO_SET_REGISTER - (int)&ADDX_GPIO_CLEAR_REGISTER;
  631. DMA_TCD0_DLASTSGA = (ADDRESS_ARRAY_REGISTERS_TO_UPDATE * ((int)&ADDX_GPIO_CLEAR_REGISTER - (int)&ADDX_GPIO_SET_REGISTER));
  632. // single major loop
  633. DMA_TCD0_CITER_ELINKNO = 1;
  634. DMA_TCD0_BITER_ELINKNO = 1;
  635. // link channel 1, enable major channel-to-channel linking, don't clear enable on major loop complete
  636. DMA_TCD0_CSR = (1 << 8) | (1 << 5);
  637. DMAMUX0_CHCFG0 = DMAMUX_SOURCE_LATCH_RISING_EDGE | DMAMUX_ENABLE;
  638. // DMA channel #1 - copy address values from current position in array to buffer to temporarily hold row values for the next timer cycle
  639. // only use single major loop, never disable channel
  640. DMA_TCD1_SADDR = &matrixUpdateBlocks[0][0].addressValues;
  641. DMA_TCD1_SOFF = sizeof(uint16_t);
  642. DMA_TCD1_SLAST = sizeof(matrixUpdateBlock) - (ADDRESS_ARRAY_REGISTERS_TO_UPDATE * sizeof(uint16_t));
  643. DMA_TCD1_ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
  644. // 16-bit = 2 bytes transferred
  645. // transfer two 16-bit values, reset destination address back after each minor loop
  646. DMA_TCD1_NBYTES_MLOFFNO = (ADDRESS_ARRAY_REGISTERS_TO_UPDATE * sizeof(uint16_t));
  647. // start with the register that's the highest location in memory and make offset decrement to avoid negative number in NBYTES_MLOFFYES register (TODO: can switch order by masking negative offset)
  648. DMA_TCD1_DADDR = &gpiosync.gpio_pcor;
  649. DMA_TCD1_DOFF = (int)&gpiosync.gpio_psor - (int)&gpiosync.gpio_pcor;
  650. DMA_TCD1_DLASTSGA = (ADDRESS_ARRAY_REGISTERS_TO_UPDATE * ((int)&gpiosync.gpio_pcor - (int)&gpiosync.gpio_psor));
  651. // no minor loop linking, single major loop, single minor loop, don't clear enable after major loop complete
  652. DMA_TCD1_CITER_ELINKNO = 1;
  653. DMA_TCD1_BITER_ELINKNO = 1;
  654. DMA_TCD1_CSR = 0;
  655. // DMA channel #2 - on latch falling edge, load FTM1_CV1 and FTM1_MOD with with next values from current block
  656. // only use single major loop, never disable channel
  657. // link to channel 3 when complete
  658. #define TIMER_REGISTERS_TO_UPDATE 2
  659. DMA_TCD2_SADDR = &matrixUpdateBlocks[0][0].timerValues.timer_oe;
  660. DMA_TCD2_SOFF = sizeof(uint16_t);
  661. DMA_TCD2_SLAST = sizeof(matrixUpdateBlock) - (TIMER_REGISTERS_TO_UPDATE * sizeof(uint16_t));
  662. DMA_TCD2_ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
  663. // 16-bit = 2 bytes transferred
  664. DMA_TCD2_NBYTES_MLOFFNO = TIMER_REGISTERS_TO_UPDATE * sizeof(uint16_t);
  665. DMA_TCD2_DADDR = &FTM1_C1V;
  666. DMA_TCD2_DOFF = (int)&FTM1_MOD - (int)&FTM1_C1V;
  667. DMA_TCD2_DLASTSGA = TIMER_REGISTERS_TO_UPDATE * ((int)&FTM1_C1V - (int)&FTM1_MOD);
  668. // no minor loop linking, single major loop
  669. DMA_TCD2_CITER_ELINKNO = 1;
  670. DMA_TCD2_BITER_ELINKNO = 1;
  671. // link channel 3, enable major channel-to-channel linking, don't clear enable after major loop complete
  672. DMA_TCD2_CSR = (3 << 8) | (1 << 5);
  673. DMAMUX0_CHCFG2 = DMAMUX_SOURCE_LATCH_FALLING_EDGE | DMAMUX_ENABLE;
  674. #define DMA_TCD_MLOFF_MASK (0x3FFFFC00)
  675. // DMA channel #3 - repeatedly load gpio_array into GPIOD_PDOR, stop and int on major loop complete
  676. DMA_TCD3_SADDR = matrixUpdateData[0][0];
  677. DMA_TCD3_SOFF = sizeof(matrixUpdateData[0][0]) / 2;
  678. // SADDR will get updated by ISR, no need to set SLAST
  679. DMA_TCD3_SLAST = 0;
  680. DMA_TCD3_ATTR = DMA_TCD_ATTR_SSIZE(0) | DMA_TCD_ATTR_DSIZE(0);
  681. // after each minor loop, set source to point back to the beginning of this set of data,
  682. // but advance by 1 byte to get the next significant bits data
  683. DMA_TCD3_NBYTES_MLOFFYES = DMA_TCD_NBYTES_SMLOE |
  684. (((1 - sizeof(matrixUpdateData[0])) << 10) & DMA_TCD_MLOFF_MASK) |
  685. (MATRIX_WIDTH * DMA_UPDATES_PER_CLOCK);
  686. DMA_TCD3_DADDR = &GPIOD_PDOR;
  687. DMA_TCD3_DOFF = 0;
  688. DMA_TCD3_DLASTSGA = 0;
  689. DMA_TCD3_CITER_ELINKNO = LATCHES_PER_ROW;
  690. DMA_TCD3_BITER_ELINKNO = LATCHES_PER_ROW;
  691. // int after major loop is complete
  692. DMA_TCD3_CSR = DMA_TCD_CSR_INTMAJOR;
  693. // for debugging - enable bandwidth control (space out GPIO updates so they can be seen easier on a low-bandwidth logic analyzer)
  694. //DMA_TCD3_CSR |= (0x02 << 14);
  695. // enable a done interrupt when all DMA operations are complete
  696. NVIC_ENABLE_IRQ(IRQ_DMA_CH3);
  697. // enable additional dma interrupt used as software interrupt
  698. NVIC_SET_PRIORITY(IRQ_DMA_CH1, 0xFF); // 0xFF = lowest priority
  699. NVIC_ENABLE_IRQ(IRQ_DMA_CH1);
  700. // enable channels 0, 1, 2, 3
  701. DMA_ERQ = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3);
  702. // at the end after everything is set up: enable timer from system clock, with appropriate prescale
  703. FTM1_SC = FTM_SC_CLKS(1) | FTM_SC_PS(LATCH_TIMER_PRESCALE);
  704. */
  705. };
  706. // arrange the relative priority of 2 or more DMA channels
  707. void DMAPriorityOrder(DMAChannel &ch1, DMAChannel &ch2);
  708. void DMAPriorityOrder(DMAChannel &ch1, DMAChannel &ch2, DMAChannel &ch3);
  709. void DMAPriorityOrder(DMAChannel &ch1, DMAChannel &ch2, DMAChannel &ch3, DMAChannel &ch4);
  710. extern "C" {
  711. #endif
  712. extern uint16_t dma_channel_allocated_mask;
  713. #ifdef __cplusplus
  714. }
  715. #endif
  716. #endif