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Teensy 4.1 core updated for C++20
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teensy-core-4.1/teensy4/startup.c

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  1. #include "imxrt.h"

  2. #include "wiring.h"

  3. #include "usb_dev.h"

  4. #include "avr/pgmspace.h"

  5. 

  6. #include "debug/printf.h"

  7. 

  8. // from the linker

  9. extern unsigned long _stextload;

  10. extern unsigned long _stext;

  11. extern unsigned long _etext;

  12. extern unsigned long _sdataload;

  13. extern unsigned long _sdata;

  14. extern unsigned long _edata;

  15. extern unsigned long _sbss;

  16. extern unsigned long _ebss;

  17. extern unsigned long _flexram_bank_config;

  18. extern unsigned long _estack;

  19. 

  20. __attribute__ ((used, aligned(1024)))

  21. void (* _VectorsRam[NVIC_NUM_INTERRUPTS+16])(void);

  22. 

  23. static void memory_copy(uint32_t *dest, const uint32_t *src, uint32_t *dest_end);

  24. static void memory_clear(uint32_t *dest, uint32_t *dest_end);

  25. static void configure_systick(void);

  26. static void reset_PFD();

  27. extern void systick_isr(void);

  28. extern void pendablesrvreq_isr(void);

  29. void configure_cache(void);

  30. void configure_external_ram(void);

  31. void unused_interrupt_vector(void);

  32. void usb_pll_start();

  33. extern void analog_init(void); // analog.c

  34. extern void pwm_init(void); // pwm.c

  35. extern void tempmon_init(void);  //tempmon.c

  36. uint32_t set_arm_clock(uint32_t frequency); // clockspeed.c

  37. extern void __libc_init_array(void); // C++ standard library

  38. 

  39. uint8_t external_psram_size = 0;

  40. 

  41. extern int main (void);

  42. void startup_default_early_hook(void) {}

  43. void startup_early_hook(void)		__attribute__ ((weak, alias("startup_default_early_hook")));

  44. void startup_default_late_hook(void) {}

  45. void startup_late_hook(void)		__attribute__ ((weak, alias("startup_default_late_hook")));

  46. __attribute__((section(".startup"), optimize("no-tree-loop-distribute-patterns")))

  47. void ResetHandler(void)

  48. {

  49. 	unsigned int i;

  50. 

  51. #if defined(__IMXRT1062__)

  52. 	IOMUXC_GPR_GPR17 = (uint32_t)&_flexram_bank_config;

  53. 	IOMUXC_GPR_GPR16 = 0x00200007;

  54. 	IOMUXC_GPR_GPR14 = 0x00AA0000;

  55. 	__asm__ volatile("mov sp, %0" : : "r" ((uint32_t)&_estack) : );

  56. #endif

  57. 	PMU_MISC0_SET = 1<<3; //Use bandgap-based bias currents for best performance (Page 1175)

  58. 	// pin 13 - if startup crashes, use this to turn on the LED early for troubleshooting

  59. 	//IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 5;

  60. 	//IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = IOMUXC_PAD_DSE(7);

  61. 	//IOMUXC_GPR_GPR27 = 0xFFFFFFFF;

  62. 	//GPIO7_GDIR |= (1<<3);

  63. 	//GPIO7_DR_SET = (1<<3); // digitalWrite(13, HIGH);

  64. 

  65. 	// Initialize memory

  66. 	memory_copy(&_stext, &_stextload, &_etext);

  67. 	memory_copy(&_sdata, &_sdataload, &_edata);

  68. 	memory_clear(&_sbss, &_ebss);

  69. 

  70. 	// enable FPU

  71. 	SCB_CPACR = 0x00F00000;

  72. 

  73. 	// set up blank interrupt & exception vector table

  74. 	for (i=0; i < NVIC_NUM_INTERRUPTS + 16; i++) _VectorsRam[i] = &unused_interrupt_vector;

  75. 	for (i=0; i < NVIC_NUM_INTERRUPTS; i++) NVIC_SET_PRIORITY(i, 128);

  76. 	SCB_VTOR = (uint32_t)_VectorsRam;

  77. 

  78. 	reset_PFD();

  79. 	

  80. 	// Configure clocks

  81. 	// TODO: make sure all affected peripherals are turned off!

  82. 	// PIT & GPT timers to run from 24 MHz clock (independent of CPU speed)

  83. 	CCM_CSCMR1 = (CCM_CSCMR1 & ~CCM_CSCMR1_PERCLK_PODF(0x3F)) | CCM_CSCMR1_PERCLK_CLK_SEL;

  84. 	// UARTs run from 24 MHz clock (works if PLL3 off or bypassed)

  85. 	CCM_CSCDR1 = (CCM_CSCDR1 & ~CCM_CSCDR1_UART_CLK_PODF(0x3F)) | CCM_CSCDR1_UART_CLK_SEL;

  86. 

  87. #if defined(__IMXRT1062__)

  88. 	// Use fast GPIO6, GPIO7, GPIO8, GPIO9

  89. 	IOMUXC_GPR_GPR26 = 0xFFFFFFFF;

  90. 	IOMUXC_GPR_GPR27 = 0xFFFFFFFF;

  91. 	IOMUXC_GPR_GPR28 = 0xFFFFFFFF;

  92. 	IOMUXC_GPR_GPR29 = 0xFFFFFFFF;

  93. #endif

  94. 

  95. 	// must enable PRINT_DEBUG_STUFF in debug/print.h

  96. 	printf_debug_init();

  97. 	printf("\n***********IMXRT Startup**********\n");

  98. 	printf("test %d %d %d\n", 1, -1234567, 3);

  99. 

  100. 	configure_cache();

  101. 	configure_systick();

  102. 	usb_pll_start();	

  103. 	reset_PFD(); //TODO: is this really needed?

  104. #ifdef F_CPU

  105. 	set_arm_clock(F_CPU);

  106. #endif

  107. 

  108. 	// Undo PIT timer usage by ROM startup

  109. 	CCM_CCGR1 |= CCM_CCGR1_PIT(CCM_CCGR_ON);

  110. 	PIT_MCR = 0;

  111. 	PIT_TCTRL0 = 0;

  112. 	PIT_TCTRL1 = 0;

  113. 	PIT_TCTRL2 = 0;

  114. 	PIT_TCTRL3 = 0;

  115. 

  116. 	// initialize RTC

  117. 	if (!(SNVS_LPCR & SNVS_LPCR_SRTC_ENV)) {

  118. 		// if SRTC isn't running, start it with default Jan 1, 2019

  119. 		SNVS_LPSRTCLR = 1546300800u << 15;

  120. 		SNVS_LPSRTCMR = 1546300800u >> 17;

  121. 		SNVS_LPCR |= SNVS_LPCR_SRTC_ENV;

  122. 	}

  123. 	SNVS_HPCR |= SNVS_HPCR_RTC_EN | SNVS_HPCR_HP_TS;

  124. 

  125. #ifdef ARDUINO_TEENSY41

  126. 	configure_external_ram();

  127. #endif

  128. 	startup_early_hook();

  129. 	while (millis() < 20) ; // wait at least 20ms before starting USB

  130. 	usb_init();

  131. 	analog_init();

  132. 	pwm_init();

  133. 	tempmon_init();

  134. 

  135. 	startup_late_hook();

  136. 	while (millis() < 300) ; // wait at least 300ms before calling user code

  137. 	//printf("before C++ constructors\n");

  138. 	__libc_init_array();

  139. 	//printf("after C++ constructors\n");

  140. 	//printf("before setup\n");

  141. 	main();

  142. 	

  143. 	while (1) ;

  144. }

  145. 

  146. 

  147. 

  148. 

  149. // ARM SysTick is used for most Ardiuno timing functions, delay(), millis(),

  150. // micros().  SysTick can run from either the ARM core clock, or from an

  151. // "external" clock.  NXP documents it as "24 MHz XTALOSC can be the external

  152. // clock source of SYSTICK" (RT1052 ref manual, rev 1, page 411).  However,

  153. // NXP actually hid an undocumented divide-by-240 circuit in the hardware, so

  154. // the external clock is really 100 kHz.  We use this clock rather than the

  155. // ARM clock, to allow SysTick to maintain correct timing even when we change

  156. // the ARM clock to run at different speeds.

  157. #define SYSTICK_EXT_FREQ 100000

  158. 

  159. extern volatile uint32_t systick_cycle_count;

  160. static void configure_systick(void)

  161. {

  162. 	_VectorsRam[14] = pendablesrvreq_isr;

  163. 	_VectorsRam[15] = systick_isr;

  164. 	SYST_RVR = (SYSTICK_EXT_FREQ / 1000) - 1;

  165. 	SYST_CVR = 0;

  166. 	SYST_CSR = SYST_CSR_TICKINT | SYST_CSR_ENABLE;

  167. 	SCB_SHPR3 = 0x20200000;  // Systick, pendablesrvreq_isr = priority 32;

  168. 	ARM_DEMCR |= ARM_DEMCR_TRCENA;

  169. 	ARM_DWT_CTRL |= ARM_DWT_CTRL_CYCCNTENA; // turn on cycle counter

  170. 	systick_cycle_count = ARM_DWT_CYCCNT; // compiled 0, corrected w/1st systick

  171. }

  172. 

  173. 

  174. // concise defines for SCB_MPU_RASR and SCB_MPU_RBAR, ARM DDI0403E, pg 696

  175. #define NOEXEC		SCB_MPU_RASR_XN

  176. #define READONLY	SCB_MPU_RASR_AP(7)

  177. #define READWRITE	SCB_MPU_RASR_AP(3)

  178. #define NOACCESS	SCB_MPU_RASR_AP(0)

  179. #define MEM_CACHE_WT	SCB_MPU_RASR_TEX(0) | SCB_MPU_RASR_C

  180. #define MEM_CACHE_WB	SCB_MPU_RASR_TEX(0) | SCB_MPU_RASR_C | SCB_MPU_RASR_B

  181. #define MEM_CACHE_WBWA	SCB_MPU_RASR_TEX(1) | SCB_MPU_RASR_C | SCB_MPU_RASR_B

  182. #define MEM_NOCACHE	SCB_MPU_RASR_TEX(1)

  183. #define DEV_NOCACHE	SCB_MPU_RASR_TEX(2)

  184. #define SIZE_32B	(SCB_MPU_RASR_SIZE(4) | SCB_MPU_RASR_ENABLE)

  185. #define SIZE_64B	(SCB_MPU_RASR_SIZE(5) | SCB_MPU_RASR_ENABLE)

  186. #define SIZE_128B	(SCB_MPU_RASR_SIZE(6) | SCB_MPU_RASR_ENABLE)

  187. #define SIZE_256B	(SCB_MPU_RASR_SIZE(7) | SCB_MPU_RASR_ENABLE)

  188. #define SIZE_512B	(SCB_MPU_RASR_SIZE(8) | SCB_MPU_RASR_ENABLE)

  189. #define SIZE_1K		(SCB_MPU_RASR_SIZE(9) | SCB_MPU_RASR_ENABLE)

  190. #define SIZE_2K		(SCB_MPU_RASR_SIZE(10) | SCB_MPU_RASR_ENABLE)

  191. #define SIZE_4K		(SCB_MPU_RASR_SIZE(11) | SCB_MPU_RASR_ENABLE)

  192. #define SIZE_8K		(SCB_MPU_RASR_SIZE(12) | SCB_MPU_RASR_ENABLE)

  193. #define SIZE_16K	(SCB_MPU_RASR_SIZE(13) | SCB_MPU_RASR_ENABLE)

  194. #define SIZE_32K	(SCB_MPU_RASR_SIZE(14) | SCB_MPU_RASR_ENABLE)

  195. #define SIZE_64K	(SCB_MPU_RASR_SIZE(15) | SCB_MPU_RASR_ENABLE)

  196. #define SIZE_128K	(SCB_MPU_RASR_SIZE(16) | SCB_MPU_RASR_ENABLE)

  197. #define SIZE_256K	(SCB_MPU_RASR_SIZE(17) | SCB_MPU_RASR_ENABLE)

  198. #define SIZE_512K	(SCB_MPU_RASR_SIZE(18) | SCB_MPU_RASR_ENABLE)

  199. #define SIZE_1M		(SCB_MPU_RASR_SIZE(19) | SCB_MPU_RASR_ENABLE)

  200. #define SIZE_2M		(SCB_MPU_RASR_SIZE(20) | SCB_MPU_RASR_ENABLE)

  201. #define SIZE_4M		(SCB_MPU_RASR_SIZE(21) | SCB_MPU_RASR_ENABLE)

  202. #define SIZE_8M		(SCB_MPU_RASR_SIZE(22) | SCB_MPU_RASR_ENABLE)

  203. #define SIZE_16M	(SCB_MPU_RASR_SIZE(23) | SCB_MPU_RASR_ENABLE)

  204. #define SIZE_32M	(SCB_MPU_RASR_SIZE(24) | SCB_MPU_RASR_ENABLE)

  205. #define SIZE_64M	(SCB_MPU_RASR_SIZE(25) | SCB_MPU_RASR_ENABLE)

  206. #define SIZE_128M	(SCB_MPU_RASR_SIZE(26) | SCB_MPU_RASR_ENABLE)

  207. #define SIZE_256M	(SCB_MPU_RASR_SIZE(27) | SCB_MPU_RASR_ENABLE)

  208. #define SIZE_512M	(SCB_MPU_RASR_SIZE(28) | SCB_MPU_RASR_ENABLE)

  209. #define SIZE_1G		(SCB_MPU_RASR_SIZE(29) | SCB_MPU_RASR_ENABLE)

  210. #define SIZE_2G		(SCB_MPU_RASR_SIZE(30) | SCB_MPU_RASR_ENABLE)

  211. #define SIZE_4G		(SCB_MPU_RASR_SIZE(31) | SCB_MPU_RASR_ENABLE)

  212. #define REGION(n)	(SCB_MPU_RBAR_REGION(n) | SCB_MPU_RBAR_VALID)

  213. 

  214. FLASHMEM void configure_cache(void)

  215. {

  216. 	//printf("MPU_TYPE = %08lX\n", SCB_MPU_TYPE);

  217. 	//printf("CCR = %08lX\n", SCB_CCR);

  218. 

  219. 	// TODO: check if caches already active - skip?

  220. 

  221. 	SCB_MPU_CTRL = 0; // turn off MPU

  222. 

  223. 	uint32_t i = 0;

  224. 	SCB_MPU_RBAR = 0x00000000 | REGION(i++); //https://developer.arm.com/docs/146793866/10/why-does-the-cortex-m7-initiate-axim-read-accesses-to-memory-addresses-that-do-not-fall-under-a-defined-mpu-region

  225. 	SCB_MPU_RASR = SCB_MPU_RASR_TEX(0) | NOACCESS | NOEXEC | SIZE_4G;

  226. 	

  227. 	SCB_MPU_RBAR = 0x00000000 | REGION(i++); // ITCM

  228. 	SCB_MPU_RASR = MEM_NOCACHE | READWRITE | SIZE_512K;

  229. 

  230. 	// TODO: trap regions should be created last, because the hardware gives

  231. 	//  priority to the higher number ones.

  232. 	SCB_MPU_RBAR = 0x00000000 | REGION(i++); // trap NULL pointer deref

  233. 	SCB_MPU_RASR =  DEV_NOCACHE | NOACCESS | SIZE_32B;

  234. 

  235. 	SCB_MPU_RBAR = 0x00200000 | REGION(i++); // Boot ROM

  236. 	SCB_MPU_RASR = MEM_CACHE_WT | READONLY | SIZE_128K;

  237. 

  238. 	SCB_MPU_RBAR = 0x20000000 | REGION(i++); // DTCM

  239. 	SCB_MPU_RASR = MEM_NOCACHE | READWRITE | NOEXEC | SIZE_512K;

  240. 	

  241. 	SCB_MPU_RBAR = ((uint32_t)&_ebss) | REGION(i++); // trap stack overflow

  242. 	SCB_MPU_RASR = SCB_MPU_RASR_TEX(0) | NOACCESS | NOEXEC | SIZE_32B;

  243. 

  244. 	SCB_MPU_RBAR = 0x20200000 | REGION(i++); // RAM (AXI bus)

  245. 	SCB_MPU_RASR = MEM_CACHE_WBWA | READWRITE | NOEXEC | SIZE_1M;

  246. 

  247. 	SCB_MPU_RBAR = 0x40000000 | REGION(i++); // Peripherals

  248. 	SCB_MPU_RASR = DEV_NOCACHE | READWRITE | NOEXEC | SIZE_64M;

  249. 

  250. 	SCB_MPU_RBAR = 0x60000000 | REGION(i++); // QSPI Flash

  251. 	SCB_MPU_RASR = MEM_CACHE_WBWA | READONLY | SIZE_16M;

  252. 

  253. 	SCB_MPU_RBAR = 0x70000000 | REGION(i++); // FlexSPI2

  254. 	SCB_MPU_RASR = MEM_CACHE_WBWA | READONLY | NOEXEC | SIZE_256M;

  255. 

  256. 	SCB_MPU_RBAR = 0x70000000 | REGION(i++); // FlexSPI2

  257. 	SCB_MPU_RASR = MEM_CACHE_WBWA | READWRITE | NOEXEC | SIZE_16M;

  258. 

  259. 	// TODO: protect access to power supply config

  260. 

  261. 	SCB_MPU_CTRL = SCB_MPU_CTRL_ENABLE;

  262. 

  263. 	// cache enable, ARM DDI0403E, pg 628

  264. 	asm("dsb");

  265. 	asm("isb");

  266. 	SCB_CACHE_ICIALLU = 0;

  267. 

  268. 	asm("dsb");

  269. 	asm("isb");

  270. 	SCB_CCR |= (SCB_CCR_IC | SCB_CCR_DC);

  271. }

  272. 

  273. #ifdef ARDUINO_TEENSY41

  274. 

  275. #define LUT0(opcode, pads, operand) (FLEXSPI_LUT_INSTRUCTION((opcode), (pads), (operand)))

  276. #define LUT1(opcode, pads, operand) (FLEXSPI_LUT_INSTRUCTION((opcode), (pads), (operand)) << 16)

  277. #define CMD_SDR         FLEXSPI_LUT_OPCODE_CMD_SDR

  278. #define ADDR_SDR        FLEXSPI_LUT_OPCODE_RADDR_SDR

  279. #define READ_SDR        FLEXSPI_LUT_OPCODE_READ_SDR

  280. #define WRITE_SDR       FLEXSPI_LUT_OPCODE_WRITE_SDR

  281. #define DUMMY_SDR       FLEXSPI_LUT_OPCODE_DUMMY_SDR

  282. #define PINS1           FLEXSPI_LUT_NUM_PADS_1

  283. #define PINS4           FLEXSPI_LUT_NUM_PADS_4

  284. 

  285. FLASHMEM static void flexspi2_command(uint32_t index, uint32_t addr)

  286. {

  287. 	FLEXSPI2_IPCR0 = addr;

  288. 	FLEXSPI2_IPCR1 = FLEXSPI_IPCR1_ISEQID(index);

  289. 	FLEXSPI2_IPCMD = FLEXSPI_IPCMD_TRG;

  290. 	while (!(FLEXSPI2_INTR & FLEXSPI_INTR_IPCMDDONE)); // wait

  291. 	FLEXSPI2_INTR = FLEXSPI_INTR_IPCMDDONE;

  292. }

  293. 

  294. FLASHMEM static uint32_t flexspi2_psram_id(uint32_t addr)

  295. {

  296. 	FLEXSPI2_IPCR0 = addr;

  297. 	FLEXSPI2_IPCR1 = FLEXSPI_IPCR1_ISEQID(3) | FLEXSPI_IPCR1_IDATSZ(4);

  298. 	FLEXSPI2_IPCMD = FLEXSPI_IPCMD_TRG;

  299. 	while (!(FLEXSPI2_INTR & FLEXSPI_INTR_IPCMDDONE)); // wait

  300. 	uint32_t id = FLEXSPI2_RFDR0;

  301. 	FLEXSPI2_INTR = FLEXSPI_INTR_IPCMDDONE | FLEXSPI_INTR_IPRXWA;

  302. 	return id & 0xFFFF;

  303. }

  304. 

  305. FLASHMEM void configure_external_ram()

  306. {

  307. 	// initialize pins

  308. 	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 = 0x1B0F9; // 100K pullup, strong drive, max speed, hyst

  309. 	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 = 0x110F9; // keeper, strong drive, max speed, hyst

  310. 	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 = 0x1B0F9; // 100K pullup, strong drive, max speed, hyst

  311. 	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 = 0x100F9; // strong drive, max speed, hyst

  312. 	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 = 0x170F9; // 47K pullup, strong drive, max speed, hyst

  313. 	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 = 0x170F9; // 47K pullup, strong drive, max speed, hyst

  314. 	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 = 0x170F9; // 47K pullup, strong drive, max speed, hyst

  315. 	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 = 0x170F9; // 47K pullup, strong drive, max speed, hyst

  316. 

  317. 	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 8 | 0x10; // ALT1 = FLEXSPI2_A_SS1_B (Flash)

  318. 	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 8 | 0x10; // ALT1 = FLEXSPI2_A_DQS

  319. 	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 8 | 0x10; // ALT1 = FLEXSPI2_A_SS0_B (RAM)

  320. 	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 8 | 0x10; // ALT1 = FLEXSPI2_A_SCLK

  321. 	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 8 | 0x10; // ALT1 = FLEXSPI2_A_DATA0

  322. 	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 8 | 0x10; // ALT1 = FLEXSPI2_A_DATA1

  323. 	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 = 8 | 0x10; // ALT1 = FLEXSPI2_A_DATA2

  324. 	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 = 8 | 0x10; // ALT1 = FLEXSPI2_A_DATA3

  325. 

  326. 	IOMUXC_FLEXSPI2_IPP_IND_DQS_FA_SELECT_INPUT = 1; // GPIO_EMC_23 for Mode: ALT8, pg 986

  327. 	IOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT0_SELECT_INPUT = 1; // GPIO_EMC_26 for Mode: ALT8

  328. 	IOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT1_SELECT_INPUT = 1; // GPIO_EMC_27 for Mode: ALT8

  329. 	IOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT2_SELECT_INPUT = 1; // GPIO_EMC_28 for Mode: ALT8

  330. 	IOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT3_SELECT_INPUT = 1; // GPIO_EMC_29 for Mode: ALT8

  331. 	IOMUXC_FLEXSPI2_IPP_IND_SCK_FA_SELECT_INPUT = 1; // GPIO_EMC_25 for Mode: ALT8

  332. 

  333. 	// turn on clock  (TODO: increase clock speed later, slow & cautious for first release)

  334. 	CCM_CBCMR = (CCM_CBCMR & ~(CCM_CBCMR_FLEXSPI2_PODF_MASK | CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK))

  335. 		| CCM_CBCMR_FLEXSPI2_PODF(5) | CCM_CBCMR_FLEXSPI2_CLK_SEL(3); // 88 MHz

  336. 	CCM_CCGR7 |= CCM_CCGR7_FLEXSPI2(CCM_CCGR_ON);

  337. 

  338. 	FLEXSPI2_MCR0 |= FLEXSPI_MCR0_MDIS;

  339. 	FLEXSPI2_MCR0 = (FLEXSPI2_MCR0 & ~(FLEXSPI_MCR0_AHBGRANTWAIT_MASK

  340. 		 | FLEXSPI_MCR0_IPGRANTWAIT_MASK | FLEXSPI_MCR0_SCKFREERUNEN

  341. 		 | FLEXSPI_MCR0_COMBINATIONEN | FLEXSPI_MCR0_DOZEEN

  342. 		 | FLEXSPI_MCR0_HSEN | FLEXSPI_MCR0_ATDFEN | FLEXSPI_MCR0_ARDFEN

  343. 		 | FLEXSPI_MCR0_RXCLKSRC_MASK | FLEXSPI_MCR0_SWRESET))

  344. 		| FLEXSPI_MCR0_AHBGRANTWAIT(0xFF) | FLEXSPI_MCR0_IPGRANTWAIT(0xFF)

  345. 		| FLEXSPI_MCR0_RXCLKSRC(1) | FLEXSPI_MCR0_MDIS;

  346. 	FLEXSPI2_MCR1 = FLEXSPI_MCR1_SEQWAIT(0xFFFF) | FLEXSPI_MCR1_AHBBUSWAIT(0xFFFF);

  347. 	FLEXSPI2_MCR2 = (FLEXSPI_MCR2 & ~(FLEXSPI_MCR2_RESUMEWAIT_MASK

  348. 		 | FLEXSPI_MCR2_SCKBDIFFOPT | FLEXSPI_MCR2_SAMEDEVICEEN

  349. 		 | FLEXSPI_MCR2_CLRLEARNPHASE | FLEXSPI_MCR2_CLRAHBBUFOPT))

  350. 		| FLEXSPI_MCR2_RESUMEWAIT(0x20) /*| FLEXSPI_MCR2_SAMEDEVICEEN*/;

  351. 

  352. 	FLEXSPI2_AHBCR = FLEXSPI2_AHBCR & ~(FLEXSPI_AHBCR_READADDROPT | FLEXSPI_AHBCR_PREFETCHEN

  353. 		| FLEXSPI_AHBCR_BUFFERABLEEN | FLEXSPI_AHBCR_CACHABLEEN);

  354. 	uint32_t mask = (FLEXSPI_AHBRXBUFCR0_PREFETCHEN | FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK

  355. 		| FLEXSPI_AHBRXBUFCR0_MSTRID_MASK | FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK);

  356. 	FLEXSPI2_AHBRXBUF0CR0 = (FLEXSPI2_AHBRXBUF0CR0 & ~mask)

  357. 		| FLEXSPI_AHBRXBUFCR0_PREFETCHEN | FLEXSPI_AHBRXBUFCR0_BUFSZ(64);

  358. 	FLEXSPI2_AHBRXBUF1CR0 = (FLEXSPI2_AHBRXBUF0CR0 & ~mask)

  359. 		| FLEXSPI_AHBRXBUFCR0_PREFETCHEN | FLEXSPI_AHBRXBUFCR0_BUFSZ(64);

  360. 	FLEXSPI2_AHBRXBUF2CR0 = mask;

  361. 	FLEXSPI2_AHBRXBUF3CR0 = mask;

  362. 

  363. 	// RX watermark = one 64 bit line

  364. 	FLEXSPI2_IPRXFCR = (FLEXSPI_IPRXFCR & 0xFFFFFFC0) | FLEXSPI_IPRXFCR_CLRIPRXF;

  365. 	// TX watermark = one 64 bit line

  366. 	FLEXSPI2_IPTXFCR = (FLEXSPI_IPTXFCR & 0xFFFFFFC0) | FLEXSPI_IPTXFCR_CLRIPTXF;

  367. 

  368. 	FLEXSPI2_INTEN = 0;

  369. 	FLEXSPI2_FLSHA1CR0 = 0x2000; // 8 MByte

  370. 	FLEXSPI2_FLSHA1CR1 = FLEXSPI_FLSHCR1_CSINTERVAL(2)

  371. 		| FLEXSPI_FLSHCR1_TCSH(3) | FLEXSPI_FLSHCR1_TCSS(3);

  372. 	FLEXSPI2_FLSHA1CR2 = FLEXSPI_FLSHCR2_AWRSEQID(6) | FLEXSPI_FLSHCR2_AWRSEQNUM(0)

  373. 		| FLEXSPI_FLSHCR2_ARDSEQID(5) | FLEXSPI_FLSHCR2_ARDSEQNUM(0);

  374. 

  375. 	FLEXSPI2_FLSHA2CR0 = 0x2000; // 8 MByte

  376. 	FLEXSPI2_FLSHA2CR1 = FLEXSPI_FLSHCR1_CSINTERVAL(2)

  377. 		| FLEXSPI_FLSHCR1_TCSH(3) | FLEXSPI_FLSHCR1_TCSS(3);

  378. 	FLEXSPI2_FLSHA2CR2 = FLEXSPI_FLSHCR2_AWRSEQID(6) | FLEXSPI_FLSHCR2_AWRSEQNUM(0)

  379. 		| FLEXSPI_FLSHCR2_ARDSEQID(5) | FLEXSPI_FLSHCR2_ARDSEQNUM(0);

  380. 

  381. 	FLEXSPI2_MCR0 &= ~FLEXSPI_MCR0_MDIS;

  382. 

  383. 	FLEXSPI2_LUTKEY = FLEXSPI_LUTKEY_VALUE;

  384. 	FLEXSPI2_LUTCR = FLEXSPI_LUTCR_UNLOCK;

  385. 	volatile uint32_t *luttable = &FLEXSPI2_LUT0;

  386. 	for (int i=0; i < 64; i++) luttable[i] = 0;

  387. 	FLEXSPI2_MCR0 |= FLEXSPI_MCR0_SWRESET;

  388. 	while (FLEXSPI2_MCR0 & FLEXSPI_MCR0_SWRESET) ; // wait

  389. 

  390. 	FLEXSPI2_LUTKEY = FLEXSPI_LUTKEY_VALUE;

  391. 	FLEXSPI2_LUTCR = FLEXSPI_LUTCR_UNLOCK;

  392. 

  393. 	// cmd index 0 = exit QPI mode

  394. 	FLEXSPI2_LUT0 = LUT0(CMD_SDR, PINS4, 0xF5);

  395. 	// cmd index 1 = reset enable

  396. 	FLEXSPI2_LUT4 = LUT0(CMD_SDR, PINS1, 0x66);

  397. 	// cmd index 2 = reset

  398. 	FLEXSPI2_LUT8 = LUT0(CMD_SDR, PINS1, 0x99);

  399. 	// cmd index 3 = read ID bytes

  400. 	FLEXSPI2_LUT12 = LUT0(CMD_SDR, PINS1, 0x9F) | LUT1(DUMMY_SDR, PINS1, 24);

  401. 	FLEXSPI2_LUT13 = LUT0(READ_SDR, PINS1, 1);

  402. 	// cmd index 4 = enter QPI mode

  403. 	FLEXSPI2_LUT16 = LUT0(CMD_SDR, PINS1, 0x35);

  404. 	// cmd index 5 = read QPI

  405. 	FLEXSPI2_LUT20 = LUT0(CMD_SDR, PINS4, 0xEB) | LUT1(ADDR_SDR, PINS4, 24);

  406. 	FLEXSPI2_LUT21 = LUT0(DUMMY_SDR, PINS4, 6) | LUT1(READ_SDR, PINS4, 1);

  407. 	// cmd index 6 = write QPI

  408. 	FLEXSPI2_LUT24 = LUT0(CMD_SDR, PINS4, 0x38) | LUT1(ADDR_SDR, PINS4, 24);

  409. 	FLEXSPI2_LUT25 = LUT0(WRITE_SDR, PINS4, 1);

  410. 

  411. 	// look for the first PSRAM chip

  412. 	flexspi2_command(0, 0); // exit quad mode

  413. 	flexspi2_command(1, 0); // reset enable

  414. 	flexspi2_command(2, 0); // reset (is this really necessary?)

  415. 	if (flexspi2_psram_id(0) == 0x5D0D) {

  416. 		// first PSRAM chip is present, look for a second PSRAM chip

  417. 		flexspi2_command(4, 0);

  418. 		flexspi2_command(0, 0x800000); // exit quad mode

  419. 		flexspi2_command(1, 0x800000); // reset enable

  420. 		flexspi2_command(2, 0x800000); // reset (is this really necessary?)

  421. 		if (flexspi2_psram_id(0x800000) == 0x5D0D) {

  422. 			flexspi2_command(4, 0x800000);

  423. 			// Two PSRAM chips are present, 16 MByte

  424. 			external_psram_size = 16;

  425. 		} else {

  426. 			// One PSRAM chip is present, 8 MByte

  427. 			external_psram_size = 8;

  428. 		}

  429. 		// TODO: zero uninitialized EXTMEM variables

  430. 		// TODO: copy from flash to initialize EXTMEM variables

  431. 		// TODO: set up for malloc_extmem()

  432. 	} else {

  433. 		// No PSRAM

  434. 	}

  435. }

  436. 

  437. #endif // ARDUINO_TEENSY41

  438. 

  439. 

  440. FLASHMEM void usb_pll_start()

  441. {

  442. 	while (1) {

  443. 		uint32_t n = CCM_ANALOG_PLL_USB1; // pg 759

  444. 		printf("CCM_ANALOG_PLL_USB1=%08lX\n", n);

  445. 		if (n & CCM_ANALOG_PLL_USB1_DIV_SELECT) {

  446. 			printf("  ERROR, 528 MHz mode!\n"); // never supposed to use this mode!

  447. 			CCM_ANALOG_PLL_USB1_CLR = 0xC000;			// bypass 24 MHz

  448. 			CCM_ANALOG_PLL_USB1_SET = CCM_ANALOG_PLL_USB1_BYPASS;	// bypass

  449. 			CCM_ANALOG_PLL_USB1_CLR = CCM_ANALOG_PLL_USB1_POWER |	// power down

  450. 				CCM_ANALOG_PLL_USB1_DIV_SELECT |		// use 480 MHz

  451. 				CCM_ANALOG_PLL_USB1_ENABLE |			// disable

  452. 				CCM_ANALOG_PLL_USB1_EN_USB_CLKS;		// disable usb

  453. 			continue;

  454. 		}

  455. 		if (!(n & CCM_ANALOG_PLL_USB1_ENABLE)) {

  456. 			printf("  enable PLL\n");

  457. 			// TODO: should this be done so early, or later??

  458. 			CCM_ANALOG_PLL_USB1_SET = CCM_ANALOG_PLL_USB1_ENABLE;

  459. 			continue;

  460. 		}

  461. 		if (!(n & CCM_ANALOG_PLL_USB1_POWER)) {

  462. 			printf("  power up PLL\n");

  463. 			CCM_ANALOG_PLL_USB1_SET = CCM_ANALOG_PLL_USB1_POWER;

  464. 			continue;

  465. 		}

  466. 		if (!(n & CCM_ANALOG_PLL_USB1_LOCK)) {

  467. 			printf("  wait for lock\n");

  468. 			continue;

  469. 		}

  470. 		if (n & CCM_ANALOG_PLL_USB1_BYPASS) {

  471. 			printf("  turn off bypass\n");

  472. 			CCM_ANALOG_PLL_USB1_CLR = CCM_ANALOG_PLL_USB1_BYPASS;

  473. 			continue;

  474. 		}

  475. 		if (!(n & CCM_ANALOG_PLL_USB1_EN_USB_CLKS)) {

  476. 			printf("  enable USB clocks\n");

  477. 			CCM_ANALOG_PLL_USB1_SET = CCM_ANALOG_PLL_USB1_EN_USB_CLKS;

  478. 			continue;

  479. 		}

  480. 		return; // everything is as it should be  :-)

  481. 	}

  482. }

  483. 

  484. FLASHMEM void reset_PFD()

  485. {	

  486. 	//Reset PLL2 PFDs, set default frequencies:

  487. 	CCM_ANALOG_PFD_528_SET = (1 << 31) | (1 << 23) | (1 << 15) | (1 << 7);

  488. 	CCM_ANALOG_PFD_528 = 0x2018101B; // PFD0:352, PFD1:594, PFD2:396, PFD3:297 MHz 	

  489. 	//PLL3:

  490. 	CCM_ANALOG_PFD_480_SET = (1 << 31) | (1 << 23) | (1 << 15) | (1 << 7);	

  491. 	CCM_ANALOG_PFD_480 = 0x13110D0C; // PFD0:720, PFD1:664, PFD2:508, PFD3:454 MHz

  492. }

  493. 

  494. // Stack frame

  495. //  xPSR

  496. //  ReturnAddress

  497. //  LR (R14) - typically FFFFFFF9 for IRQ or Exception

  498. //  R12

  499. //  R3

  500. //  R2

  501. //  R1

  502. //  R0

  503. // Code from :: https://community.nxp.com/thread/389002

  504. __attribute__((naked))

  505. void unused_interrupt_vector(void)

  506. {

  507.   __asm( ".syntax unified\n"

  508.          "MOVS R0, #4 \n"

  509.          "MOV R1, LR \n"

  510.          "TST R0, R1 \n"

  511.          "BEQ _MSP \n"

  512.          "MRS R0, PSP \n"

  513.          "B HardFault_HandlerC \n"

  514.          "_MSP: \n"

  515.          "MRS R0, MSP \n"

  516.          "B HardFault_HandlerC \n"

  517.          ".syntax divided\n") ;

  518. }

  519. 

  520. __attribute__((weak))

  521. void HardFault_HandlerC(unsigned int *hardfault_args)

  522. {

  523.   volatile unsigned int nn ;

  524. #ifdef PRINT_DEBUG_STUFF

  525.   volatile unsigned int stacked_r0 ;

  526.   volatile unsigned int stacked_r1 ;

  527.   volatile unsigned int stacked_r2 ;

  528.   volatile unsigned int stacked_r3 ;

  529.   volatile unsigned int stacked_r12 ;

  530.   volatile unsigned int stacked_lr ;

  531.   volatile unsigned int stacked_pc ;

  532.   volatile unsigned int stacked_psr ;

  533.   volatile unsigned int _CFSR ;

  534.   volatile unsigned int _HFSR ;

  535.   volatile unsigned int _DFSR ;

  536.   volatile unsigned int _AFSR ;

  537.   volatile unsigned int _BFAR ;

  538.   volatile unsigned int _MMAR ;

  539.   volatile unsigned int addr ;

  540. 

  541.   stacked_r0 = ((unsigned int)hardfault_args[0]) ;

  542.   stacked_r1 = ((unsigned int)hardfault_args[1]) ;

  543.   stacked_r2 = ((unsigned int)hardfault_args[2]) ;

  544.   stacked_r3 = ((unsigned int)hardfault_args[3]) ;

  545.   stacked_r12 = ((unsigned int)hardfault_args[4]) ;

  546.   stacked_lr = ((unsigned int)hardfault_args[5]) ;

  547.   stacked_pc = ((unsigned int)hardfault_args[6]) ;

  548.   stacked_psr = ((unsigned int)hardfault_args[7]) ;

  549.   // Configurable Fault Status Register

  550.   // Consists of MMSR, BFSR and UFSR

  551.   //(n & ( 1 << k )) >> k

  552.   _CFSR = (*((volatile unsigned int *)(0xE000ED28))) ;  

  553.   // Hard Fault Status Register

  554.   _HFSR = (*((volatile unsigned int *)(0xE000ED2C))) ;

  555.   // Debug Fault Status Register

  556.   _DFSR = (*((volatile unsigned int *)(0xE000ED30))) ;

  557.   // Auxiliary Fault Status Register

  558.   _AFSR = (*((volatile unsigned int *)(0xE000ED3C))) ;

  559.   // Read the Fault Address Registers. These may not contain valid values.

  560.   // Check BFARVALID/MMARVALID to see if they are valid values

  561.   // MemManage Fault Address Register

  562.   _MMAR = (*((volatile unsigned int *)(0xE000ED34))) ;

  563.   // Bus Fault Address Register

  564.   _BFAR = (*((volatile unsigned int *)(0xE000ED38))) ;

  565.   //__asm("BKPT #0\n") ; // Break into the debugger // NO Debugger here.

  566. 

  567.   asm volatile("mrs %0, ipsr\n" : "=r" (addr)::);

  568.   printf("\nFault irq %d\n", addr & 0x1FF);

  569.   printf(" stacked_r0 ::  %x\n", stacked_r0);

  570.   printf(" stacked_r1 ::  %x\n", stacked_r1);

  571.   printf(" stacked_r2 ::  %x\n", stacked_r2);

  572.   printf(" stacked_r3 ::  %x\n", stacked_r3);

  573.   printf(" stacked_r12 ::  %x\n", stacked_r12);

  574.   printf(" stacked_lr ::  %x\n", stacked_lr);

  575.   printf(" stacked_pc ::  %x\n", stacked_pc);

  576.   printf(" stacked_psr ::  %x\n", stacked_psr);

  577.   printf(" _CFSR ::  %x\n", _CFSR);

  578.  

  579.   if(_CFSR > 0){

  580. 	  //Memory Management Faults

  581. 	  if((_CFSR & 1) == 1){

  582. 		printf("      (IACCVIOL) Instruction Access Violation\n");

  583. 	  } else  if(((_CFSR & (0x02))>>1) == 1){

  584. 		printf("      (DACCVIOL) Data Access Violation\n");

  585. 	  } else if(((_CFSR & (0x08))>>3) == 1){

  586. 		printf("      (MUNSTKERR) MemMange Fault on Unstacking\n");

  587. 	  } else if(((_CFSR & (0x10))>>4) == 1){

  588. 		printf("      (MSTKERR) MemMange Fault on stacking\n");

  589. 	  } else if(((_CFSR & (0x20))>>5) == 1){

  590. 		printf("      (MLSPERR) MemMange Fault on FP Lazy State\n");

  591. 	  }

  592. 	  if(((_CFSR & (0x80))>>7) == 1){

  593. 		printf("      (MMARVALID) MemMange Fault Address Valid\n");

  594. 	  }

  595. 	  //Bus Fault Status Register

  596. 	  if(((_CFSR & 0x100)>>8) == 1){

  597. 		printf("      (IBUSERR) Instruction Bus Error\n");

  598. 	  } else  if(((_CFSR & (0x200))>>9) == 1){

  599. 		printf("      (PRECISERR) Data bus error(address in BFAR)\n");

  600. 	  } else if(((_CFSR & (0x400))>>10) == 1){

  601. 		printf("      (IMPRECISERR) Data bus error but address not related to instruction\n");

  602. 	  } else if(((_CFSR & (0x800))>>11) == 1){

  603. 		printf("      (UNSTKERR) Bus Fault on unstacking for a return from exception \n");

  604. 	  } else if(((_CFSR & (0x1000))>>12) == 1){

  605. 		printf("      (STKERR) Bus Fault on stacking for exception entry\n");

  606. 	  } else if(((_CFSR & (0x2000))>>13) == 1){

  607. 		printf("      (LSPERR) Bus Fault on FP lazy state preservation\n");

  608. 	  }

  609. 	  if(((_CFSR & (0x8000))>>15) == 1){

  610. 		printf("      (BFARVALID) Bus Fault Address Valid\n");

  611. 	  }  

  612. 	  //Usuage Fault Status Register

  613. 	  if(((_CFSR & 0x10000)>>16) == 1){

  614. 		printf("      (UNDEFINSTR) Undefined instruction\n");

  615. 	  } else  if(((_CFSR & (0x20000))>>17) == 1){

  616. 		printf("      (INVSTATE) Instruction makes illegal use of EPSR)\n");

  617. 	  } else if(((_CFSR & (0x40000))>>18) == 1){

  618. 		printf("      (INVPC) Usage fault: invalid EXC_RETURN\n");

  619. 	  } else if(((_CFSR & (0x80000))>>19) == 1){

  620. 		printf("      (NOCP) No Coprocessor \n");

  621. 	  } else if(((_CFSR & (0x1000000))>>24) == 1){

  622. 		printf("      (UNALIGNED) Unaligned access UsageFault\n");

  623. 	  } else if(((_CFSR & (0x2000000))>>25) == 1){

  624. 		printf("      (DIVBYZERO) Divide by zero\n");

  625. 	  }

  626.   }

  627.   printf(" _HFSR ::  %x\n", _HFSR);

  628.   if(_HFSR > 0){

  629. 	  //Memory Management Faults

  630. 	  if(((_HFSR & (0x02))>>1) == 1){

  631. 		printf("      (VECTTBL) Bus Fault on Vec Table Read\n");

  632. 	  } else if(((_HFSR & (0x40000000))>>30) == 1){

  633. 		printf("      (FORCED) Forced Hard Fault\n");

  634. 	  } else if(((_HFSR & (0x80000000))>>31) == 31){

  635. 		printf("      (DEBUGEVT) Reserved for Debug\n");

  636. 	  } 

  637.   }

  638.   printf(" _DFSR ::  %x\n", _DFSR);

  639.   printf(" _AFSR ::  %x\n", _AFSR);

  640.   printf(" _BFAR ::  %x\n", _BFAR);

  641.   printf(" _MMAR ::  %x\n", _MMAR);

  642. #endif

  643. 

  644.   IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 5; // pin 13

  645.   IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = IOMUXC_PAD_DSE(7);

  646.   GPIO2_GDIR |= (1 << 3);

  647.   GPIO2_DR_SET = (1 << 3);

  648.   GPIO2_DR_CLEAR = (1 << 3); //digitalWrite(13, LOW);

  649. 

  650.   if ( F_CPU_ACTUAL >= 600000000 )

  651.     set_arm_clock(300000000);

  652. 

  653.   while (1)

  654.   {

  655.     GPIO2_DR_SET = (1 << 3); //digitalWrite(13, HIGH);

  656.     // digitalWrite(13, HIGH);

  657.     for (nn = 0; nn < 2000000/2; nn++) ;

  658.     GPIO2_DR_CLEAR = (1 << 3); //digitalWrite(13, LOW);

  659.     // digitalWrite(13, LOW);

  660.     for (nn = 0; nn < 18000000/2; nn++) ;

  661.   }

  662. }

  663. 

  664. __attribute__((weak))

  665. void userDebugDump(){

  666. 	volatile unsigned int nn;

  667. 	printf("\nuserDebugDump() in startup.c ___ \n");

  668. 

  669.   while (1)

  670.   {

  671.     GPIO2_DR_SET = (1 << 3); //digitalWrite(13, HIGH);

  672.     // digitalWrite(13, HIGH);

  673.     for (nn = 0; nn < 2000000; nn++) ;

  674.     GPIO2_DR_CLEAR = (1 << 3); //digitalWrite(13, LOW);

  675. 	// digitalWrite(13, LOW);

  676.     for (nn = 0; nn < 18000000; nn++) ;

  677.     GPIO2_DR_SET = (1 << 3); //digitalWrite(13, HIGH);

  678.     // digitalWrite(13, HIGH);

  679.     for (nn = 0; nn < 20000000; nn++) ;

  680.     GPIO2_DR_CLEAR = (1 << 3); //digitalWrite(13, LOW);

  681. 	// digitalWrite(13, LOW);

  682.     for (nn = 0; nn < 10000000; nn++) ;

  683.   }

  684. }

  685. 

  686. __attribute__((weak))

  687. void PJRCunused_interrupt_vector(void)

  688. {

  689. 	// TODO: polling Serial to complete buffered transmits

  690. #ifdef PRINT_DEBUG_STUFF

  691. 	uint32_t addr;

  692. 	asm volatile("mrs %0, ipsr\n" : "=r" (addr)::);

  693. 	printf("\nirq %d\n", addr & 0x1FF);

  694. 	asm("ldr %0, [sp, #52]" : "=r" (addr) ::);

  695. 	printf(" %x\n", addr);

  696. 	asm("ldr %0, [sp, #48]" : "=r" (addr) ::);

  697. 	printf(" %x\n", addr);

  698. 	asm("ldr %0, [sp, #44]" : "=r" (addr) ::);

  699. 	printf(" %x\n", addr);

  700. 	asm("ldr %0, [sp, #40]" : "=r" (addr) ::);

  701. 	printf(" %x\n", addr);

  702. 	asm("ldr %0, [sp, #36]" : "=r" (addr) ::);

  703. 	printf(" %x\n", addr);

  704. 	asm("ldr %0, [sp, #33]" : "=r" (addr) ::);

  705. 	printf(" %x\n", addr);

  706. 	asm("ldr %0, [sp, #34]" : "=r" (addr) ::);

  707. 	printf(" %x\n", addr);

  708. 	asm("ldr %0, [sp, #28]" : "=r" (addr) ::);

  709. 	printf(" %x\n", addr);

  710. 	asm("ldr %0, [sp, #24]" : "=r" (addr) ::);

  711. 	printf(" %x\n", addr);

  712. 	asm("ldr %0, [sp, #20]" : "=r" (addr) ::);

  713. 	printf(" %x\n", addr);

  714. 	asm("ldr %0, [sp, #16]" : "=r" (addr) ::);

  715. 	printf(" %x\n", addr);

  716. 	asm("ldr %0, [sp, #12]" : "=r" (addr) ::);

  717. 	printf(" %x\n", addr);

  718. 	asm("ldr %0, [sp, #8]" : "=r" (addr) ::);

  719. 	printf(" %x\n", addr);

  720. 	asm("ldr %0, [sp, #4]" : "=r" (addr) ::);

  721. 	printf(" %x\n", addr);

  722. 	asm("ldr %0, [sp, #0]" : "=r" (addr) ::);

  723. 	printf(" %x\n", addr);

  724. #endif

  725. #if 1

  726. 	if ( F_CPU_ACTUAL >= 600000000 )

  727. 		set_arm_clock(100000000);

  728. 	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 5; // pin 13

  729. 	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = IOMUXC_PAD_DSE(7);

  730. 	GPIO2_GDIR |= (1<<3);

  731. 	GPIO2_DR_SET = (1<<3);

  732. 	while (1) {

  733. 		volatile uint32_t n;

  734. 		GPIO2_DR_SET = (1<<3); //digitalWrite(13, HIGH);

  735. 		for (n=0; n < 2000000/6; n++) ;

  736. 		GPIO2_DR_CLEAR = (1<<3); //digitalWrite(13, LOW);

  737. 		for (n=0; n < 1500000/6; n++) ;

  738. 	}

  739. #else

  740. 	if ( F_CPU_ACTUAL >= 600000000 )

  741. 		set_arm_clock(100000000);

  742. 	while (1) asm ("WFI");

  743. #endif

  744. }

  745. 

  746. __attribute__((section(".startup"), optimize("no-tree-loop-distribute-patterns")))

  747. static void memory_copy(uint32_t *dest, const uint32_t *src, uint32_t *dest_end)

  748. {

  749. 	if (dest == src) return;

  750. 	while (dest < dest_end) {

  751. 		*dest++ = *src++;

  752. 	}

  753. }

  754. 

  755. __attribute__((section(".startup"), optimize("no-tree-loop-distribute-patterns")))

  756. static void memory_clear(uint32_t *dest, uint32_t *dest_end)

  757. {

  758. 	while (dest < dest_end) {

  759. 		*dest++ = 0;

  760. 	}

  761. }

  762. 

  763. 

  764. 

  765. // syscall functions need to be in the same C file as the entry point "ResetVector"

  766. // otherwise the linker will discard them in some cases.

  767. 

  768. #include <errno.h>

  769. 

  770. // from the linker script

  771. extern unsigned long _heap_start;

  772. extern unsigned long _heap_end;

  773. 

  774. char *__brkval = (char *)&_heap_start;

  775. 

  776. void * _sbrk(int incr)

  777. {

  778.         char *prev = __brkval;

  779.         if (incr != 0) {

  780.                 if (prev + incr > (char *)&_heap_end) {

  781.                         errno = ENOMEM;

  782.                         return (void *)-1;

  783.                 }

  784.                 __brkval = prev + incr;

  785.         }

  786.         return prev;

  787. }

  788. 

  789. __attribute__((weak))

  790. int _read(int file, char *ptr, int len)

  791. {

  792. 	return 0;

  793. }

  794. 

  795. __attribute__((weak))

  796. int _close(int fd)

  797. {

  798. 	return -1;

  799. }

  800. 

  801. #include <sys/stat.h>

  802. 

  803. __attribute__((weak))

  804. int _fstat(int fd, struct stat *st)

  805. {

  806. 	st->st_mode = S_IFCHR;

  807. 	return 0;

  808. }

  809. 

  810. __attribute__((weak))

  811. int _isatty(int fd)

  812. {

  813. 	return 1;

  814. }

  815. 

  816. __attribute__((weak))

  817. int _lseek(int fd, long long offset, int whence)

  818. {

  819. 	return -1;

  820. }

  821. 

  822. __attribute__((weak))

  823. void _exit(int status)

  824. {

  825. 	while (1) asm ("WFI");

  826. }

  827. 

  828. __attribute__((weak))

  829. void __cxa_pure_virtual()

  830. {

  831. 	while (1) asm ("WFI");

  832. }

  833. 

  834. __attribute__((weak))

  835. int __cxa_guard_acquire (char *g)

  836. {

  837. 	return !(*g);

  838. }

  839. 

  840. __attribute__((weak))

  841. void __cxa_guard_release(char *g)

  842. {

  843. 	*g = 1;

  844. }

  845. 

  846. __attribute__((weak))

  847. void abort(void)

  848. {

  849. 	while (1) asm ("WFI");

  850. }