Teensy 4.1 core updated for C++20
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  1. /* Teensyduino Core Library
  2. * http://www.pjrc.com/teensy/
  3. * Copyright (c) 2013 PJRC.COM, LLC.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining
  6. * a copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sublicense, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * 1. The above copyright notice and this permission notice shall be
  14. * included in all copies or substantial portions of the Software.
  15. *
  16. * 2. If the Software is incorporated into a build system that allows
  17. * selection among a list of target devices, then similar target
  18. * devices manufactured by PJRC.COM must be included in the list of
  19. * target devices and selectable in the same manner.
  20. *
  21. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  24. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  25. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  26. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  27. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  28. * SOFTWARE.
  29. */
  30. #include "kinetis.h"
  31. #include "core_pins.h"
  32. #include "HardwareSerial.h"
  33. ////////////////////////////////////////////////////////////////
  34. // Tunable parameters (relatively safe to edit these numbers)
  35. ////////////////////////////////////////////////////////////////
  36. #define TX_BUFFER_SIZE 64 // number of outgoing bytes to buffer
  37. #define RX_BUFFER_SIZE 64 // number of incoming bytes to buffer
  38. #define IRQ_PRIORITY 64 // 0 = highest priority, 255 = lowest
  39. ////////////////////////////////////////////////////////////////
  40. // changes not recommended below this point....
  41. ////////////////////////////////////////////////////////////////
  42. #ifdef SERIAL_9BIT_SUPPORT
  43. static uint8_t use9Bits = 0;
  44. #define BUFTYPE uint16_t
  45. #else
  46. #define BUFTYPE uint8_t
  47. #define use9Bits 0
  48. #endif
  49. static volatile BUFTYPE tx_buffer[TX_BUFFER_SIZE];
  50. static volatile BUFTYPE rx_buffer[RX_BUFFER_SIZE];
  51. static volatile uint8_t transmitting = 0;
  52. static volatile uint8_t *transmit_pin=NULL;
  53. #if TX_BUFFER_SIZE > 255
  54. static volatile uint16_t tx_buffer_head = 0;
  55. static volatile uint16_t tx_buffer_tail = 0;
  56. #else
  57. static volatile uint8_t tx_buffer_head = 0;
  58. static volatile uint8_t tx_buffer_tail = 0;
  59. #endif
  60. #if RX_BUFFER_SIZE > 255
  61. static volatile uint16_t rx_buffer_head = 0;
  62. static volatile uint16_t rx_buffer_tail = 0;
  63. #else
  64. static volatile uint8_t rx_buffer_head = 0;
  65. static volatile uint8_t rx_buffer_tail = 0;
  66. #endif
  67. // UART0 and UART1 are clocked by F_CPU, UART2 is clocked by F_BUS
  68. // UART0 has 8 byte fifo, UART1 and UART2 have 1 byte buffer
  69. #ifdef KINETISK_UART0_FIFO
  70. #define C2_ENABLE UART_C2_TE | UART_C2_RE | UART_C2_RIE | UART_C2_ILIE
  71. #else
  72. #define C2_ENABLE UART_C2_TE | UART_C2_RE | UART_C2_RIE
  73. #endif
  74. #define C2_TX_ACTIVE C2_ENABLE | UART_C2_TIE
  75. #define C2_TX_COMPLETING C2_ENABLE | UART_C2_TCIE
  76. #define C2_TX_INACTIVE C2_ENABLE
  77. void serial_begin(uint32_t divisor)
  78. {
  79. SIM_SCGC4 |= SIM_SCGC4_UART0; // turn on clock, TODO: use bitband
  80. rx_buffer_head = 0;
  81. rx_buffer_tail = 0;
  82. tx_buffer_head = 0;
  83. tx_buffer_tail = 0;
  84. transmitting = 0;
  85. CORE_PIN0_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3);
  86. CORE_PIN1_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3);
  87. #if defined(KINETISK_UART0)
  88. UART0_BDH = (divisor >> 13) & 0x1F;
  89. UART0_BDL = (divisor >> 5) & 0xFF;
  90. UART0_C4 = divisor & 0x1F;
  91. #ifdef KINETISK_UART0_FIFO
  92. UART0_C1 = UART_C1_ILT;
  93. UART0_TWFIFO = 2; // tx watermark, causes S1_TDRE to set
  94. UART0_RWFIFO = 4; // rx watermark, causes S1_RDRF to set
  95. UART0_PFIFO = UART_PFIFO_TXFE | UART_PFIFO_RXFE;
  96. #else
  97. UART0_C1 = 0;
  98. UART0_PFIFO = 0;
  99. #endif
  100. #elif defined(KINETISL_UART1)
  101. UART0_BDH = (divisor >> 8) & 0x1F;
  102. UART0_BDL = divisor & 0xFF;
  103. UART0_C1 = 0;
  104. #endif
  105. UART0_C2 = C2_TX_INACTIVE;
  106. NVIC_SET_PRIORITY(IRQ_UART0_STATUS, IRQ_PRIORITY);
  107. NVIC_ENABLE_IRQ(IRQ_UART0_STATUS);
  108. }
  109. void serial_format(uint32_t format)
  110. {
  111. uint8_t c;
  112. c = UART0_C1;
  113. c = (c & ~0x13) | (format & 0x03); // configure parity
  114. if (format & 0x04) c |= 0x10; // 9 bits (might include parity)
  115. UART0_C1 = c;
  116. if ((format & 0x0F) == 0x04) UART0_C3 |= 0x40; // 8N2 is 9 bit with 9th bit always 1
  117. c = UART0_S2 & ~0x10;
  118. if (format & 0x10) c |= 0x10; // rx invert
  119. UART0_S2 = c;
  120. c = UART0_C3 & ~0x10;
  121. if (format & 0x20) c |= 0x10; // tx invert
  122. UART0_C3 = c;
  123. #ifdef SERIAL_9BIT_SUPPORT
  124. c = UART0_C4 & 0x1F;
  125. if (format & 0x08) c |= 0x20; // 9 bit mode with parity (requires 10 bits)
  126. UART0_C4 = c;
  127. use9Bits = format & 0x80;
  128. #endif
  129. }
  130. void serial_end(void)
  131. {
  132. if (!(SIM_SCGC4 & SIM_SCGC4_UART0)) return;
  133. while (transmitting) yield(); // wait for buffered data to send
  134. NVIC_DISABLE_IRQ(IRQ_UART0_STATUS);
  135. UART0_C2 = 0;
  136. CORE_PIN0_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1);
  137. CORE_PIN1_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1);
  138. rx_buffer_head = 0;
  139. rx_buffer_tail = 0;
  140. }
  141. void serial_set_transmit_pin(uint8_t pin)
  142. {
  143. while (transmitting) ;
  144. pinMode(pin, OUTPUT);
  145. digitalWrite(pin, LOW);
  146. transmit_pin = portOutputRegister(pin);
  147. }
  148. void serial_putchar(uint32_t c)
  149. {
  150. uint32_t head, n;
  151. if (!(SIM_SCGC4 & SIM_SCGC4_UART0)) return;
  152. if (transmit_pin) *transmit_pin = 1;
  153. head = tx_buffer_head;
  154. if (++head >= TX_BUFFER_SIZE) head = 0;
  155. while (tx_buffer_tail == head) {
  156. int priority = nvic_execution_priority();
  157. if (priority <= IRQ_PRIORITY) {
  158. if ((UART0_S1 & UART_S1_TDRE)) {
  159. uint32_t tail = tx_buffer_tail;
  160. if (++tail >= TX_BUFFER_SIZE) tail = 0;
  161. n = tx_buffer[tail];
  162. if (use9Bits) UART0_C3 = (UART0_C3 & ~0x40) | ((n & 0x100) >> 2);
  163. UART0_D = n;
  164. tx_buffer_tail = tail;
  165. }
  166. } else if (priority >= 256) {
  167. yield();
  168. }
  169. }
  170. tx_buffer[head] = c;
  171. transmitting = 1;
  172. tx_buffer_head = head;
  173. UART0_C2 = C2_TX_ACTIVE;
  174. }
  175. #ifdef KINETISK_UART0_FIFO
  176. void serial_write(const void *buf, unsigned int count)
  177. {
  178. const uint8_t *p = (const uint8_t *)buf;
  179. const uint8_t *end = p + count;
  180. uint32_t head, n;
  181. if (!(SIM_SCGC4 & SIM_SCGC4_UART0)) return;
  182. if (transmit_pin) *transmit_pin = 1;
  183. while (p < end) {
  184. head = tx_buffer_head;
  185. if (++head >= TX_BUFFER_SIZE) head = 0;
  186. if (tx_buffer_tail == head) {
  187. UART0_C2 = C2_TX_ACTIVE;
  188. do {
  189. int priority = nvic_execution_priority();
  190. if (priority <= IRQ_PRIORITY) {
  191. if ((UART0_S1 & UART_S1_TDRE)) {
  192. uint32_t tail = tx_buffer_tail;
  193. if (++tail >= TX_BUFFER_SIZE) tail = 0;
  194. n = tx_buffer[tail];
  195. if (use9Bits) UART0_C3 = (UART0_C3 & ~0x40) | ((n & 0x100) >> 2);
  196. UART0_D = n;
  197. tx_buffer_tail = tail;
  198. }
  199. } else if (priority >= 256) {
  200. yield();
  201. }
  202. } while (tx_buffer_tail == head);
  203. }
  204. tx_buffer[head] = *p++;
  205. transmitting = 1;
  206. tx_buffer_head = head;
  207. }
  208. UART0_C2 = C2_TX_ACTIVE;
  209. }
  210. #else
  211. void serial_write(const void *buf, unsigned int count)
  212. {
  213. const uint8_t *p = (const uint8_t *)buf;
  214. while (count-- > 0) serial_putchar(*p++);
  215. }
  216. #endif
  217. void serial_flush(void)
  218. {
  219. while (transmitting) yield(); // wait
  220. }
  221. int serial_write_buffer_free(void)
  222. {
  223. uint32_t head, tail;
  224. head = tx_buffer_head;
  225. tail = tx_buffer_tail;
  226. if (head >= tail) return TX_BUFFER_SIZE - 1 - head + tail;
  227. return tail - head - 1;
  228. }
  229. int serial_available(void)
  230. {
  231. uint32_t head, tail;
  232. head = rx_buffer_head;
  233. tail = rx_buffer_tail;
  234. if (head >= tail) return head - tail;
  235. return RX_BUFFER_SIZE + head - tail;
  236. }
  237. int serial_getchar(void)
  238. {
  239. uint32_t head, tail;
  240. int c;
  241. head = rx_buffer_head;
  242. tail = rx_buffer_tail;
  243. if (head == tail) return -1;
  244. if (++tail >= RX_BUFFER_SIZE) tail = 0;
  245. c = rx_buffer[tail];
  246. rx_buffer_tail = tail;
  247. return c;
  248. }
  249. int serial_peek(void)
  250. {
  251. uint32_t head, tail;
  252. head = rx_buffer_head;
  253. tail = rx_buffer_tail;
  254. if (head == tail) return -1;
  255. if (++tail >= RX_BUFFER_SIZE) tail = 0;
  256. return rx_buffer[tail];
  257. }
  258. void serial_clear(void)
  259. {
  260. #ifdef KINETISK_UART0_FIFO
  261. if (!(SIM_SCGC4 & SIM_SCGC4_UART0)) return;
  262. UART0_C2 &= ~(UART_C2_RE | UART_C2_RIE | UART_C2_ILIE);
  263. UART0_CFIFO = UART_CFIFO_RXFLUSH;
  264. UART0_C2 |= (UART_C2_RE | UART_C2_RIE | UART_C2_ILIE);
  265. #endif
  266. rx_buffer_head = rx_buffer_tail;
  267. }
  268. // status interrupt combines
  269. // Transmit data below watermark UART_S1_TDRE
  270. // Transmit complete UART_S1_TC
  271. // Idle line UART_S1_IDLE
  272. // Receive data above watermark UART_S1_RDRF
  273. // LIN break detect UART_S2_LBKDIF
  274. // RxD pin active edge UART_S2_RXEDGIF
  275. void uart0_status_isr(void)
  276. {
  277. uint32_t head, tail, n;
  278. uint8_t c;
  279. #ifdef KINETISK_UART0_FIFO
  280. uint32_t newhead;
  281. uint8_t avail;
  282. if (UART0_S1 & (UART_S1_RDRF | UART_S1_IDLE)) {
  283. __disable_irq();
  284. avail = UART0_RCFIFO;
  285. if (avail == 0) {
  286. // The only way to clear the IDLE interrupt flag is
  287. // to read the data register. But reading with no
  288. // data causes a FIFO underrun, which causes the
  289. // FIFO to return corrupted data. If anyone from
  290. // Freescale reads this, what a poor design! There
  291. // write should be a write-1-to-clear for IDLE.
  292. c = UART0_D;
  293. // flushing the fifo recovers from the underrun,
  294. // but there's a possible race condition where a
  295. // new character could be received between reading
  296. // RCFIFO == 0 and flushing the FIFO. To minimize
  297. // the chance, interrupts are disabled so a higher
  298. // priority interrupt (hopefully) doesn't delay.
  299. // TODO: change this to disabling the IDLE interrupt
  300. // which won't be simple, since we already manage
  301. // which transmit interrupts are enabled.
  302. UART0_CFIFO = UART_CFIFO_RXFLUSH;
  303. __enable_irq();
  304. } else {
  305. __enable_irq();
  306. head = rx_buffer_head;
  307. tail = rx_buffer_tail;
  308. do {
  309. n = UART0_D;
  310. if (use9Bits && (UART0_C3 & 0x80)) n |= 0x100;
  311. newhead = head + 1;
  312. if (newhead >= RX_BUFFER_SIZE) newhead = 0;
  313. if (newhead != tail) {
  314. head = newhead;
  315. rx_buffer[head] = n;
  316. }
  317. } while (--avail > 0);
  318. rx_buffer_head = head;
  319. }
  320. }
  321. c = UART0_C2;
  322. if ((c & UART_C2_TIE) && (UART0_S1 & UART_S1_TDRE)) {
  323. head = tx_buffer_head;
  324. tail = tx_buffer_tail;
  325. do {
  326. if (tail == head) break;
  327. if (++tail >= TX_BUFFER_SIZE) tail = 0;
  328. avail = UART0_S1;
  329. n = tx_buffer[tail];
  330. if (use9Bits) UART0_C3 = (UART0_C3 & ~0x40) | ((n & 0x100) >> 2);
  331. UART0_D = n;
  332. } while (UART0_TCFIFO < 8);
  333. tx_buffer_tail = tail;
  334. if (UART0_S1 & UART_S1_TDRE) UART0_C2 = C2_TX_COMPLETING;
  335. }
  336. #else
  337. if (UART0_S1 & UART_S1_RDRF) {
  338. n = UART0_D;
  339. if (use9Bits && (UART0_C3 & 0x80)) n |= 0x100;
  340. head = rx_buffer_head + 1;
  341. if (head >= RX_BUFFER_SIZE) head = 0;
  342. if (head != rx_buffer_tail) {
  343. rx_buffer[head] = n;
  344. rx_buffer_head = head;
  345. }
  346. }
  347. c = UART0_C2;
  348. if ((c & UART_C2_TIE) && (UART0_S1 & UART_S1_TDRE)) {
  349. head = tx_buffer_head;
  350. tail = tx_buffer_tail;
  351. if (head == tail) {
  352. UART0_C2 = C2_TX_COMPLETING;
  353. } else {
  354. if (++tail >= TX_BUFFER_SIZE) tail = 0;
  355. n = tx_buffer[tail];
  356. if (use9Bits) UART0_C3 = (UART0_C3 & ~0x40) | ((n & 0x100) >> 2);
  357. UART0_D = n;
  358. tx_buffer_tail = tail;
  359. }
  360. }
  361. #endif
  362. if ((c & UART_C2_TCIE) && (UART0_S1 & UART_S1_TC)) {
  363. transmitting = 0;
  364. if (transmit_pin) *transmit_pin = 0;
  365. UART0_C2 = C2_TX_INACTIVE;
  366. }
  367. }
  368. void serial_print(const char *p)
  369. {
  370. while (*p) {
  371. char c = *p++;
  372. if (c == '\n') serial_putchar('\r');
  373. serial_putchar(c);
  374. }
  375. }
  376. static void serial_phex1(uint32_t n)
  377. {
  378. n &= 15;
  379. if (n < 10) {
  380. serial_putchar('0' + n);
  381. } else {
  382. serial_putchar('A' - 10 + n);
  383. }
  384. }
  385. void serial_phex(uint32_t n)
  386. {
  387. serial_phex1(n >> 4);
  388. serial_phex1(n);
  389. }
  390. void serial_phex16(uint32_t n)
  391. {
  392. serial_phex(n >> 8);
  393. serial_phex(n);
  394. }
  395. void serial_phex32(uint32_t n)
  396. {
  397. serial_phex(n >> 24);
  398. serial_phex(n >> 16);
  399. serial_phex(n >> 8);
  400. serial_phex(n);
  401. }