Teensy 4.1 core updated for C++20
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  1. /* Teensyduino Core Library
  2. * http://www.pjrc.com/teensy/
  3. * Copyright (c) 2013 PJRC.COM, LLC.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining
  6. * a copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sublicense, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * 1. The above copyright notice and this permission notice shall be
  14. * included in all copies or substantial portions of the Software.
  15. *
  16. * 2. If the Software is incorporated into a build system that allows
  17. * selection among a list of target devices, then similar target
  18. * devices manufactured by PJRC.COM must be included in the list of
  19. * target devices and selectable in the same manner.
  20. *
  21. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  24. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  25. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  26. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  27. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  28. * SOFTWARE.
  29. */
  30. #include "kinetis.h"
  31. #include "core_pins.h"
  32. #include "HardwareSerial.h"
  33. ////////////////////////////////////////////////////////////////
  34. // Tunable parameters (relatively safe to edit these numbers)
  35. ////////////////////////////////////////////////////////////////
  36. #define TX_BUFFER_SIZE 40 // number of outgoing bytes to buffer
  37. #define RX_BUFFER_SIZE 64 // number of incoming bytes to buffer
  38. #define RTS_HIGH_WATERMARK 40 // RTS requests sender to pause
  39. #define RTS_LOW_WATERMARK 26 // RTS allows sender to resume
  40. #define IRQ_PRIORITY 64 // 0 = highest priority, 255 = lowest
  41. ////////////////////////////////////////////////////////////////
  42. // changes not recommended below this point....
  43. ////////////////////////////////////////////////////////////////
  44. #ifdef SERIAL_9BIT_SUPPORT
  45. static uint8_t use9Bits = 0;
  46. #define BUFTYPE uint16_t
  47. #else
  48. #define BUFTYPE uint8_t
  49. #define use9Bits 0
  50. #endif
  51. static volatile BUFTYPE tx_buffer[TX_BUFFER_SIZE];
  52. static volatile BUFTYPE rx_buffer[RX_BUFFER_SIZE];
  53. static volatile uint8_t transmitting = 0;
  54. #if defined(KINETISK)
  55. static volatile uint8_t *transmit_pin=NULL;
  56. #define transmit_assert() *transmit_pin = 1
  57. #define transmit_deassert() *transmit_pin = 0
  58. static volatile uint8_t *rts_pin=NULL;
  59. #define rts_assert() *rts_pin = 0
  60. #define rts_deassert() *rts_pin = 1
  61. #elif defined(KINETISL)
  62. static volatile uint8_t *transmit_pin=NULL;
  63. static uint8_t transmit_mask=0;
  64. #define transmit_assert() *(transmit_pin+4) = transmit_mask;
  65. #define transmit_deassert() *(transmit_pin+8) = transmit_mask;
  66. static volatile uint8_t *rts_pin=NULL;
  67. static uint8_t rts_mask=0;
  68. #define rts_assert() *(rts_pin+8) = rts_mask;
  69. #define rts_deassert() *(rts_pin+4) = rts_mask;
  70. #endif
  71. #if TX_BUFFER_SIZE > 255
  72. static volatile uint16_t tx_buffer_head = 0;
  73. static volatile uint16_t tx_buffer_tail = 0;
  74. #else
  75. static volatile uint8_t tx_buffer_head = 0;
  76. static volatile uint8_t tx_buffer_tail = 0;
  77. #endif
  78. #if RX_BUFFER_SIZE > 255
  79. static volatile uint16_t rx_buffer_head = 0;
  80. static volatile uint16_t rx_buffer_tail = 0;
  81. #else
  82. static volatile uint8_t rx_buffer_head = 0;
  83. static volatile uint8_t rx_buffer_tail = 0;
  84. #endif
  85. #if defined(KINETISK)
  86. static uint8_t rx_pin_num = 9;
  87. static uint8_t tx_pin_num = 10;
  88. #endif
  89. // UART0 and UART1 are clocked by F_CPU, UART2 is clocked by F_BUS
  90. // UART0 has 8 byte fifo, UART1 and UART2 have 1 byte buffer
  91. #ifdef HAS_KINETISK_UART1_FIFO
  92. #define C2_ENABLE UART_C2_TE | UART_C2_RE | UART_C2_RIE | UART_C2_ILIE
  93. #else
  94. #define C2_ENABLE UART_C2_TE | UART_C2_RE | UART_C2_RIE
  95. #endif
  96. #define C2_TX_ACTIVE C2_ENABLE | UART_C2_TIE
  97. #define C2_TX_COMPLETING C2_ENABLE | UART_C2_TCIE
  98. #define C2_TX_INACTIVE C2_ENABLE
  99. void serial2_begin(uint32_t divisor)
  100. {
  101. SIM_SCGC4 |= SIM_SCGC4_UART1; // turn on clock, TODO: use bitband
  102. rx_buffer_head = 0;
  103. rx_buffer_tail = 0;
  104. tx_buffer_head = 0;
  105. tx_buffer_tail = 0;
  106. transmitting = 0;
  107. #if defined(KINETISK)
  108. switch (rx_pin_num) {
  109. case 9: CORE_PIN9_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
  110. case 26: CORE_PIN26_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
  111. }
  112. switch (tx_pin_num) {
  113. case 10: CORE_PIN10_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
  114. case 31: CORE_PIN31_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
  115. }
  116. #elif defined(KINETISL)
  117. CORE_PIN9_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3);
  118. CORE_PIN10_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3);
  119. #endif
  120. #if defined(HAS_KINETISK_UART1)
  121. UART1_BDH = (divisor >> 13) & 0x1F;
  122. UART1_BDL = (divisor >> 5) & 0xFF;
  123. UART1_C4 = divisor & 0x1F;
  124. #ifdef HAS_KINETISK_UART1_FIFO
  125. UART1_C1 = UART_C1_ILT;
  126. UART1_TWFIFO = 2; // tx watermark, causes S1_TDRE to set
  127. UART1_RWFIFO = 4; // rx watermark, causes S1_RDRF to set
  128. UART1_PFIFO = UART_PFIFO_TXFE | UART_PFIFO_RXFE;
  129. #else
  130. UART1_C1 = 0;
  131. UART1_PFIFO = 0;
  132. #endif
  133. #elif defined(HAS_KINETISL_UART1)
  134. UART1_BDH = (divisor >> 8) & 0x1F;
  135. UART1_BDL = divisor & 0xFF;
  136. UART1_C1 = 0;
  137. #endif
  138. UART1_C2 = C2_TX_INACTIVE;
  139. NVIC_SET_PRIORITY(IRQ_UART1_STATUS, IRQ_PRIORITY);
  140. NVIC_ENABLE_IRQ(IRQ_UART1_STATUS);
  141. }
  142. void serial2_format(uint32_t format)
  143. {
  144. uint8_t c;
  145. c = UART1_C1;
  146. c = (c & ~0x13) | (format & 0x03); // configure parity
  147. if (format & 0x04) c |= 0x10; // 9 bits (might include parity)
  148. UART1_C1 = c;
  149. if ((format & 0x0F) == 0x04) UART1_C3 |= 0x40; // 8N2 is 9 bit with 9th bit always 1
  150. c = UART1_S2 & ~0x10;
  151. if (format & 0x10) c |= 0x10; // rx invert
  152. UART1_S2 = c;
  153. c = UART1_C3 & ~0x10;
  154. if (format & 0x20) c |= 0x10; // tx invert
  155. UART1_C3 = c;
  156. #ifdef SERIAL_9BIT_SUPPORT
  157. c = UART1_C4 & 0x1F;
  158. if (format & 0x08) c |= 0x20; // 9 bit mode with parity (requires 10 bits)
  159. UART1_C4 = c;
  160. use9Bits = format & 0x80;
  161. #endif
  162. // UART1_C1.0 = parity, 0=even, 1=odd
  163. // UART1_C1.1 = parity, 0=disable, 1=enable
  164. // UART1_C1.4 = mode, 1=9bit, 0=8bit
  165. // UART1_C4.5 = mode, 1=10bit, 0=8bit
  166. // UART1_C3.4 = txinv, 0=normal, 1=inverted
  167. // UART1_S2.4 = rxinv, 0=normal, 1=inverted
  168. }
  169. void serial2_end(void)
  170. {
  171. if (!(SIM_SCGC4 & SIM_SCGC4_UART1)) return;
  172. while (transmitting) yield(); // wait for buffered data to send
  173. NVIC_DISABLE_IRQ(IRQ_UART1_STATUS);
  174. UART1_C2 = 0;
  175. CORE_PIN9_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1);
  176. CORE_PIN10_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1);
  177. rx_buffer_head = 0;
  178. rx_buffer_tail = 0;
  179. if (rts_pin) rts_deassert();
  180. }
  181. void serial2_set_transmit_pin(uint8_t pin)
  182. {
  183. while (transmitting) ;
  184. pinMode(pin, OUTPUT);
  185. digitalWrite(pin, LOW);
  186. transmit_pin = portOutputRegister(pin);
  187. #if defined(KINETISL)
  188. transmit_mask = digitalPinToBitMask(pin);
  189. #endif
  190. }
  191. void serial2_set_tx(uint8_t pin, uint8_t opendrain)
  192. {
  193. #if defined(KINETISK)
  194. uint32_t cfg;
  195. if (opendrain) pin |= 128;
  196. if (pin == tx_pin_num) return;
  197. if ((SIM_SCGC4 & SIM_SCGC4_UART1)) {
  198. switch (tx_pin_num & 127) {
  199. case 10: CORE_PIN10_CONFIG = 0; break; // PTC4
  200. #if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.4 or T3.5
  201. case 31: CORE_PIN31_CONFIG = 0; break; // PTE0
  202. #endif
  203. }
  204. if (opendrain) {
  205. cfg = PORT_PCR_DSE | PORT_PCR_ODE;
  206. } else {
  207. cfg = PORT_PCR_DSE | PORT_PCR_SRE;
  208. }
  209. switch (pin & 127) {
  210. case 10: CORE_PIN10_CONFIG = cfg | PORT_PCR_MUX(3); break;
  211. #if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.4 or T3.5
  212. case 31: CORE_PIN31_CONFIG = cfg | PORT_PCR_MUX(3); break;
  213. #endif
  214. }
  215. }
  216. tx_pin_num = pin;
  217. #endif
  218. }
  219. void serial2_set_rx(uint8_t pin)
  220. {
  221. #if defined(KINETISK)
  222. if (pin == rx_pin_num) return;
  223. if ((SIM_SCGC4 & SIM_SCGC4_UART1)) {
  224. switch (rx_pin_num) {
  225. case 9: CORE_PIN9_CONFIG = 0; break; // PTC3
  226. #if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.4 or T3.5
  227. case 26: CORE_PIN26_CONFIG = 0; break; // PTE1
  228. #endif
  229. }
  230. switch (pin) {
  231. case 9: CORE_PIN9_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
  232. #if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.4 or T3.5
  233. case 26: CORE_PIN26_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
  234. #endif
  235. }
  236. }
  237. rx_pin_num = pin;
  238. #endif
  239. }
  240. int serial2_set_rts(uint8_t pin)
  241. {
  242. if (!(SIM_SCGC4 & SIM_SCGC4_UART1)) return 0;
  243. if (pin < CORE_NUM_DIGITAL) {
  244. rts_pin = portOutputRegister(pin);
  245. #if defined(KINETISL)
  246. rts_mask = digitalPinToBitMask(pin);
  247. #endif
  248. pinMode(pin, OUTPUT);
  249. rts_assert();
  250. } else {
  251. rts_pin = NULL;
  252. return 0;
  253. }
  254. /*
  255. if (!(SIM_SCGC4 & SIM_SCGC4_UART1)) return 0;
  256. if (pin == 22) {
  257. CORE_PIN22_CONFIG = PORT_PCR_MUX(3);
  258. } else {
  259. UART1_MODEM &= ~UART_MODEM_RXRTSE;
  260. return 0;
  261. }
  262. UART1_MODEM |= UART_MODEM_RXRTSE;
  263. */
  264. return 1;
  265. }
  266. int serial2_set_cts(uint8_t pin)
  267. {
  268. #if defined(KINETISK)
  269. if (!(SIM_SCGC4 & SIM_SCGC4_UART1)) return 0;
  270. if (pin == 23) {
  271. CORE_PIN23_CONFIG = PORT_PCR_MUX(3) | PORT_PCR_PE; // weak pulldown
  272. } else {
  273. UART1_MODEM &= ~UART_MODEM_TXCTSE;
  274. return 0;
  275. }
  276. UART1_MODEM |= UART_MODEM_TXCTSE;
  277. return 1;
  278. #else
  279. return 0;
  280. #endif
  281. }
  282. void serial2_putchar(uint32_t c)
  283. {
  284. uint32_t head, n;
  285. if (!(SIM_SCGC4 & SIM_SCGC4_UART1)) return;
  286. if (transmit_pin) transmit_assert();
  287. head = tx_buffer_head;
  288. if (++head >= TX_BUFFER_SIZE) head = 0;
  289. while (tx_buffer_tail == head) {
  290. int priority = nvic_execution_priority();
  291. if (priority <= IRQ_PRIORITY) {
  292. if ((UART1_S1 & UART_S1_TDRE)) {
  293. uint32_t tail = tx_buffer_tail;
  294. if (++tail >= TX_BUFFER_SIZE) tail = 0;
  295. n = tx_buffer[tail];
  296. if (use9Bits) UART1_C3 = (UART1_C3 & ~0x40) | ((n & 0x100) >> 2);
  297. UART1_D = n;
  298. tx_buffer_tail = tail;
  299. }
  300. } else if (priority >= 256) {
  301. yield(); // wait
  302. }
  303. }
  304. tx_buffer[head] = c;
  305. transmitting = 1;
  306. tx_buffer_head = head;
  307. UART1_C2 = C2_TX_ACTIVE;
  308. }
  309. #ifdef HAS_KINETISK_UART1_FIFO
  310. void serial2_write(const void *buf, unsigned int count)
  311. {
  312. const uint8_t *p = (const uint8_t *)buf;
  313. const uint8_t *end = p + count;
  314. uint32_t head, n;
  315. if (!(SIM_SCGC4 & SIM_SCGC4_UART1)) return;
  316. if (transmit_pin) transmit_assert();
  317. while (p < end) {
  318. head = tx_buffer_head;
  319. if (++head >= TX_BUFFER_SIZE) head = 0;
  320. if (tx_buffer_tail == head) {
  321. UART1_C2 = C2_TX_ACTIVE;
  322. do {
  323. int priority = nvic_execution_priority();
  324. if (priority <= IRQ_PRIORITY) {
  325. if ((UART1_S1 & UART_S1_TDRE)) {
  326. uint32_t tail = tx_buffer_tail;
  327. if (++tail >= TX_BUFFER_SIZE) tail = 0;
  328. n = tx_buffer[tail];
  329. if (use9Bits) UART1_C3 = (UART1_C3 & ~0x40) | ((n & 0x100) >> 2);
  330. UART1_D = n;
  331. tx_buffer_tail = tail;
  332. }
  333. } else if (priority >= 256) {
  334. yield();
  335. }
  336. } while (tx_buffer_tail == head);
  337. }
  338. tx_buffer[head] = *p++;
  339. transmitting = 1;
  340. tx_buffer_head = head;
  341. }
  342. UART1_C2 = C2_TX_ACTIVE;
  343. }
  344. #else
  345. void serial2_write(const void *buf, unsigned int count)
  346. {
  347. const uint8_t *p = (const uint8_t *)buf;
  348. while (count-- > 0) serial2_putchar(*p++);
  349. }
  350. #endif
  351. void serial2_flush(void)
  352. {
  353. while (transmitting) yield(); // wait
  354. }
  355. int serial2_write_buffer_free(void)
  356. {
  357. uint32_t head, tail;
  358. head = tx_buffer_head;
  359. tail = tx_buffer_tail;
  360. if (head >= tail) return TX_BUFFER_SIZE - 1 - head + tail;
  361. return tail - head - 1;
  362. }
  363. int serial2_available(void)
  364. {
  365. uint32_t head, tail;
  366. head = rx_buffer_head;
  367. tail = rx_buffer_tail;
  368. if (head >= tail) return head - tail;
  369. return RX_BUFFER_SIZE + head - tail;
  370. }
  371. int serial2_getchar(void)
  372. {
  373. uint32_t head, tail;
  374. int c;
  375. head = rx_buffer_head;
  376. tail = rx_buffer_tail;
  377. if (head == tail) return -1;
  378. if (++tail >= RX_BUFFER_SIZE) tail = 0;
  379. c = rx_buffer[tail];
  380. rx_buffer_tail = tail;
  381. if (rts_pin) {
  382. int avail;
  383. if (head >= tail) avail = head - tail;
  384. else avail = RX_BUFFER_SIZE + head - tail;
  385. if (avail <= RTS_LOW_WATERMARK) rts_assert();
  386. }
  387. return c;
  388. }
  389. int serial2_peek(void)
  390. {
  391. uint32_t head, tail;
  392. head = rx_buffer_head;
  393. tail = rx_buffer_tail;
  394. if (head == tail) return -1;
  395. if (++tail >= RX_BUFFER_SIZE) tail = 0;
  396. return rx_buffer[tail];
  397. }
  398. void serial2_clear(void)
  399. {
  400. #ifdef HAS_KINETISK_UART1_FIFO
  401. if (!(SIM_SCGC4 & SIM_SCGC4_UART1)) return;
  402. UART1_C2 &= ~(UART_C2_RE | UART_C2_RIE | UART_C2_ILIE);
  403. UART1_CFIFO = UART_CFIFO_RXFLUSH;
  404. UART1_C2 |= (UART_C2_RE | UART_C2_RIE | UART_C2_ILIE);
  405. #endif
  406. rx_buffer_head = rx_buffer_tail;
  407. if (rts_pin) rts_assert();
  408. }
  409. // status interrupt combines
  410. // Transmit data below watermark UART_S1_TDRE
  411. // Transmit complete UART_S1_TC
  412. // Idle line UART_S1_IDLE
  413. // Receive data above watermark UART_S1_RDRF
  414. // LIN break detect UART_S2_LBKDIF
  415. // RxD pin active edge UART_S2_RXEDGIF
  416. void uart1_status_isr(void)
  417. {
  418. uint32_t head, tail, n;
  419. uint8_t c;
  420. #ifdef HAS_KINETISK_UART1_FIFO
  421. uint32_t newhead;
  422. uint8_t avail;
  423. if (UART1_S1 & (UART_S1_RDRF | UART_S1_IDLE)) {
  424. __disable_irq();
  425. avail = UART1_RCFIFO;
  426. if (avail == 0) {
  427. // The only way to clear the IDLE interrupt flag is
  428. // to read the data register. But reading with no
  429. // data causes a FIFO underrun, which causes the
  430. // FIFO to return corrupted data. If anyone from
  431. // Freescale reads this, what a poor design! There
  432. // write should be a write-1-to-clear for IDLE.
  433. c = UART1_D;
  434. // flushing the fifo recovers from the underrun,
  435. // but there's a possible race condition where a
  436. // new character could be received between reading
  437. // RCFIFO == 0 and flushing the FIFO. To minimize
  438. // the chance, interrupts are disabled so a higher
  439. // priority interrupt (hopefully) doesn't delay.
  440. // TODO: change this to disabling the IDLE interrupt
  441. // which won't be simple, since we already manage
  442. // which transmit interrupts are enabled.
  443. UART1_CFIFO = UART_CFIFO_RXFLUSH;
  444. __enable_irq();
  445. } else {
  446. __enable_irq();
  447. head = rx_buffer_head;
  448. tail = rx_buffer_tail;
  449. do {
  450. if (use9Bits && (UART1_C3 & 0x80)) {
  451. n = UART1_D | 0x100;
  452. } else {
  453. n = UART1_D;
  454. }
  455. newhead = head + 1;
  456. if (newhead >= RX_BUFFER_SIZE) newhead = 0;
  457. if (newhead != tail) {
  458. head = newhead;
  459. rx_buffer[head] = n;
  460. }
  461. } while (--avail > 0);
  462. rx_buffer_head = head;
  463. if (rts_pin) {
  464. int avail;
  465. if (head >= tail) avail = head - tail;
  466. else avail = RX_BUFFER_SIZE + head - tail;
  467. if (avail >= RTS_HIGH_WATERMARK) rts_deassert();
  468. }
  469. }
  470. }
  471. c = UART1_C2;
  472. if ((c & UART_C2_TIE) && (UART1_S1 & UART_S1_TDRE)) {
  473. head = tx_buffer_head;
  474. tail = tx_buffer_tail;
  475. do {
  476. if (tail == head) break;
  477. if (++tail >= TX_BUFFER_SIZE) tail = 0;
  478. avail = UART1_S1;
  479. n = tx_buffer[tail];
  480. if (use9Bits) UART1_C3 = (UART1_C3 & ~0x40) | ((n & 0x100) >> 2);
  481. UART1_D = n;
  482. } while (UART1_TCFIFO < 8);
  483. tx_buffer_tail = tail;
  484. if (UART1_S1 & UART_S1_TDRE) UART1_C2 = C2_TX_COMPLETING;
  485. }
  486. #else
  487. if (UART1_S1 & UART_S1_RDRF) {
  488. n = UART1_D;
  489. if (use9Bits && (UART1_C3 & 0x80)) n |= 0x100;
  490. head = rx_buffer_head + 1;
  491. if (head >= RX_BUFFER_SIZE) head = 0;
  492. if (head != rx_buffer_tail) {
  493. rx_buffer[head] = n;
  494. rx_buffer_head = head;
  495. }
  496. }
  497. c = UART1_C2;
  498. if ((c & UART_C2_TIE) && (UART1_S1 & UART_S1_TDRE)) {
  499. head = tx_buffer_head;
  500. tail = tx_buffer_tail;
  501. if (head == tail) {
  502. UART1_C2 = C2_TX_COMPLETING;
  503. } else {
  504. if (++tail >= TX_BUFFER_SIZE) tail = 0;
  505. n = tx_buffer[tail];
  506. if (use9Bits) UART1_C3 = (UART1_C3 & ~0x40) | ((n & 0x100) >> 2);
  507. UART1_D = n;
  508. tx_buffer_tail = tail;
  509. }
  510. }
  511. #endif
  512. if ((c & UART_C2_TCIE) && (UART1_S1 & UART_S1_TC)) {
  513. transmitting = 0;
  514. if (transmit_pin) transmit_deassert();
  515. UART1_C2 = C2_TX_INACTIVE;
  516. }
  517. }