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Teensy 4.1 core updated for C++20
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teensy-core-4.1/teensy4/core_pins.h

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  1. /* Teensyduino Core Library

  2.  * http://www.pjrc.com/teensy/

  3.  * Copyright (c) 2018 PJRC.COM, LLC.

  4.  *

  5.  * Permission is hereby granted, free of charge, to any person obtaining

  6.  * a copy of this software and associated documentation files (the

  7.  * "Software"), to deal in the Software without restriction, including

  8.  * without limitation the rights to use, copy, modify, merge, publish,

  9.  * distribute, sublicense, and/or sell copies of the Software, and to

  10.  * permit persons to whom the Software is furnished to do so, subject to

  11.  * the following conditions:

  12.  *

  13.  * 1. The above copyright notice and this permission notice shall be

  14.  * included in all copies or substantial portions of the Software.

  15.  *

  16.  * 2. If the Software is incorporated into a build system that allows

  17.  * selection among a list of target devices, then similar target

  18.  * devices manufactured by PJRC.COM must be included in the list of

  19.  * target devices and selectable in the same manner.

  20.  *

  21.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

  22.  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

  23.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

  24.  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS

  25.  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN

  26.  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

  27.  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

  28.  * SOFTWARE.

  29.  */

  30. 

  31. #pragma once

  32. #include "imxrt.h"

  33. #include "pins_arduino.h"

  34. 

  35. #define HIGH			1

  36. #define LOW			0

  37. #define INPUT			0

  38. #define OUTPUT			1

  39. #define INPUT_PULLUP		2

  40. #define INPUT_PULLDOWN		3

  41. #define OUTPUT_OPENDRAIN	4

  42. #define INPUT_DISABLE		5

  43. #define LSBFIRST		0

  44. #define MSBFIRST		1

  45. #define _BV(n)			(1<<(n))

  46. #define CHANGE			4

  47. #define FALLING			2

  48. #define RISING			3

  49. 

  50. 

  51. #if defined(__IMXRT1062__)

  52. 

  53. #define CORE_NUM_TOTAL_PINS	40

  54. #define CORE_NUM_DIGITAL	40

  55. #define CORE_NUM_INTERRUPT	40

  56. #define CORE_NUM_ANALOG		14

  57. #define CORE_NUM_PWM		27

  58. 

  59. #define CORE_PIN0_BIT		3

  60. #define CORE_PIN1_BIT		2

  61. #define CORE_PIN2_BIT		4

  62. #define CORE_PIN3_BIT		5

  63. #define CORE_PIN4_BIT		6

  64. #define CORE_PIN5_BIT		8

  65. #define CORE_PIN6_BIT		10

  66. #define CORE_PIN7_BIT		17

  67. #define CORE_PIN8_BIT		16

  68. #define CORE_PIN9_BIT		11

  69. #define CORE_PIN10_BIT		0

  70. #define CORE_PIN11_BIT		2

  71. #define CORE_PIN12_BIT		1

  72. #define CORE_PIN13_BIT		3

  73. #define CORE_PIN14_BIT		18

  74. #define CORE_PIN15_BIT		19

  75. #define CORE_PIN16_BIT		23

  76. #define CORE_PIN17_BIT		22

  77. #define CORE_PIN18_BIT		17

  78. #define CORE_PIN19_BIT		16

  79. #define CORE_PIN20_BIT		26

  80. #define CORE_PIN21_BIT		27

  81. #define CORE_PIN22_BIT		24

  82. #define CORE_PIN23_BIT		25

  83. #define CORE_PIN24_BIT		12

  84. #define CORE_PIN25_BIT		13

  85. #define CORE_PIN26_BIT		30

  86. #define CORE_PIN27_BIT		31

  87. #define CORE_PIN28_BIT		18

  88. #define CORE_PIN29_BIT		31

  89. #define CORE_PIN30_BIT		24

  90. #define CORE_PIN31_BIT		23

  91. #define CORE_PIN32_BIT		12

  92. #define CORE_PIN33_BIT		7

  93. #define CORE_PIN34_BIT		15

  94. #define CORE_PIN35_BIT		14

  95. #define CORE_PIN36_BIT		13

  96. #define CORE_PIN37_BIT		12

  97. #define CORE_PIN38_BIT		17

  98. #define CORE_PIN39_BIT		16

  99. 

  100. #define CORE_PIN0_BITMASK	(1<<(CORE_PIN0_BIT))

  101. #define CORE_PIN1_BITMASK	(1<<(CORE_PIN1_BIT))

  102. #define CORE_PIN2_BITMASK	(1<<(CORE_PIN2_BIT))

  103. #define CORE_PIN3_BITMASK	(1<<(CORE_PIN3_BIT))

  104. #define CORE_PIN4_BITMASK	(1<<(CORE_PIN4_BIT))

  105. #define CORE_PIN5_BITMASK	(1<<(CORE_PIN5_BIT))

  106. #define CORE_PIN6_BITMASK	(1<<(CORE_PIN6_BIT))

  107. #define CORE_PIN7_BITMASK	(1<<(CORE_PIN7_BIT))

  108. #define CORE_PIN8_BITMASK	(1<<(CORE_PIN8_BIT))

  109. #define CORE_PIN9_BITMASK	(1<<(CORE_PIN9_BIT))

  110. #define CORE_PIN10_BITMASK	(1<<(CORE_PIN10_BIT))

  111. #define CORE_PIN11_BITMASK	(1<<(CORE_PIN11_BIT))

  112. #define CORE_PIN12_BITMASK	(1<<(CORE_PIN12_BIT))

  113. #define CORE_PIN13_BITMASK	(1<<(CORE_PIN13_BIT))

  114. #define CORE_PIN14_BITMASK	(1<<(CORE_PIN14_BIT))

  115. #define CORE_PIN15_BITMASK	(1<<(CORE_PIN15_BIT))

  116. #define CORE_PIN16_BITMASK	(1<<(CORE_PIN16_BIT))

  117. #define CORE_PIN17_BITMASK	(1<<(CORE_PIN17_BIT))

  118. #define CORE_PIN18_BITMASK	(1<<(CORE_PIN18_BIT))

  119. #define CORE_PIN19_BITMASK	(1<<(CORE_PIN19_BIT))

  120. #define CORE_PIN20_BITMASK	(1<<(CORE_PIN20_BIT))

  121. #define CORE_PIN21_BITMASK	(1<<(CORE_PIN21_BIT))

  122. #define CORE_PIN22_BITMASK	(1<<(CORE_PIN22_BIT))

  123. #define CORE_PIN23_BITMASK	(1<<(CORE_PIN23_BIT))

  124. #define CORE_PIN24_BITMASK	(1<<(CORE_PIN24_BIT))

  125. #define CORE_PIN25_BITMASK	(1<<(CORE_PIN25_BIT))

  126. #define CORE_PIN26_BITMASK	(1<<(CORE_PIN26_BIT))

  127. #define CORE_PIN27_BITMASK	(1<<(CORE_PIN27_BIT))

  128. #define CORE_PIN28_BITMASK	(1<<(CORE_PIN28_BIT))

  129. #define CORE_PIN29_BITMASK	(1<<(CORE_PIN29_BIT))

  130. #define CORE_PIN30_BITMASK	(1<<(CORE_PIN30_BIT))

  131. #define CORE_PIN31_BITMASK	(1<<(CORE_PIN31_BIT))

  132. #define CORE_PIN32_BITMASK	(1<<(CORE_PIN32_BIT))

  133. #define CORE_PIN33_BITMASK	(1<<(CORE_PIN33_BIT))

  134. #define CORE_PIN34_BITMASK	(1<<(CORE_PIN34_BIT))

  135. #define CORE_PIN35_BITMASK	(1<<(CORE_PIN35_BIT))

  136. #define CORE_PIN36_BITMASK	(1<<(CORE_PIN36_BIT))

  137. #define CORE_PIN37_BITMASK	(1<<(CORE_PIN37_BIT))

  138. #define CORE_PIN38_BITMASK	(1<<(CORE_PIN38_BIT))

  139. #define CORE_PIN39_BITMASK	(1<<(CORE_PIN39_BIT))

  140. 

  141. #define CORE_PIN0_PORTREG	GPIO1_DR

  142. #define CORE_PIN1_PORTREG	GPIO1_DR

  143. #define CORE_PIN2_PORTREG	GPIO4_DR

  144. #define CORE_PIN3_PORTREG	GPIO4_DR

  145. #define CORE_PIN4_PORTREG	GPIO4_DR

  146. #define CORE_PIN5_PORTREG	GPIO4_DR

  147. #define CORE_PIN6_PORTREG	GPIO2_DR

  148. #define CORE_PIN7_PORTREG	GPIO2_DR

  149. #define CORE_PIN8_PORTREG	GPIO2_DR

  150. #define CORE_PIN9_PORTREG	GPIO2_DR

  151. #define CORE_PIN10_PORTREG	GPIO2_DR

  152. #define CORE_PIN11_PORTREG	GPIO2_DR

  153. #define CORE_PIN12_PORTREG	GPIO2_DR

  154. #define CORE_PIN13_PORTREG	GPIO2_DR

  155. #define CORE_PIN14_PORTREG	GPIO1_DR

  156. #define CORE_PIN15_PORTREG	GPIO1_DR

  157. #define CORE_PIN16_PORTREG	GPIO1_DR

  158. #define CORE_PIN17_PORTREG	GPIO1_DR

  159. #define CORE_PIN18_PORTREG	GPIO1_DR

  160. #define CORE_PIN19_PORTREG	GPIO1_DR

  161. #define CORE_PIN20_PORTREG	GPIO1_DR

  162. #define CORE_PIN21_PORTREG	GPIO1_DR

  163. #define CORE_PIN22_PORTREG	GPIO1_DR

  164. #define CORE_PIN23_PORTREG	GPIO1_DR

  165. #define CORE_PIN24_PORTREG	GPIO1_DR

  166. #define CORE_PIN25_PORTREG	GPIO1_DR

  167. #define CORE_PIN26_PORTREG	GPIO1_DR

  168. #define CORE_PIN27_PORTREG	GPIO1_DR

  169. #define CORE_PIN28_PORTREG	GPIO3_DR

  170. #define CORE_PIN29_PORTREG	GPIO4_DR

  171. #define CORE_PIN30_PORTREG	GPIO4_DR

  172. #define CORE_PIN31_PORTREG	GPIO4_DR

  173. #define CORE_PIN32_PORTREG	GPIO2_DR

  174. #define CORE_PIN33_PORTREG	GPIO4_DR

  175. #define CORE_PIN34_PORTREG	GPIO3_DR

  176. #define CORE_PIN35_PORTREG	GPIO3_DR

  177. #define CORE_PIN36_PORTREG	GPIO3_DR

  178. #define CORE_PIN37_PORTREG	GPIO3_DR

  179. #define CORE_PIN38_PORTREG	GPIO3_DR

  180. #define CORE_PIN39_PORTREG	GPIO3_DR

  181. 

  182. #define CORE_PIN0_PORTSET	GPIO1_DR_SET

  183. #define CORE_PIN1_PORTSET	GPIO1_DR_SET

  184. #define CORE_PIN2_PORTSET	GPIO4_DR_SET

  185. #define CORE_PIN3_PORTSET	GPIO4_DR_SET

  186. #define CORE_PIN4_PORTSET	GPIO4_DR_SET

  187. #define CORE_PIN5_PORTSET	GPIO4_DR_SET

  188. #define CORE_PIN6_PORTSET	GPIO2_DR_SET

  189. #define CORE_PIN7_PORTSET	GPIO2_DR_SET

  190. #define CORE_PIN8_PORTSET	GPIO2_DR_SET

  191. #define CORE_PIN9_PORTSET	GPIO2_DR_SET

  192. #define CORE_PIN10_PORTSET	GPIO2_DR_SET

  193. #define CORE_PIN11_PORTSET	GPIO2_DR_SET

  194. #define CORE_PIN12_PORTSET	GPIO2_DR_SET

  195. #define CORE_PIN13_PORTSET	GPIO2_DR_SET

  196. #define CORE_PIN14_PORTSET	GPIO1_DR_SET

  197. #define CORE_PIN15_PORTSET	GPIO1_DR_SET

  198. #define CORE_PIN16_PORTSET	GPIO1_DR_SET

  199. #define CORE_PIN17_PORTSET	GPIO1_DR_SET

  200. #define CORE_PIN18_PORTSET	GPIO1_DR_SET

  201. #define CORE_PIN19_PORTSET	GPIO1_DR_SET

  202. #define CORE_PIN20_PORTSET	GPIO1_DR_SET

  203. #define CORE_PIN21_PORTSET	GPIO1_DR_SET

  204. #define CORE_PIN22_PORTSET	GPIO1_DR_SET

  205. #define CORE_PIN23_PORTSET	GPIO1_DR_SET

  206. #define CORE_PIN24_PORTSET	GPIO1_DR_SET

  207. #define CORE_PIN25_PORTSET	GPIO1_DR_SET

  208. #define CORE_PIN26_PORTSET	GPIO1_DR_SET

  209. #define CORE_PIN27_PORTSET	GPIO1_DR_SET

  210. #define CORE_PIN28_PORTSET	GPIO3_DR_SET

  211. #define CORE_PIN29_PORTSET	GPIO4_DR_SET

  212. #define CORE_PIN30_PORTSET	GPIO4_DR_SET

  213. #define CORE_PIN31_PORTSET	GPIO4_DR_SET

  214. #define CORE_PIN32_PORTSET	GPIO2_DR_SET

  215. #define CORE_PIN33_PORTSET	GPIO4_DR_SET

  216. #define CORE_PIN34_PORTSET	GPIO3_DR_SET

  217. #define CORE_PIN35_PORTSET	GPIO3_DR_SET

  218. #define CORE_PIN36_PORTSET	GPIO3_DR_SET

  219. #define CORE_PIN37_PORTSET	GPIO3_DR_SET

  220. #define CORE_PIN38_PORTSET	GPIO3_DR_SET

  221. #define CORE_PIN39_PORTSET	GPIO3_DR_SET

  222. 

  223. #define CORE_PIN0_PORTCLEAR	GPIO1_DR_CLEAR

  224. #define CORE_PIN1_PORTCLEAR	GPIO1_DR_CLEAR

  225. #define CORE_PIN2_PORTCLEAR	GPIO4_DR_CLEAR

  226. #define CORE_PIN3_PORTCLEAR	GPIO4_DR_CLEAR

  227. #define CORE_PIN4_PORTCLEAR	GPIO4_DR_CLEAR

  228. #define CORE_PIN5_PORTCLEAR	GPIO4_DR_CLEAR

  229. #define CORE_PIN6_PORTCLEAR	GPIO2_DR_CLEAR

  230. #define CORE_PIN7_PORTCLEAR	GPIO2_DR_CLEAR

  231. #define CORE_PIN8_PORTCLEAR	GPIO2_DR_CLEAR

  232. #define CORE_PIN9_PORTCLEAR	GPIO2_DR_CLEAR

  233. #define CORE_PIN10_PORTCLEAR	GPIO2_DR_CLEAR

  234. #define CORE_PIN11_PORTCLEAR	GPIO2_DR_CLEAR

  235. #define CORE_PIN12_PORTCLEAR	GPIO2_DR_CLEAR

  236. #define CORE_PIN13_PORTCLEAR	GPIO2_DR_CLEAR

  237. #define CORE_PIN14_PORTCLEAR	GPIO1_DR_CLEAR

  238. #define CORE_PIN15_PORTCLEAR	GPIO1_DR_CLEAR

  239. #define CORE_PIN16_PORTCLEAR	GPIO1_DR_CLEAR

  240. #define CORE_PIN17_PORTCLEAR	GPIO1_DR_CLEAR

  241. #define CORE_PIN18_PORTCLEAR	GPIO1_DR_CLEAR

  242. #define CORE_PIN19_PORTCLEAR	GPIO1_DR_CLEAR

  243. #define CORE_PIN20_PORTCLEAR	GPIO1_DR_CLEAR

  244. #define CORE_PIN21_PORTCLEAR	GPIO1_DR_CLEAR

  245. #define CORE_PIN22_PORTCLEAR	GPIO1_DR_CLEAR

  246. #define CORE_PIN23_PORTCLEAR	GPIO1_DR_CLEAR

  247. #define CORE_PIN24_PORTCLEAR	GPIO1_DR_CLEAR

  248. #define CORE_PIN25_PORTCLEAR	GPIO1_DR_CLEAR

  249. #define CORE_PIN26_PORTCLEAR	GPIO1_DR_CLEAR

  250. #define CORE_PIN27_PORTCLEAR	GPIO1_DR_CLEAR

  251. #define CORE_PIN28_PORTCLEAR	GPIO3_DR_CLEAR

  252. #define CORE_PIN29_PORTCLEAR	GPIO4_DR_CLEAR

  253. #define CORE_PIN30_PORTCLEAR	GPIO4_DR_CLEAR

  254. #define CORE_PIN31_PORTCLEAR	GPIO4_DR_CLEAR

  255. #define CORE_PIN32_PORTCLEAR	GPIO2_DR_CLEAR

  256. #define CORE_PIN33_PORTCLEAR	GPIO4_DR_CLEAR

  257. #define CORE_PIN34_PORTCLEAR	GPIO3_DR_CLEAR

  258. #define CORE_PIN35_PORTCLEAR	GPIO3_DR_CLEAR

  259. #define CORE_PIN36_PORTCLEAR	GPIO3_DR_CLEAR

  260. #define CORE_PIN37_PORTCLEAR	GPIO3_DR_CLEAR

  261. #define CORE_PIN38_PORTCLEAR	GPIO3_DR_CLEAR

  262. #define CORE_PIN39_PORTCLEAR	GPIO3_DR_CLEAR

  263. 

  264. #define CORE_PIN0_DDRREG	GPIO1_GDIR

  265. #define CORE_PIN1_DDRREG	GPIO1_GDIR

  266. #define CORE_PIN2_DDRREG	GPIO4_GDIR

  267. #define CORE_PIN3_DDRREG	GPIO4_GDIR

  268. #define CORE_PIN4_DDRREG	GPIO4_GDIR

  269. #define CORE_PIN5_DDRREG	GPIO4_GDIR

  270. #define CORE_PIN6_DDRREG	GPIO2_GDIR

  271. #define CORE_PIN7_DDRREG	GPIO2_GDIR

  272. #define CORE_PIN8_DDRREG	GPIO2_GDIR

  273. #define CORE_PIN9_DDRREG	GPIO2_GDIR

  274. #define CORE_PIN10_DDRREG	GPIO2_GDIR

  275. #define CORE_PIN11_DDRREG	GPIO2_GDIR

  276. #define CORE_PIN12_DDRREG	GPIO2_GDIR

  277. #define CORE_PIN13_DDRREG	GPIO2_GDIR

  278. #define CORE_PIN14_DDRREG	GPIO1_GDIR

  279. #define CORE_PIN15_DDRREG	GPIO1_GDIR

  280. #define CORE_PIN16_DDRREG	GPIO1_GDIR

  281. #define CORE_PIN17_DDRREG	GPIO1_GDIR

  282. #define CORE_PIN18_DDRREG	GPIO1_GDIR

  283. #define CORE_PIN19_DDRREG	GPIO1_GDIR

  284. #define CORE_PIN20_DDRREG	GPIO1_GDIR

  285. #define CORE_PIN21_DDRREG	GPIO1_GDIR

  286. #define CORE_PIN22_DDRREG	GPIO1_GDIR

  287. #define CORE_PIN23_DDRREG	GPIO1_GDIR

  288. #define CORE_PIN24_DDRREG	GPIO1_GDIR

  289. #define CORE_PIN25_DDRREG	GPIO1_GDIR

  290. #define CORE_PIN26_DDRREG	GPIO1_GDIR

  291. #define CORE_PIN27_DDRREG	GPIO1_GDIR

  292. #define CORE_PIN28_DDRREG	GPIO3_GDIR

  293. #define CORE_PIN29_DDRREG	GPIO4_GDIR

  294. #define CORE_PIN30_DDRREG	GPIO4_GDIR

  295. #define CORE_PIN31_DDRREG	GPIO4_GDIR

  296. #define CORE_PIN32_DDRREG	GPIO2_GDIR

  297. #define CORE_PIN33_DDRREG	GPIO4_GDIR

  298. #define CORE_PIN34_DDRREG	GPIO3_GDIR

  299. #define CORE_PIN35_DDRREG	GPIO3_GDIR

  300. #define CORE_PIN36_DDRREG	GPIO3_GDIR

  301. #define CORE_PIN37_DDRREG	GPIO3_GDIR

  302. #define CORE_PIN38_DDRREG	GPIO3_GDIR

  303. #define CORE_PIN39_DDRREG	GPIO3_GDIR

  304. 

  305. #define CORE_PIN0_PINREG	GPIO1_PSR

  306. #define CORE_PIN1_PINREG	GPIO1_PSR

  307. #define CORE_PIN2_PINREG	GPIO4_PSR

  308. #define CORE_PIN3_PINREG	GPIO4_PSR

  309. #define CORE_PIN4_PINREG	GPIO4_PSR

  310. #define CORE_PIN5_PINREG	GPIO4_PSR

  311. #define CORE_PIN6_PINREG	GPIO2_PSR

  312. #define CORE_PIN7_PINREG	GPIO2_PSR

  313. #define CORE_PIN8_PINREG	GPIO2_PSR

  314. #define CORE_PIN9_PINREG	GPIO2_PSR

  315. #define CORE_PIN10_PINREG	GPIO2_PSR

  316. #define CORE_PIN11_PINREG	GPIO2_PSR

  317. #define CORE_PIN12_PINREG	GPIO2_PSR

  318. #define CORE_PIN13_PINREG	GPIO2_PSR

  319. #define CORE_PIN14_PINREG	GPIO1_PSR

  320. #define CORE_PIN15_PINREG	GPIO1_PSR

  321. #define CORE_PIN16_PINREG	GPIO1_PSR

  322. #define CORE_PIN17_PINREG	GPIO1_PSR

  323. #define CORE_PIN18_PINREG	GPIO1_PSR

  324. #define CORE_PIN19_PINREG	GPIO1_PSR

  325. #define CORE_PIN20_PINREG	GPIO1_PSR

  326. #define CORE_PIN21_PINREG	GPIO1_PSR

  327. #define CORE_PIN22_PINREG	GPIO1_PSR

  328. #define CORE_PIN23_PINREG	GPIO1_PSR

  329. #define CORE_PIN24_PINREG	GPIO1_PSR

  330. #define CORE_PIN25_PINREG	GPIO1_PSR

  331. #define CORE_PIN26_PINREG	GPIO1_PSR

  332. #define CORE_PIN27_PINREG	GPIO1_PSR

  333. #define CORE_PIN28_PINREG	GPIO3_PSR

  334. #define CORE_PIN29_PINREG	GPIO4_PSR

  335. #define CORE_PIN30_PINREG	GPIO4_PSR

  336. #define CORE_PIN31_PINREG	GPIO4_PSR

  337. #define CORE_PIN32_PINREG	GPIO2_PSR

  338. #define CORE_PIN33_PINREG	GPIO4_PSR

  339. #define CORE_PIN34_PINREG	GPIO3_PSR

  340. #define CORE_PIN35_PINREG	GPIO3_PSR

  341. #define CORE_PIN36_PINREG	GPIO3_PSR

  342. #define CORE_PIN37_PINREG	GPIO3_PSR

  343. #define CORE_PIN38_PINREG	GPIO3_PSR

  344. #define CORE_PIN39_PINREG	GPIO3_PSR

  345. 

  346. // mux config registers control which peripheral uses the pin

  347. #define CORE_PIN0_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03

  348. #define CORE_PIN1_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02

  349. #define CORE_PIN2_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04

  350. #define CORE_PIN3_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05

  351. #define CORE_PIN4_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06

  352. #define CORE_PIN5_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08

  353. #define CORE_PIN6_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10

  354. #define CORE_PIN7_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01

  355. #define CORE_PIN8_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00

  356. #define CORE_PIN9_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11

  357. #define CORE_PIN10_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00

  358. #define CORE_PIN11_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02

  359. #define CORE_PIN12_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01

  360. #define CORE_PIN13_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03

  361. #define CORE_PIN14_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02

  362. #define CORE_PIN15_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03

  363. #define CORE_PIN16_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07

  364. #define CORE_PIN17_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06

  365. #define CORE_PIN18_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01

  366. #define CORE_PIN19_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00

  367. #define CORE_PIN20_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10

  368. #define CORE_PIN21_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11

  369. #define CORE_PIN22_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08

  370. #define CORE_PIN23_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09

  371. #define CORE_PIN24_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12

  372. #define CORE_PIN25_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13

  373. #define CORE_PIN26_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14

  374. #define CORE_PIN27_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15

  375. #define CORE_PIN28_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32

  376. #define CORE_PIN29_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31

  377. #define CORE_PIN30_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24

  378. #define CORE_PIN31_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23

  379. #define CORE_PIN32_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12

  380. #define CORE_PIN33_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07

  381. #define CORE_PIN34_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03

  382. #define CORE_PIN35_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02

  383. #define CORE_PIN36_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01

  384. #define CORE_PIN37_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00

  385. #define CORE_PIN38_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05

  386. #define CORE_PIN39_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04

  387. 

  388. // pad config registers control pullup/pulldown/keeper, drive strength, etc

  389. #define CORE_PIN0_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03

  390. #define CORE_PIN1_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02

  391. #define CORE_PIN2_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04

  392. #define CORE_PIN3_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05

  393. #define CORE_PIN4_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06

  394. #define CORE_PIN5_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08

  395. #define CORE_PIN6_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10

  396. #define CORE_PIN7_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01

  397. #define CORE_PIN8_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00

  398. #define CORE_PIN9_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11

  399. #define CORE_PIN10_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00

  400. #define CORE_PIN11_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02

  401. #define CORE_PIN12_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01

  402. #define CORE_PIN13_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03

  403. #define CORE_PIN14_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02

  404. #define CORE_PIN15_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03

  405. #define CORE_PIN16_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07

  406. #define CORE_PIN17_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06

  407. #define CORE_PIN18_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01

  408. #define CORE_PIN19_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00

  409. #define CORE_PIN20_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10

  410. #define CORE_PIN21_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11

  411. #define CORE_PIN22_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08

  412. #define CORE_PIN23_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09

  413. #define CORE_PIN24_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12

  414. #define CORE_PIN25_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13

  415. #define CORE_PIN26_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14

  416. #define CORE_PIN27_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15

  417. #define CORE_PIN28_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32

  418. #define CORE_PIN29_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31

  419. #define CORE_PIN30_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24

  420. #define CORE_PIN31_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23

  421. #define CORE_PIN32_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12

  422. #define CORE_PIN33_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07

  423. #define CORE_PIN34_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03

  424. #define CORE_PIN35_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02

  425. #define CORE_PIN36_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01

  426. #define CORE_PIN37_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00

  427. #define CORE_PIN38_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05

  428. #define CORE_PIN39_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04

  429. 

  430. #define CORE_LED0_PIN		13

  431. 

  432. #define CORE_ADC0_PIN		14

  433. #define CORE_ADC1_PIN		15

  434. #define CORE_ADC2_PIN		16

  435. #define CORE_ADC3_PIN		17

  436. #define CORE_ADC4_PIN		18

  437. #define CORE_ADC5_PIN		19

  438. #define CORE_ADC6_PIN		20

  439. #define CORE_ADC7_PIN		21

  440. #define CORE_ADC8_PIN		22

  441. #define CORE_ADC9_PIN		23

  442. 

  443. #define CORE_RXD0_PIN		0

  444. #define CORE_TXD0_PIN		1

  445. #define CORE_RXD1_PIN		7

  446. #define CORE_TXD1_PIN		8

  447. #define CORE_RXD2_PIN		15

  448. #define CORE_TXD2_PIN		14

  449. #define CORE_RXD3_PIN		16

  450. #define CORE_TXD3_PIN		17

  451. #define CORE_RXD4_PIN		21

  452. #define CORE_TXD4_PIN		20

  453. #define CORE_RXD5_PIN		25

  454. #define CORE_TXD5_PIN		24

  455. #define CORE_RXD6_PIN		28

  456. #define CORE_TXD6_PIN		29

  457. 

  458. #define CORE_INT0_PIN		0

  459. #define CORE_INT1_PIN		1

  460. #define CORE_INT2_PIN		2

  461. #define CORE_INT3_PIN		3

  462. #define CORE_INT4_PIN		4

  463. #define CORE_INT5_PIN		5

  464. #define CORE_INT6_PIN		6

  465. #define CORE_INT7_PIN		7

  466. #define CORE_INT8_PIN		8

  467. #define CORE_INT9_PIN		9

  468. #define CORE_INT10_PIN		10

  469. #define CORE_INT11_PIN		11

  470. #define CORE_INT12_PIN		12

  471. #define CORE_INT13_PIN		13

  472. #define CORE_INT14_PIN		14

  473. #define CORE_INT15_PIN		15

  474. #define CORE_INT16_PIN		16

  475. #define CORE_INT17_PIN		17

  476. #define CORE_INT18_PIN		18

  477. #define CORE_INT19_PIN		19

  478. #define CORE_INT20_PIN		20

  479. #define CORE_INT21_PIN		21

  480. #define CORE_INT22_PIN		22

  481. #define CORE_INT23_PIN		23

  482. #define CORE_INT24_PIN		24

  483. #define CORE_INT25_PIN		25

  484. #define CORE_INT26_PIN		26

  485. #define CORE_INT27_PIN		27

  486. #define CORE_INT28_PIN		28

  487. #define CORE_INT29_PIN		29

  488. #define CORE_INT30_PIN		30

  489. #define CORE_INT31_PIN		31

  490. #define CORE_INT32_PIN		32

  491. #define CORE_INT33_PIN		33

  492. #define CORE_INT34_PIN		34

  493. #define CORE_INT35_PIN		35

  494. #define CORE_INT36_PIN		36

  495. #define CORE_INT37_PIN		37

  496. #define CORE_INT38_PIN		38

  497. #define CORE_INT39_PIN		39

  498. #define CORE_INT_EVERY_PIN	1

  499. 

  500. 

  501. #elif defined(__IMXRT1052__)

  502. 

  503. #define CORE_NUM_TOTAL_PINS	34

  504. #define CORE_NUM_DIGITAL	34

  505. #define CORE_NUM_INTERRUPT	34

  506. #define CORE_NUM_ANALOG		14

  507. #define CORE_NUM_PWM		27

  508. 

  509. #define CORE_PIN0_BIT		3

  510. #define CORE_PIN1_BIT		2

  511. #define CORE_PIN2_BIT		4

  512. #define CORE_PIN3_BIT		5

  513. #define CORE_PIN4_BIT		6

  514. #define CORE_PIN5_BIT		7

  515. #define CORE_PIN6_BIT		17

  516. #define CORE_PIN7_BIT		16

  517. #define CORE_PIN8_BIT		10

  518. #define CORE_PIN9_BIT		11

  519. #define CORE_PIN10_BIT		0

  520. #define CORE_PIN11_BIT		2

  521. #define CORE_PIN12_BIT		1

  522. #define CORE_PIN13_BIT		3

  523. #define CORE_PIN14_BIT		18

  524. #define CORE_PIN15_BIT		19

  525. #define CORE_PIN16_BIT		23

  526. #define CORE_PIN17_BIT		22

  527. #define CORE_PIN18_BIT		17

  528. #define CORE_PIN19_BIT		16

  529. #define CORE_PIN20_BIT		26

  530. #define CORE_PIN21_BIT		27

  531. #define CORE_PIN22_BIT		24

  532. #define CORE_PIN23_BIT		25

  533. #define CORE_PIN24_BIT		12

  534. #define CORE_PIN25_BIT		13

  535. #define CORE_PIN26_BIT		30

  536. #define CORE_PIN27_BIT		31

  537. #define CORE_PIN28_BIT		18

  538. #define CORE_PIN29_BIT		31

  539. #define CORE_PIN30_BIT		24

  540. #define CORE_PIN31_BIT		23

  541. #define CORE_PIN32_BIT		12

  542. #define CORE_PIN33_BIT		8

  543. 

  544. #define CORE_PIN0_BITMASK	(1<<(CORE_PIN0_BIT))

  545. #define CORE_PIN1_BITMASK	(1<<(CORE_PIN1_BIT))

  546. #define CORE_PIN2_BITMASK	(1<<(CORE_PIN2_BIT))

  547. #define CORE_PIN3_BITMASK	(1<<(CORE_PIN3_BIT))

  548. #define CORE_PIN4_BITMASK	(1<<(CORE_PIN4_BIT))

  549. #define CORE_PIN5_BITMASK	(1<<(CORE_PIN5_BIT))

  550. #define CORE_PIN6_BITMASK	(1<<(CORE_PIN6_BIT))

  551. #define CORE_PIN7_BITMASK	(1<<(CORE_PIN7_BIT))

  552. #define CORE_PIN8_BITMASK	(1<<(CORE_PIN8_BIT))

  553. #define CORE_PIN9_BITMASK	(1<<(CORE_PIN9_BIT))

  554. #define CORE_PIN10_BITMASK	(1<<(CORE_PIN10_BIT))

  555. #define CORE_PIN11_BITMASK	(1<<(CORE_PIN11_BIT))

  556. #define CORE_PIN12_BITMASK	(1<<(CORE_PIN12_BIT))

  557. #define CORE_PIN13_BITMASK	(1<<(CORE_PIN13_BIT))

  558. #define CORE_PIN14_BITMASK	(1<<(CORE_PIN14_BIT))

  559. #define CORE_PIN15_BITMASK	(1<<(CORE_PIN15_BIT))

  560. #define CORE_PIN16_BITMASK	(1<<(CORE_PIN16_BIT))

  561. #define CORE_PIN17_BITMASK	(1<<(CORE_PIN17_BIT))

  562. #define CORE_PIN18_BITMASK	(1<<(CORE_PIN18_BIT))

  563. #define CORE_PIN19_BITMASK	(1<<(CORE_PIN19_BIT))

  564. #define CORE_PIN20_BITMASK	(1<<(CORE_PIN20_BIT))

  565. #define CORE_PIN21_BITMASK	(1<<(CORE_PIN21_BIT))

  566. #define CORE_PIN22_BITMASK	(1<<(CORE_PIN22_BIT))

  567. #define CORE_PIN23_BITMASK	(1<<(CORE_PIN23_BIT))

  568. #define CORE_PIN24_BITMASK	(1<<(CORE_PIN24_BIT))

  569. #define CORE_PIN25_BITMASK	(1<<(CORE_PIN25_BIT))

  570. #define CORE_PIN26_BITMASK	(1<<(CORE_PIN26_BIT))

  571. #define CORE_PIN27_BITMASK	(1<<(CORE_PIN27_BIT))

  572. #define CORE_PIN28_BITMASK	(1<<(CORE_PIN28_BIT))

  573. #define CORE_PIN29_BITMASK	(1<<(CORE_PIN29_BIT))

  574. #define CORE_PIN30_BITMASK	(1<<(CORE_PIN30_BIT))

  575. #define CORE_PIN31_BITMASK	(1<<(CORE_PIN31_BIT))

  576. #define CORE_PIN32_BITMASK	(1<<(CORE_PIN32_BIT))

  577. #define CORE_PIN33_BITMASK	(1<<(CORE_PIN33_BIT))

  578. 

  579. #define CORE_PIN0_PORTREG	GPIO1_DR

  580. #define CORE_PIN1_PORTREG	GPIO1_DR

  581. #define CORE_PIN2_PORTREG	GPIO4_DR

  582. #define CORE_PIN3_PORTREG	GPIO4_DR

  583. #define CORE_PIN4_PORTREG	GPIO4_DR

  584. #define CORE_PIN5_PORTREG	GPIO4_DR

  585. #define CORE_PIN6_PORTREG	GPIO2_DR

  586. #define CORE_PIN7_PORTREG	GPIO2_DR

  587. #define CORE_PIN8_PORTREG	GPIO2_DR

  588. #define CORE_PIN9_PORTREG	GPIO2_DR

  589. #define CORE_PIN10_PORTREG	GPIO2_DR

  590. #define CORE_PIN11_PORTREG	GPIO2_DR

  591. #define CORE_PIN12_PORTREG	GPIO2_DR

  592. #define CORE_PIN13_PORTREG	GPIO2_DR

  593. #define CORE_PIN14_PORTREG	GPIO1_DR

  594. #define CORE_PIN15_PORTREG	GPIO1_DR

  595. #define CORE_PIN16_PORTREG	GPIO1_DR

  596. #define CORE_PIN17_PORTREG	GPIO1_DR

  597. #define CORE_PIN18_PORTREG	GPIO1_DR

  598. #define CORE_PIN19_PORTREG	GPIO1_DR

  599. #define CORE_PIN20_PORTREG	GPIO1_DR

  600. #define CORE_PIN21_PORTREG	GPIO1_DR

  601. #define CORE_PIN22_PORTREG	GPIO1_DR

  602. #define CORE_PIN23_PORTREG	GPIO1_DR

  603. #define CORE_PIN24_PORTREG	GPIO1_DR

  604. #define CORE_PIN25_PORTREG	GPIO1_DR

  605. #define CORE_PIN26_PORTREG	GPIO1_DR

  606. #define CORE_PIN27_PORTREG	GPIO1_DR

  607. #define CORE_PIN28_PORTREG	GPIO3_DR

  608. #define CORE_PIN29_PORTREG	GPIO4_DR

  609. #define CORE_PIN30_PORTREG	GPIO4_DR

  610. #define CORE_PIN31_PORTREG	GPIO4_DR

  611. #define CORE_PIN32_PORTREG	GPIO2_DR

  612. #define CORE_PIN33_PORTREG	GPIO4_DR

  613. 

  614. #define CORE_PIN0_PORTSET	GPIO1_DR_SET

  615. #define CORE_PIN1_PORTSET	GPIO1_DR_SET

  616. #define CORE_PIN2_PORTSET	GPIO4_DR_SET

  617. #define CORE_PIN3_PORTSET	GPIO4_DR_SET

  618. #define CORE_PIN4_PORTSET	GPIO4_DR_SET

  619. #define CORE_PIN5_PORTSET	GPIO4_DR_SET

  620. #define CORE_PIN6_PORTSET	GPIO2_DR_SET

  621. #define CORE_PIN7_PORTSET	GPIO2_DR_SET

  622. #define CORE_PIN8_PORTSET	GPIO2_DR_SET

  623. #define CORE_PIN9_PORTSET	GPIO2_DR_SET

  624. #define CORE_PIN10_PORTSET	GPIO2_DR_SET

  625. #define CORE_PIN11_PORTSET	GPIO2_DR_SET

  626. #define CORE_PIN12_PORTSET	GPIO2_DR_SET

  627. #define CORE_PIN13_PORTSET	GPIO2_DR_SET

  628. #define CORE_PIN14_PORTSET	GPIO1_DR_SET

  629. #define CORE_PIN15_PORTSET	GPIO1_DR_SET

  630. #define CORE_PIN16_PORTSET	GPIO1_DR_SET

  631. #define CORE_PIN17_PORTSET	GPIO1_DR_SET

  632. #define CORE_PIN18_PORTSET	GPIO1_DR_SET

  633. #define CORE_PIN19_PORTSET	GPIO1_DR_SET

  634. #define CORE_PIN20_PORTSET	GPIO1_DR_SET

  635. #define CORE_PIN21_PORTSET	GPIO1_DR_SET

  636. #define CORE_PIN22_PORTSET	GPIO1_DR_SET

  637. #define CORE_PIN23_PORTSET	GPIO1_DR_SET

  638. #define CORE_PIN24_PORTSET	GPIO1_DR_SET

  639. #define CORE_PIN25_PORTSET	GPIO1_DR_SET

  640. #define CORE_PIN26_PORTSET	GPIO1_DR_SET

  641. #define CORE_PIN27_PORTSET	GPIO1_DR_SET

  642. #define CORE_PIN28_PORTSET	GPIO3_DR_SET

  643. #define CORE_PIN29_PORTSET	GPIO4_DR_SET

  644. #define CORE_PIN30_PORTSET	GPIO4_DR_SET

  645. #define CORE_PIN31_PORTSET	GPIO4_DR_SET

  646. #define CORE_PIN32_PORTSET	GPIO2_DR_SET

  647. #define CORE_PIN33_PORTSET	GPIO4_DR_SET

  648. 

  649. #define CORE_PIN0_PORTCLEAR	GPIO1_DR_CLEAR

  650. #define CORE_PIN1_PORTCLEAR	GPIO1_DR_CLEAR

  651. #define CORE_PIN2_PORTCLEAR	GPIO4_DR_CLEAR

  652. #define CORE_PIN3_PORTCLEAR	GPIO4_DR_CLEAR

  653. #define CORE_PIN4_PORTCLEAR	GPIO4_DR_CLEAR

  654. #define CORE_PIN5_PORTCLEAR	GPIO4_DR_CLEAR

  655. #define CORE_PIN6_PORTCLEAR	GPIO2_DR_CLEAR

  656. #define CORE_PIN7_PORTCLEAR	GPIO2_DR_CLEAR

  657. #define CORE_PIN8_PORTCLEAR	GPIO2_DR_CLEAR

  658. #define CORE_PIN9_PORTCLEAR	GPIO2_DR_CLEAR

  659. #define CORE_PIN10_PORTCLEAR	GPIO2_DR_CLEAR

  660. #define CORE_PIN11_PORTCLEAR	GPIO2_DR_CLEAR

  661. #define CORE_PIN12_PORTCLEAR	GPIO2_DR_CLEAR

  662. #define CORE_PIN13_PORTCLEAR	GPIO2_DR_CLEAR

  663. #define CORE_PIN14_PORTCLEAR	GPIO1_DR_CLEAR

  664. #define CORE_PIN15_PORTCLEAR	GPIO1_DR_CLEAR

  665. #define CORE_PIN16_PORTCLEAR	GPIO1_DR_CLEAR

  666. #define CORE_PIN17_PORTCLEAR	GPIO1_DR_CLEAR

  667. #define CORE_PIN18_PORTCLEAR	GPIO1_DR_CLEAR

  668. #define CORE_PIN19_PORTCLEAR	GPIO1_DR_CLEAR

  669. #define CORE_PIN20_PORTCLEAR	GPIO1_DR_CLEAR

  670. #define CORE_PIN21_PORTCLEAR	GPIO1_DR_CLEAR

  671. #define CORE_PIN22_PORTCLEAR	GPIO1_DR_CLEAR

  672. #define CORE_PIN23_PORTCLEAR	GPIO1_DR_CLEAR

  673. #define CORE_PIN24_PORTCLEAR	GPIO1_DR_CLEAR

  674. #define CORE_PIN25_PORTCLEAR	GPIO1_DR_CLEAR

  675. #define CORE_PIN26_PORTCLEAR	GPIO1_DR_CLEAR

  676. #define CORE_PIN27_PORTCLEAR	GPIO1_DR_CLEAR

  677. #define CORE_PIN28_PORTCLEAR	GPIO3_DR_CLEAR

  678. #define CORE_PIN29_PORTCLEAR	GPIO4_DR_CLEAR

  679. #define CORE_PIN30_PORTCLEAR	GPIO4_DR_CLEAR

  680. #define CORE_PIN31_PORTCLEAR	GPIO4_DR_CLEAR

  681. #define CORE_PIN32_PORTCLEAR	GPIO2_DR_CLEAR

  682. #define CORE_PIN33_PORTCLEAR	GPIO4_DR_CLEAR

  683. 

  684. #define CORE_PIN0_DDRREG	GPIO1_GDIR

  685. #define CORE_PIN1_DDRREG	GPIO1_GDIR

  686. #define CORE_PIN2_DDRREG	GPIO4_GDIR

  687. #define CORE_PIN3_DDRREG	GPIO4_GDIR

  688. #define CORE_PIN4_DDRREG	GPIO4_GDIR

  689. #define CORE_PIN5_DDRREG	GPIO4_GDIR

  690. #define CORE_PIN6_DDRREG	GPIO2_GDIR

  691. #define CORE_PIN7_DDRREG	GPIO2_GDIR

  692. #define CORE_PIN8_DDRREG	GPIO2_GDIR

  693. #define CORE_PIN9_DDRREG	GPIO2_GDIR

  694. #define CORE_PIN10_DDRREG	GPIO2_GDIR

  695. #define CORE_PIN11_DDRREG	GPIO2_GDIR

  696. #define CORE_PIN12_DDRREG	GPIO2_GDIR

  697. #define CORE_PIN13_DDRREG	GPIO2_GDIR

  698. #define CORE_PIN14_DDRREG	GPIO1_GDIR

  699. #define CORE_PIN15_DDRREG	GPIO1_GDIR

  700. #define CORE_PIN16_DDRREG	GPIO1_GDIR

  701. #define CORE_PIN17_DDRREG	GPIO1_GDIR

  702. #define CORE_PIN18_DDRREG	GPIO1_GDIR

  703. #define CORE_PIN19_DDRREG	GPIO1_GDIR

  704. #define CORE_PIN20_DDRREG	GPIO1_GDIR

  705. #define CORE_PIN21_DDRREG	GPIO1_GDIR

  706. #define CORE_PIN22_DDRREG	GPIO1_GDIR

  707. #define CORE_PIN23_DDRREG	GPIO1_GDIR

  708. #define CORE_PIN24_DDRREG	GPIO1_GDIR

  709. #define CORE_PIN25_DDRREG	GPIO1_GDIR

  710. #define CORE_PIN26_DDRREG	GPIO1_GDIR

  711. #define CORE_PIN27_DDRREG	GPIO1_GDIR

  712. #define CORE_PIN28_DDRREG	GPIO3_GDIR

  713. #define CORE_PIN29_DDRREG	GPIO4_GDIR

  714. #define CORE_PIN30_DDRREG	GPIO4_GDIR

  715. #define CORE_PIN31_DDRREG	GPIO4_GDIR

  716. #define CORE_PIN32_DDRREG	GPIO2_GDIR

  717. #define CORE_PIN33_DDRREG	GPIO4_GDIR

  718. 

  719. #define CORE_PIN0_PINREG	GPIO1_PSR

  720. #define CORE_PIN1_PINREG	GPIO1_PSR

  721. #define CORE_PIN2_PINREG	GPIO4_PSR

  722. #define CORE_PIN3_PINREG	GPIO4_PSR

  723. #define CORE_PIN4_PINREG	GPIO4_PSR

  724. #define CORE_PIN5_PINREG	GPIO4_PSR

  725. #define CORE_PIN6_PINREG	GPIO2_PSR

  726. #define CORE_PIN7_PINREG	GPIO2_PSR

  727. #define CORE_PIN8_PINREG	GPIO2_PSR

  728. #define CORE_PIN9_PINREG	GPIO2_PSR

  729. #define CORE_PIN10_PINREG	GPIO2_PSR

  730. #define CORE_PIN11_PINREG	GPIO2_PSR

  731. #define CORE_PIN12_PINREG	GPIO2_PSR

  732. #define CORE_PIN13_PINREG	GPIO2_PSR

  733. #define CORE_PIN14_PINREG	GPIO1_PSR

  734. #define CORE_PIN15_PINREG	GPIO1_PSR

  735. #define CORE_PIN16_PINREG	GPIO1_PSR

  736. #define CORE_PIN17_PINREG	GPIO1_PSR

  737. #define CORE_PIN18_PINREG	GPIO1_PSR

  738. #define CORE_PIN19_PINREG	GPIO1_PSR

  739. #define CORE_PIN20_PINREG	GPIO1_PSR

  740. #define CORE_PIN21_PINREG	GPIO1_PSR

  741. #define CORE_PIN22_PINREG	GPIO1_PSR

  742. #define CORE_PIN23_PINREG	GPIO1_PSR

  743. #define CORE_PIN24_PINREG	GPIO1_PSR

  744. #define CORE_PIN25_PINREG	GPIO1_PSR

  745. #define CORE_PIN26_PINREG	GPIO1_PSR

  746. #define CORE_PIN27_PINREG	GPIO1_PSR

  747. #define CORE_PIN28_PINREG	GPIO3_PSR

  748. #define CORE_PIN29_PINREG	GPIO4_PSR

  749. #define CORE_PIN30_PINREG	GPIO4_PSR

  750. #define CORE_PIN31_PINREG	GPIO4_PSR

  751. #define CORE_PIN32_PINREG	GPIO2_PSR

  752. #define CORE_PIN33_PINREG	GPIO4_PSR

  753. 

  754. // mux config registers control which peripheral uses the pin

  755. #define CORE_PIN0_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03

  756. #define CORE_PIN1_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02

  757. #define CORE_PIN2_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04

  758. #define CORE_PIN3_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05

  759. #define CORE_PIN4_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06

  760. #define CORE_PIN5_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07

  761. #define CORE_PIN6_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01

  762. #define CORE_PIN7_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00

  763. #define CORE_PIN8_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10

  764. #define CORE_PIN9_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11

  765. #define CORE_PIN10_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00

  766. #define CORE_PIN11_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02

  767. #define CORE_PIN12_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01

  768. #define CORE_PIN13_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03

  769. #define CORE_PIN14_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02

  770. #define CORE_PIN15_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03

  771. #define CORE_PIN16_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07

  772. #define CORE_PIN17_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06

  773. #define CORE_PIN18_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01

  774. #define CORE_PIN19_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00

  775. #define CORE_PIN20_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10

  776. #define CORE_PIN21_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11

  777. #define CORE_PIN22_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08

  778. #define CORE_PIN23_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09

  779. #define CORE_PIN24_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12

  780. #define CORE_PIN25_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13

  781. #define CORE_PIN26_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14

  782. #define CORE_PIN27_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15

  783. #define CORE_PIN28_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32

  784. #define CORE_PIN29_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31

  785. #define CORE_PIN30_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24

  786. #define CORE_PIN31_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23

  787. #define CORE_PIN32_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12

  788. #define CORE_PIN33_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08

  789. 

  790. // pad config registers control pullup/pulldown/keeper, drive strength, etc

  791. #define CORE_PIN0_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03

  792. #define CORE_PIN1_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02

  793. #define CORE_PIN2_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04

  794. #define CORE_PIN3_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05

  795. #define CORE_PIN4_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06

  796. #define CORE_PIN5_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07

  797. #define CORE_PIN6_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01

  798. #define CORE_PIN7_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00

  799. #define CORE_PIN8_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10

  800. #define CORE_PIN9_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11

  801. #define CORE_PIN10_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00

  802. #define CORE_PIN11_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02

  803. #define CORE_PIN12_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01

  804. #define CORE_PIN13_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03

  805. #define CORE_PIN14_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02

  806. #define CORE_PIN15_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03

  807. #define CORE_PIN16_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07

  808. #define CORE_PIN17_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06

  809. #define CORE_PIN18_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01

  810. #define CORE_PIN19_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00

  811. #define CORE_PIN20_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10

  812. #define CORE_PIN21_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11

  813. #define CORE_PIN22_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08

  814. #define CORE_PIN23_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09

  815. #define CORE_PIN24_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12

  816. #define CORE_PIN25_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13

  817. #define CORE_PIN26_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14

  818. #define CORE_PIN27_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15

  819. #define CORE_PIN28_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32

  820. #define CORE_PIN29_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31

  821. #define CORE_PIN30_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24

  822. #define CORE_PIN31_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23

  823. #define CORE_PIN32_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12

  824. #define CORE_PIN33_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08

  825. 

  826. #define CORE_LED0_PIN		13

  827. 

  828. #define CORE_ADC0_PIN		14

  829. #define CORE_ADC1_PIN		15

  830. #define CORE_ADC2_PIN		16

  831. #define CORE_ADC3_PIN		17

  832. #define CORE_ADC4_PIN		18

  833. #define CORE_ADC5_PIN		19

  834. #define CORE_ADC6_PIN		20

  835. #define CORE_ADC7_PIN		21

  836. #define CORE_ADC8_PIN		22

  837. #define CORE_ADC9_PIN		23

  838. 

  839. #define CORE_RXD0_PIN		0

  840. #define CORE_TXD0_PIN		1

  841. #define CORE_RXD1_PIN		6

  842. #define CORE_TXD1_PIN		7

  843. #define CORE_RXD2_PIN		15

  844. #define CORE_TXD2_PIN		14

  845. #define CORE_RXD3_PIN		16

  846. #define CORE_TXD3_PIN		17

  847. #define CORE_RXD4_PIN		21

  848. #define CORE_TXD4_PIN		20

  849. #define CORE_RXD5_PIN		25

  850. #define CORE_TXD5_PIN		24

  851. #define CORE_RXD6_PIN		28

  852. #define CORE_TXD6_PIN		29

  853. #define CORE_RXD7_PIN		30

  854. #define CORE_TXD7_PIN		31

  855. 

  856. #define CORE_INT0_PIN		0

  857. #define CORE_INT1_PIN		1

  858. #define CORE_INT2_PIN		2

  859. #define CORE_INT3_PIN		3

  860. #define CORE_INT4_PIN		4

  861. #define CORE_INT5_PIN		5

  862. #define CORE_INT6_PIN		6

  863. #define CORE_INT7_PIN		7

  864. #define CORE_INT8_PIN		8

  865. #define CORE_INT9_PIN		9

  866. #define CORE_INT10_PIN		10

  867. #define CORE_INT11_PIN		11

  868. #define CORE_INT12_PIN		12

  869. #define CORE_INT13_PIN		13

  870. #define CORE_INT14_PIN		14

  871. #define CORE_INT15_PIN		15

  872. #define CORE_INT16_PIN		16

  873. #define CORE_INT17_PIN		17

  874. #define CORE_INT18_PIN		18

  875. #define CORE_INT19_PIN		19

  876. #define CORE_INT20_PIN		20

  877. #define CORE_INT21_PIN		21

  878. #define CORE_INT22_PIN		22

  879. #define CORE_INT23_PIN		23

  880. #define CORE_INT24_PIN		24

  881. #define CORE_INT25_PIN		25

  882. #define CORE_INT26_PIN		26

  883. #define CORE_INT27_PIN		27

  884. #define CORE_INT28_PIN		28

  885. #define CORE_INT29_PIN		29

  886. #define CORE_INT30_PIN		30

  887. #define CORE_INT31_PIN		31

  888. #define CORE_INT32_PIN		32

  889. #define CORE_INT33_PIN		33

  890. #define CORE_INT_EVERY_PIN	1

  891. 

  892. #endif // __IMXRT1052__

  893. 

  894. #ifdef __cplusplus

  895. extern "C" {

  896. #endif

  897. 

  898. 

  899. void digitalWrite(uint8_t pin, uint8_t val);

  900. static inline void digitalWriteFast(uint8_t pin, uint8_t val) __attribute__((always_inline, unused));

  901. static inline void digitalWriteFast(uint8_t pin, uint8_t val)

  902. {

  903. 	if (__builtin_constant_p(pin)) {

  904. 		if (val) {

  905. 			if (pin == 0) {

  906. 				CORE_PIN0_PORTSET = CORE_PIN0_BITMASK;

  907. 			} else if (pin == 1) {

  908. 				CORE_PIN1_PORTSET = CORE_PIN1_BITMASK;

  909. 			} else if (pin == 2) {

  910. 				CORE_PIN2_PORTSET = CORE_PIN2_BITMASK;

  911. 			} else if (pin == 3) {

  912. 				CORE_PIN3_PORTSET = CORE_PIN3_BITMASK;

  913. 			} else if (pin == 4) {

  914. 				CORE_PIN4_PORTSET = CORE_PIN4_BITMASK;

  915. 			} else if (pin == 5) {

  916. 				CORE_PIN5_PORTSET = CORE_PIN5_BITMASK;

  917. 			} else if (pin == 6) {

  918. 				CORE_PIN6_PORTSET = CORE_PIN6_BITMASK;

  919. 			} else if (pin == 7) {

  920. 				CORE_PIN7_PORTSET = CORE_PIN7_BITMASK;

  921. 			} else if (pin == 8) {

  922. 				CORE_PIN8_PORTSET = CORE_PIN8_BITMASK;

  923. 			} else if (pin == 9) {

  924. 				CORE_PIN9_PORTSET = CORE_PIN9_BITMASK;

  925. 			} else if (pin == 10) {

  926. 				CORE_PIN10_PORTSET = CORE_PIN10_BITMASK;

  927. 			} else if (pin == 11) {

  928. 				CORE_PIN11_PORTSET = CORE_PIN11_BITMASK;

  929. 			} else if (pin == 12) {

  930. 				CORE_PIN12_PORTSET = CORE_PIN12_BITMASK;

  931. 			} else if (pin == 13) {

  932. 				CORE_PIN13_PORTSET = CORE_PIN13_BITMASK;

  933. 			} else if (pin == 14) {

  934. 				CORE_PIN14_PORTSET = CORE_PIN14_BITMASK;

  935. 			} else if (pin == 15) {

  936. 				CORE_PIN15_PORTSET = CORE_PIN15_BITMASK;

  937. 			} else if (pin == 16) {

  938. 				CORE_PIN16_PORTSET = CORE_PIN16_BITMASK;

  939. 			} else if (pin == 17) {

  940. 				CORE_PIN17_PORTSET = CORE_PIN17_BITMASK;

  941. 			} else if (pin == 18) {

  942. 				CORE_PIN18_PORTSET = CORE_PIN18_BITMASK;

  943. 			} else if (pin == 19) {

  944. 				CORE_PIN19_PORTSET = CORE_PIN19_BITMASK;

  945. 			} else if (pin == 20) {

  946. 				CORE_PIN20_PORTSET = CORE_PIN20_BITMASK;

  947. 			} else if (pin == 21) {

  948. 				CORE_PIN21_PORTSET = CORE_PIN21_BITMASK;

  949. 			} else if (pin == 22) {

  950. 				CORE_PIN22_PORTSET = CORE_PIN22_BITMASK;

  951. 			} else if (pin == 23) {

  952. 				CORE_PIN23_PORTSET = CORE_PIN23_BITMASK;

  953. 			} else if (pin == 24) {

  954. 				CORE_PIN24_PORTSET = CORE_PIN24_BITMASK;

  955. 			} else if (pin == 25) {

  956. 				CORE_PIN25_PORTSET = CORE_PIN25_BITMASK;

  957. 			} else if (pin == 26) {

  958. 				CORE_PIN26_PORTSET = CORE_PIN26_BITMASK;

  959. 			} else if (pin == 27) {

  960. 				CORE_PIN27_PORTSET = CORE_PIN27_BITMASK;

  961. 			} else if (pin == 28) {

  962. 				CORE_PIN28_PORTSET = CORE_PIN28_BITMASK;

  963. 			} else if (pin == 29) {

  964. 				CORE_PIN29_PORTSET = CORE_PIN29_BITMASK;

  965. 			} else if (pin == 30) {

  966. 				CORE_PIN30_PORTSET = CORE_PIN30_BITMASK;

  967. 			} else if (pin == 31) {

  968. 				CORE_PIN31_PORTSET = CORE_PIN31_BITMASK;

  969. 			} else if (pin == 32) {

  970. 				CORE_PIN32_PORTSET = CORE_PIN32_BITMASK;

  971. 			} else if (pin == 33) {

  972. 				CORE_PIN33_PORTSET = CORE_PIN33_BITMASK;

  973. #if defined(__IMXRT1062__)

  974. 			} else if (pin == 34) {

  975. 				CORE_PIN34_PORTSET = CORE_PIN34_BITMASK;

  976. 			} else if (pin == 35) {

  977. 				CORE_PIN35_PORTSET = CORE_PIN35_BITMASK;

  978. 			} else if (pin == 36) {

  979. 				CORE_PIN36_PORTSET = CORE_PIN36_BITMASK;

  980. 			} else if (pin == 37) {

  981. 				CORE_PIN37_PORTSET = CORE_PIN37_BITMASK;

  982. 			} else if (pin == 38) {

  983. 				CORE_PIN38_PORTSET = CORE_PIN38_BITMASK;

  984. 			} else if (pin == 39) {

  985. 				CORE_PIN39_PORTSET = CORE_PIN39_BITMASK;

  986. #endif

  987. 			}

  988. 		} else {

  989. 			if (pin == 0) {

  990. 				CORE_PIN0_PORTCLEAR = CORE_PIN0_BITMASK;

  991. 			} else if (pin == 1) {

  992. 				CORE_PIN1_PORTCLEAR = CORE_PIN1_BITMASK;

  993. 			} else if (pin == 2) {

  994. 				CORE_PIN2_PORTCLEAR = CORE_PIN2_BITMASK;

  995. 			} else if (pin == 3) {

  996. 				CORE_PIN3_PORTCLEAR = CORE_PIN3_BITMASK;

  997. 			} else if (pin == 4) {

  998. 				CORE_PIN4_PORTCLEAR = CORE_PIN4_BITMASK;

  999. 			} else if (pin == 5) {

  1000. 				CORE_PIN5_PORTCLEAR = CORE_PIN5_BITMASK;

  1001. 			} else if (pin == 6) {

  1002. 				CORE_PIN6_PORTCLEAR = CORE_PIN6_BITMASK;

  1003. 			} else if (pin == 7) {

  1004. 				CORE_PIN7_PORTCLEAR = CORE_PIN7_BITMASK;

  1005. 			} else if (pin == 8) {

  1006. 				CORE_PIN8_PORTCLEAR = CORE_PIN8_BITMASK;

  1007. 			} else if (pin == 9) {

  1008. 				CORE_PIN9_PORTCLEAR = CORE_PIN9_BITMASK;

  1009. 			} else if (pin == 10) {

  1010. 				CORE_PIN10_PORTCLEAR = CORE_PIN10_BITMASK;

  1011. 			} else if (pin == 11) {

  1012. 				CORE_PIN11_PORTCLEAR = CORE_PIN11_BITMASK;

  1013. 			} else if (pin == 12) {

  1014. 				CORE_PIN12_PORTCLEAR = CORE_PIN12_BITMASK;

  1015. 			} else if (pin == 13) {

  1016. 				CORE_PIN13_PORTCLEAR = CORE_PIN13_BITMASK;

  1017. 			} else if (pin == 14) {

  1018. 				CORE_PIN14_PORTCLEAR = CORE_PIN14_BITMASK;

  1019. 			} else if (pin == 15) {

  1020. 				CORE_PIN15_PORTCLEAR = CORE_PIN15_BITMASK;

  1021. 			} else if (pin == 16) {

  1022. 				CORE_PIN16_PORTCLEAR = CORE_PIN16_BITMASK;

  1023. 			} else if (pin == 17) {

  1024. 				CORE_PIN17_PORTCLEAR = CORE_PIN17_BITMASK;

  1025. 			} else if (pin == 18) {

  1026. 				CORE_PIN18_PORTCLEAR = CORE_PIN18_BITMASK;

  1027. 			} else if (pin == 19) {

  1028. 				CORE_PIN19_PORTCLEAR = CORE_PIN19_BITMASK;

  1029. 			} else if (pin == 20) {

  1030. 				CORE_PIN20_PORTCLEAR = CORE_PIN20_BITMASK;

  1031. 			} else if (pin == 21) {

  1032. 				CORE_PIN21_PORTCLEAR = CORE_PIN21_BITMASK;

  1033. 			} else if (pin == 22) {

  1034. 				CORE_PIN22_PORTCLEAR = CORE_PIN22_BITMASK;

  1035. 			} else if (pin == 23) {

  1036. 				CORE_PIN23_PORTCLEAR = CORE_PIN23_BITMASK;

  1037. 			} else if (pin == 24) {

  1038. 				CORE_PIN24_PORTCLEAR = CORE_PIN24_BITMASK;

  1039. 			} else if (pin == 25) {

  1040. 				CORE_PIN25_PORTCLEAR = CORE_PIN25_BITMASK;

  1041. 			} else if (pin == 26) {

  1042. 				CORE_PIN26_PORTCLEAR = CORE_PIN26_BITMASK;

  1043. 			} else if (pin == 27) {

  1044. 				CORE_PIN27_PORTCLEAR = CORE_PIN27_BITMASK;

  1045. 			} else if (pin == 28) {

  1046. 				CORE_PIN28_PORTCLEAR = CORE_PIN28_BITMASK;

  1047. 			} else if (pin == 29) {

  1048. 				CORE_PIN29_PORTCLEAR = CORE_PIN29_BITMASK;

  1049. 			} else if (pin == 30) {

  1050. 				CORE_PIN30_PORTCLEAR = CORE_PIN30_BITMASK;

  1051. 			} else if (pin == 31) {

  1052. 				CORE_PIN31_PORTCLEAR = CORE_PIN31_BITMASK;

  1053. 			} else if (pin == 32) {

  1054. 				CORE_PIN32_PORTCLEAR = CORE_PIN32_BITMASK;

  1055. 			} else if (pin == 33) {

  1056. 				CORE_PIN33_PORTCLEAR = CORE_PIN33_BITMASK;

  1057. #if defined(__IMXRT1062__)

  1058. 			} else if (pin == 34) {

  1059. 				CORE_PIN34_PORTCLEAR = CORE_PIN34_BITMASK;

  1060. 			} else if (pin == 35) {

  1061. 				CORE_PIN35_PORTCLEAR = CORE_PIN35_BITMASK;

  1062. 			} else if (pin == 36) {

  1063. 				CORE_PIN36_PORTCLEAR = CORE_PIN36_BITMASK;

  1064. 			} else if (pin == 37) {

  1065. 				CORE_PIN37_PORTCLEAR = CORE_PIN37_BITMASK;

  1066. 			} else if (pin == 38) {

  1067. 				CORE_PIN38_PORTCLEAR = CORE_PIN38_BITMASK;

  1068. 			} else if (pin == 39) {

  1069. 				CORE_PIN39_PORTCLEAR = CORE_PIN39_BITMASK;

  1070. #endif

  1071. 			}

  1072. 		}

  1073. 	} else {

  1074. 		if(val) *portSetRegister(pin) = digitalPinToBitMask(pin);

  1075. 		else *portClearRegister(pin) = digitalPinToBitMask(pin);

  1076. 	}

  1077. }

  1078. 

  1079. uint8_t digitalRead(uint8_t pin);

  1080. static inline uint8_t digitalReadFast(uint8_t pin) __attribute__((always_inline, unused));

  1081. static inline uint8_t digitalReadFast(uint8_t pin)

  1082. {

  1083. 	if (__builtin_constant_p(pin)) {

  1084. 		if (pin == 0) {

  1085. 			return (CORE_PIN0_PINREG & CORE_PIN0_BITMASK) ? 1 : 0;

  1086. 		} else if (pin == 1) {

  1087. 			return (CORE_PIN1_PINREG & CORE_PIN1_BITMASK) ? 1 : 0;

  1088. 		} else if (pin == 2) {

  1089. 			return (CORE_PIN2_PINREG & CORE_PIN2_BITMASK) ? 1 : 0;

  1090. 		} else if (pin == 3) {

  1091. 			return (CORE_PIN3_PINREG & CORE_PIN3_BITMASK) ? 1 : 0;

  1092. 		} else if (pin == 4) {

  1093. 			return (CORE_PIN4_PINREG & CORE_PIN4_BITMASK) ? 1 : 0;

  1094. 		} else if (pin == 5) {

  1095. 			return (CORE_PIN5_PINREG & CORE_PIN5_BITMASK) ? 1 : 0;

  1096. 		} else if (pin == 6) {

  1097. 			return (CORE_PIN6_PINREG & CORE_PIN6_BITMASK) ? 1 : 0;

  1098. 		} else if (pin == 7) {

  1099. 			return (CORE_PIN7_PINREG & CORE_PIN7_BITMASK) ? 1 : 0;

  1100. 		} else if (pin == 8) {

  1101. 			return (CORE_PIN8_PINREG & CORE_PIN8_BITMASK) ? 1 : 0;

  1102. 		} else if (pin == 9) {

  1103. 			return (CORE_PIN9_PINREG & CORE_PIN9_BITMASK) ? 1 : 0;

  1104. 		} else if (pin == 10) {

  1105. 			return (CORE_PIN10_PINREG & CORE_PIN10_BITMASK) ? 1 : 0;

  1106. 		} else if (pin == 11) {

  1107. 			return (CORE_PIN11_PINREG & CORE_PIN11_BITMASK) ? 1 : 0;

  1108. 		} else if (pin == 12) {

  1109. 			return (CORE_PIN12_PINREG & CORE_PIN12_BITMASK) ? 1 : 0;

  1110. 		} else if (pin == 13) {

  1111. 			return (CORE_PIN13_PINREG & CORE_PIN13_BITMASK) ? 1 : 0;

  1112. 		} else if (pin == 14) {

  1113. 			return (CORE_PIN14_PINREG & CORE_PIN14_BITMASK) ? 1 : 0;

  1114. 		} else if (pin == 15) {

  1115. 			return (CORE_PIN15_PINREG & CORE_PIN15_BITMASK) ? 1 : 0;

  1116. 		} else if (pin == 16) {

  1117. 			return (CORE_PIN16_PINREG & CORE_PIN16_BITMASK) ? 1 : 0;

  1118. 		} else if (pin == 17) {

  1119. 			return (CORE_PIN17_PINREG & CORE_PIN17_BITMASK) ? 1 : 0;

  1120. 		} else if (pin == 18) {

  1121. 			return (CORE_PIN18_PINREG & CORE_PIN18_BITMASK) ? 1 : 0;

  1122. 		} else if (pin == 19) {

  1123. 			return (CORE_PIN19_PINREG & CORE_PIN19_BITMASK) ? 1 : 0;

  1124. 		} else if (pin == 20) {

  1125. 			return (CORE_PIN20_PINREG & CORE_PIN20_BITMASK) ? 1 : 0;

  1126. 		} else if (pin == 21) {

  1127. 			return (CORE_PIN21_PINREG & CORE_PIN21_BITMASK) ? 1 : 0;

  1128. 		} else if (pin == 22) {

  1129. 			return (CORE_PIN22_PINREG & CORE_PIN22_BITMASK) ? 1 : 0;

  1130. 		} else if (pin == 23) {

  1131. 			return (CORE_PIN23_PINREG & CORE_PIN23_BITMASK) ? 1 : 0;

  1132. 		} else if (pin == 24) {

  1133. 			return (CORE_PIN24_PINREG & CORE_PIN24_BITMASK) ? 1 : 0;

  1134. 		} else if (pin == 25) {

  1135. 			return (CORE_PIN25_PINREG & CORE_PIN25_BITMASK) ? 1 : 0;

  1136. 		} else if (pin == 26) {

  1137. 			return (CORE_PIN26_PINREG & CORE_PIN26_BITMASK) ? 1 : 0;

  1138. 		} else if (pin == 27) {

  1139. 			return (CORE_PIN27_PINREG & CORE_PIN27_BITMASK) ? 1 : 0;

  1140. 		} else if (pin == 28) {

  1141. 			return (CORE_PIN28_PINREG & CORE_PIN28_BITMASK) ? 1 : 0;

  1142. 		} else if (pin == 29) {

  1143. 			return (CORE_PIN29_PINREG & CORE_PIN29_BITMASK) ? 1 : 0;

  1144. 		} else if (pin == 30) {

  1145. 			return (CORE_PIN30_PINREG & CORE_PIN30_BITMASK) ? 1 : 0;

  1146. 		} else if (pin == 31) {

  1147. 			return (CORE_PIN31_PINREG & CORE_PIN31_BITMASK) ? 1 : 0;

  1148. 		} else if (pin == 32) {

  1149. 			return (CORE_PIN32_PINREG & CORE_PIN32_BITMASK) ? 1 : 0;

  1150. 		} else if (pin == 33) {

  1151. 			return (CORE_PIN33_PINREG & CORE_PIN33_BITMASK) ? 1 : 0;

  1152. 		} else {

  1153. 			return 0;

  1154. 		}

  1155. 	} else {

  1156. 		return (*portInputRegister(pin) & digitalPinToBitMask(pin)) ? 1 : 0;

  1157. 	}

  1158. }

  1159. 

  1160. 

  1161. void pinMode(uint8_t pin, uint8_t mode);

  1162. void init_pins(void);

  1163. void analogWrite(uint8_t pin, int val);

  1164. uint32_t analogWriteRes(uint32_t bits);

  1165. static inline uint32_t analogWriteResolution(uint32_t bits) { return analogWriteRes(bits); }

  1166. void analogWriteFrequency(uint8_t pin, float frequency);

  1167. void attachInterrupt(uint8_t pin, void (*function)(void), int mode);

  1168. void detachInterrupt(uint8_t pin);

  1169. void _init_Teensyduino_internal_(void);

  1170. int analogRead(uint8_t pin);

  1171. void analogReference(uint8_t type);

  1172. void analogReadRes(unsigned int bits);

  1173. static inline void analogReadResolution(unsigned int bits) { analogReadRes(bits); }

  1174. void analogReadAveraging(unsigned int num);

  1175. void analog_init(void);

  1176. int touchRead(uint8_t pin);

  1177. 

  1178. static inline void shiftOut(uint8_t, uint8_t, uint8_t, uint8_t) __attribute__((always_inline, unused));

  1179. extern void _shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t value) __attribute__((noinline));

  1180. extern void shiftOut_lsbFirst(uint8_t dataPin, uint8_t clockPin, uint8_t value) __attribute__((noinline));

  1181. extern void shiftOut_msbFirst(uint8_t dataPin, uint8_t clockPin, uint8_t value) __attribute__((noinline));

  1182. 

  1183. static inline void shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t value)

  1184. {

  1185.         if (__builtin_constant_p(bitOrder)) {

  1186.                 if (bitOrder == LSBFIRST) {

  1187.                         shiftOut_lsbFirst(dataPin, clockPin, value);

  1188.                 } else {

  1189.                         shiftOut_msbFirst(dataPin, clockPin, value);

  1190.                 }

  1191.         } else {

  1192.                 _shiftOut(dataPin, clockPin, bitOrder, value);

  1193.         }

  1194. }

  1195. 

  1196. static inline uint8_t shiftIn(uint8_t, uint8_t, uint8_t) __attribute__((always_inline, unused));

  1197. extern uint8_t _shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder) __attribute__((noinline));

  1198. extern uint8_t shiftIn_lsbFirst(uint8_t dataPin, uint8_t clockPin) __attribute__((noinline));

  1199. extern uint8_t shiftIn_msbFirst(uint8_t dataPin, uint8_t clockPin) __attribute__((noinline));

  1200. 

  1201. static inline uint8_t shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder)

  1202. {

  1203.         if (__builtin_constant_p(bitOrder)) {

  1204.                 if (bitOrder == LSBFIRST) {

  1205.                         return shiftIn_lsbFirst(dataPin, clockPin);

  1206.                 } else {

  1207.                         return shiftIn_msbFirst(dataPin, clockPin);

  1208.                 }

  1209.         } else {

  1210.                 return _shiftIn(dataPin, clockPin, bitOrder);

  1211.         }

  1212. }

  1213. 

  1214. void _reboot_Teensyduino_(void) __attribute__((noreturn));

  1215. void _restart_Teensyduino_(void) __attribute__((noreturn));

  1216. 

  1217. void yield(void);

  1218. 

  1219. void delay(uint32_t msec);

  1220. 

  1221. extern volatile uint32_t F_CPU_ACTUAL;

  1222. extern volatile uint32_t F_BUS_ACTUAL;

  1223. extern volatile uint32_t systick_millis_count;

  1224. 

  1225. static inline uint32_t millis(void) __attribute__((always_inline, unused));

  1226. static inline uint32_t millis(void)

  1227. {

  1228. 	return systick_millis_count;

  1229. }

  1230. 

  1231. uint32_t micros(void);

  1232. 

  1233. static inline void delayMicroseconds(uint32_t) __attribute__((always_inline, unused));

  1234. static inline void delayMicroseconds(uint32_t usec)

  1235. {

  1236. 	uint32_t begin = ARM_DWT_CYCCNT;

  1237. 	uint32_t cycles = F_CPU_ACTUAL / 1000000 * usec;

  1238. 	// TODO: check if cycles is large, do a wait with yield calls until it's smaller

  1239. 	while (ARM_DWT_CYCCNT - begin < cycles) ; // wait

  1240. }

  1241. 

  1242. static inline void delayNanoseconds(uint32_t) __attribute__((always_inline, unused));

  1243. static inline void delayNanoseconds(uint32_t nsec)

  1244. {

  1245. 	uint32_t begin = ARM_DWT_CYCCNT;

  1246. 	uint32_t cycles =   ((F_CPU_ACTUAL>>16) * nsec) / (1000000000UL>>16);

  1247. 	while (ARM_DWT_CYCCNT - begin < cycles) ; // wait

  1248. }

  1249. 

  1250. 

  1251. unsigned long rtc_get(void);

  1252. void rtc_set(unsigned long t);

  1253. void rtc_compensate(int adjust);

  1254. 

  1255. void tempmon_init(void);

  1256. float tempmonGetTemp(void);

  1257. void tempmon_Start();

  1258. void tempmon_Stop();

  1259. void tempmon_PwrDwn();

  1260. 

  1261. #ifdef __cplusplus

  1262. }

  1263. 

  1264. class teensy3_clock_class

  1265. {

  1266. public:

  1267.         static unsigned long get(void) __attribute__((always_inline)) { return rtc_get(); }

  1268.         static void set(unsigned long t) __attribute__((always_inline)) { rtc_set(t); }

  1269.         static void compensate(int adj) __attribute__((always_inline)) { rtc_compensate(adj); }

  1270. };

  1271. extern teensy3_clock_class Teensy3Clock;

  1272. 

  1273. #endif // __cplusplus

  1274. 

  1275. 

  1276.