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Teensy 4.1 core updated for C++20
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teensy-core-4.1/teensy4/core_pins.h

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  1. /* Teensyduino Core Library

  2.  * http://www.pjrc.com/teensy/

  3.  * Copyright (c) 2018 PJRC.COM, LLC.

  4.  *

  5.  * Permission is hereby granted, free of charge, to any person obtaining

  6.  * a copy of this software and associated documentation files (the

  7.  * "Software"), to deal in the Software without restriction, including

  8.  * without limitation the rights to use, copy, modify, merge, publish,

  9.  * distribute, sublicense, and/or sell copies of the Software, and to

  10.  * permit persons to whom the Software is furnished to do so, subject to

  11.  * the following conditions:

  12.  *

  13.  * 1. The above copyright notice and this permission notice shall be

  14.  * included in all copies or substantial portions of the Software.

  15.  *

  16.  * 2. If the Software is incorporated into a build system that allows

  17.  * selection among a list of target devices, then similar target

  18.  * devices manufactured by PJRC.COM must be included in the list of

  19.  * target devices and selectable in the same manner.

  20.  *

  21.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

  22.  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

  23.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

  24.  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS

  25.  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN

  26.  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

  27.  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

  28.  * SOFTWARE.

  29.  */

  30. 

  31. #pragma once

  32. #include "imxrt.h"

  33. #include "pins_arduino.h"

  34. 

  35. #define HIGH			1

  36. #define LOW			0

  37. #define INPUT			0

  38. #define OUTPUT			1

  39. #define INPUT_PULLUP		2

  40. #define INPUT_PULLDOWN		3

  41. #define OUTPUT_OPENDRAIN	4

  42. #define INPUT_DISABLE		5

  43. #define LSBFIRST		0

  44. #define MSBFIRST		1

  45. #define _BV(n)			(1<<(n))

  46. #define CHANGE			4

  47. #define FALLING			2

  48. #define RISING			3

  49. 

  50. 

  51. #if defined(__IMXRT1062__) && defined(ARDUINO_TEENSY40)

  52. 

  53. #define CORE_NUM_TOTAL_PINS	40

  54. #define CORE_NUM_DIGITAL	40

  55. #define CORE_NUM_INTERRUPT	40

  56. #define CORE_NUM_ANALOG		14

  57. #define CORE_NUM_PWM		27

  58. 

  59. #define CORE_PIN0_BIT		3

  60. #define CORE_PIN1_BIT		2

  61. #define CORE_PIN2_BIT		4

  62. #define CORE_PIN3_BIT		5

  63. #define CORE_PIN4_BIT		6

  64. #define CORE_PIN5_BIT		8

  65. #define CORE_PIN6_BIT		10

  66. #define CORE_PIN7_BIT		17

  67. #define CORE_PIN8_BIT		16

  68. #define CORE_PIN9_BIT		11

  69. #define CORE_PIN10_BIT		0

  70. #define CORE_PIN11_BIT		2

  71. #define CORE_PIN12_BIT		1

  72. #define CORE_PIN13_BIT		3

  73. #define CORE_PIN14_BIT		18

  74. #define CORE_PIN15_BIT		19

  75. #define CORE_PIN16_BIT		23

  76. #define CORE_PIN17_BIT		22

  77. #define CORE_PIN18_BIT		17

  78. #define CORE_PIN19_BIT		16

  79. #define CORE_PIN20_BIT		26

  80. #define CORE_PIN21_BIT		27

  81. #define CORE_PIN22_BIT		24

  82. #define CORE_PIN23_BIT		25

  83. #define CORE_PIN24_BIT		12

  84. #define CORE_PIN25_BIT		13

  85. #define CORE_PIN26_BIT		30

  86. #define CORE_PIN27_BIT		31

  87. #define CORE_PIN28_BIT		18

  88. #define CORE_PIN29_BIT		31

  89. #define CORE_PIN30_BIT		23

  90. #define CORE_PIN31_BIT		22

  91. #define CORE_PIN32_BIT		12

  92. #define CORE_PIN33_BIT		7

  93. #define CORE_PIN34_BIT		15

  94. #define CORE_PIN35_BIT		14

  95. #define CORE_PIN36_BIT		13

  96. #define CORE_PIN37_BIT		12

  97. #define CORE_PIN38_BIT		17

  98. #define CORE_PIN39_BIT		16

  99. 

  100. #define CORE_PIN0_BITMASK	(1<<(CORE_PIN0_BIT))

  101. #define CORE_PIN1_BITMASK	(1<<(CORE_PIN1_BIT))

  102. #define CORE_PIN2_BITMASK	(1<<(CORE_PIN2_BIT))

  103. #define CORE_PIN3_BITMASK	(1<<(CORE_PIN3_BIT))

  104. #define CORE_PIN4_BITMASK	(1<<(CORE_PIN4_BIT))

  105. #define CORE_PIN5_BITMASK	(1<<(CORE_PIN5_BIT))

  106. #define CORE_PIN6_BITMASK	(1<<(CORE_PIN6_BIT))

  107. #define CORE_PIN7_BITMASK	(1<<(CORE_PIN7_BIT))

  108. #define CORE_PIN8_BITMASK	(1<<(CORE_PIN8_BIT))

  109. #define CORE_PIN9_BITMASK	(1<<(CORE_PIN9_BIT))

  110. #define CORE_PIN10_BITMASK	(1<<(CORE_PIN10_BIT))

  111. #define CORE_PIN11_BITMASK	(1<<(CORE_PIN11_BIT))

  112. #define CORE_PIN12_BITMASK	(1<<(CORE_PIN12_BIT))

  113. #define CORE_PIN13_BITMASK	(1<<(CORE_PIN13_BIT))

  114. #define CORE_PIN14_BITMASK	(1<<(CORE_PIN14_BIT))

  115. #define CORE_PIN15_BITMASK	(1<<(CORE_PIN15_BIT))

  116. #define CORE_PIN16_BITMASK	(1<<(CORE_PIN16_BIT))

  117. #define CORE_PIN17_BITMASK	(1<<(CORE_PIN17_BIT))

  118. #define CORE_PIN18_BITMASK	(1<<(CORE_PIN18_BIT))

  119. #define CORE_PIN19_BITMASK	(1<<(CORE_PIN19_BIT))

  120. #define CORE_PIN20_BITMASK	(1<<(CORE_PIN20_BIT))

  121. #define CORE_PIN21_BITMASK	(1<<(CORE_PIN21_BIT))

  122. #define CORE_PIN22_BITMASK	(1<<(CORE_PIN22_BIT))

  123. #define CORE_PIN23_BITMASK	(1<<(CORE_PIN23_BIT))

  124. #define CORE_PIN24_BITMASK	(1<<(CORE_PIN24_BIT))

  125. #define CORE_PIN25_BITMASK	(1<<(CORE_PIN25_BIT))

  126. #define CORE_PIN26_BITMASK	(1<<(CORE_PIN26_BIT))

  127. #define CORE_PIN27_BITMASK	(1<<(CORE_PIN27_BIT))

  128. #define CORE_PIN28_BITMASK	(1<<(CORE_PIN28_BIT))

  129. #define CORE_PIN29_BITMASK	(1<<(CORE_PIN29_BIT))

  130. #define CORE_PIN30_BITMASK	(1<<(CORE_PIN30_BIT))

  131. #define CORE_PIN31_BITMASK	(1<<(CORE_PIN31_BIT))

  132. #define CORE_PIN32_BITMASK	(1<<(CORE_PIN32_BIT))

  133. #define CORE_PIN33_BITMASK	(1<<(CORE_PIN33_BIT))

  134. #define CORE_PIN34_BITMASK	(1<<(CORE_PIN34_BIT))

  135. #define CORE_PIN35_BITMASK	(1<<(CORE_PIN35_BIT))

  136. #define CORE_PIN36_BITMASK	(1<<(CORE_PIN36_BIT))

  137. #define CORE_PIN37_BITMASK	(1<<(CORE_PIN37_BIT))

  138. #define CORE_PIN38_BITMASK	(1<<(CORE_PIN38_BIT))

  139. #define CORE_PIN39_BITMASK	(1<<(CORE_PIN39_BIT))

  140. 

  141. 

  142. // Fast GPIO

  143. #define CORE_PIN0_PORTREG	GPIO6_DR

  144. #define CORE_PIN1_PORTREG	GPIO6_DR

  145. #define CORE_PIN2_PORTREG	GPIO9_DR

  146. #define CORE_PIN3_PORTREG	GPIO9_DR

  147. #define CORE_PIN4_PORTREG	GPIO9_DR

  148. #define CORE_PIN5_PORTREG	GPIO9_DR

  149. #define CORE_PIN6_PORTREG	GPIO7_DR

  150. #define CORE_PIN7_PORTREG	GPIO7_DR

  151. #define CORE_PIN8_PORTREG	GPIO7_DR

  152. #define CORE_PIN9_PORTREG	GPIO7_DR

  153. #define CORE_PIN10_PORTREG	GPIO7_DR

  154. #define CORE_PIN11_PORTREG	GPIO7_DR

  155. #define CORE_PIN12_PORTREG	GPIO7_DR

  156. #define CORE_PIN13_PORTREG	GPIO7_DR

  157. #define CORE_PIN14_PORTREG	GPIO6_DR

  158. #define CORE_PIN15_PORTREG	GPIO6_DR

  159. #define CORE_PIN16_PORTREG	GPIO6_DR

  160. #define CORE_PIN17_PORTREG	GPIO6_DR

  161. #define CORE_PIN18_PORTREG	GPIO6_DR

  162. #define CORE_PIN19_PORTREG	GPIO6_DR

  163. #define CORE_PIN20_PORTREG	GPIO6_DR

  164. #define CORE_PIN21_PORTREG	GPIO6_DR

  165. #define CORE_PIN22_PORTREG	GPIO6_DR

  166. #define CORE_PIN23_PORTREG	GPIO6_DR

  167. #define CORE_PIN24_PORTREG	GPIO6_DR

  168. #define CORE_PIN25_PORTREG	GPIO6_DR

  169. #define CORE_PIN26_PORTREG	GPIO6_DR

  170. #define CORE_PIN27_PORTREG	GPIO6_DR

  171. #define CORE_PIN28_PORTREG	GPIO8_DR

  172. #define CORE_PIN29_PORTREG	GPIO9_DR

  173. #define CORE_PIN30_PORTREG	GPIO8_DR

  174. #define CORE_PIN31_PORTREG	GPIO8_DR

  175. #define CORE_PIN32_PORTREG	GPIO7_DR

  176. #define CORE_PIN33_PORTREG	GPIO9_DR

  177. #define CORE_PIN34_PORTREG	GPIO8_DR

  178. #define CORE_PIN35_PORTREG	GPIO8_DR

  179. #define CORE_PIN36_PORTREG	GPIO8_DR

  180. #define CORE_PIN37_PORTREG	GPIO8_DR

  181. #define CORE_PIN38_PORTREG	GPIO8_DR

  182. #define CORE_PIN39_PORTREG	GPIO8_DR

  183. 

  184. #define CORE_PIN0_PORTSET	GPIO6_DR_SET

  185. #define CORE_PIN1_PORTSET	GPIO6_DR_SET

  186. #define CORE_PIN2_PORTSET	GPIO9_DR_SET

  187. #define CORE_PIN3_PORTSET	GPIO9_DR_SET

  188. #define CORE_PIN4_PORTSET	GPIO9_DR_SET

  189. #define CORE_PIN5_PORTSET	GPIO9_DR_SET

  190. #define CORE_PIN6_PORTSET	GPIO7_DR_SET

  191. #define CORE_PIN7_PORTSET	GPIO7_DR_SET

  192. #define CORE_PIN8_PORTSET	GPIO7_DR_SET

  193. #define CORE_PIN9_PORTSET	GPIO7_DR_SET

  194. #define CORE_PIN10_PORTSET	GPIO7_DR_SET

  195. #define CORE_PIN11_PORTSET	GPIO7_DR_SET

  196. #define CORE_PIN12_PORTSET	GPIO7_DR_SET

  197. #define CORE_PIN13_PORTSET	GPIO7_DR_SET

  198. #define CORE_PIN14_PORTSET	GPIO6_DR_SET

  199. #define CORE_PIN15_PORTSET	GPIO6_DR_SET

  200. #define CORE_PIN16_PORTSET	GPIO6_DR_SET

  201. #define CORE_PIN17_PORTSET	GPIO6_DR_SET

  202. #define CORE_PIN18_PORTSET	GPIO6_DR_SET

  203. #define CORE_PIN19_PORTSET	GPIO6_DR_SET

  204. #define CORE_PIN20_PORTSET	GPIO6_DR_SET

  205. #define CORE_PIN21_PORTSET	GPIO6_DR_SET

  206. #define CORE_PIN22_PORTSET	GPIO6_DR_SET

  207. #define CORE_PIN23_PORTSET	GPIO6_DR_SET

  208. #define CORE_PIN24_PORTSET	GPIO6_DR_SET

  209. #define CORE_PIN25_PORTSET	GPIO6_DR_SET

  210. #define CORE_PIN26_PORTSET	GPIO6_DR_SET

  211. #define CORE_PIN27_PORTSET	GPIO6_DR_SET

  212. #define CORE_PIN28_PORTSET	GPIO8_DR_SET

  213. #define CORE_PIN29_PORTSET	GPIO9_DR_SET

  214. #define CORE_PIN30_PORTSET	GPIO8_DR_SET

  215. #define CORE_PIN31_PORTSET	GPIO8_DR_SET

  216. #define CORE_PIN32_PORTSET	GPIO7_DR_SET

  217. #define CORE_PIN33_PORTSET	GPIO9_DR_SET

  218. #define CORE_PIN34_PORTSET	GPIO8_DR_SET

  219. #define CORE_PIN35_PORTSET	GPIO8_DR_SET

  220. #define CORE_PIN36_PORTSET	GPIO8_DR_SET

  221. #define CORE_PIN37_PORTSET	GPIO8_DR_SET

  222. #define CORE_PIN38_PORTSET	GPIO8_DR_SET

  223. #define CORE_PIN39_PORTSET	GPIO8_DR_SET

  224. 

  225. #define CORE_PIN0_PORTCLEAR	GPIO6_DR_CLEAR

  226. #define CORE_PIN1_PORTCLEAR	GPIO6_DR_CLEAR

  227. #define CORE_PIN2_PORTCLEAR	GPIO9_DR_CLEAR

  228. #define CORE_PIN3_PORTCLEAR	GPIO9_DR_CLEAR

  229. #define CORE_PIN4_PORTCLEAR	GPIO9_DR_CLEAR

  230. #define CORE_PIN5_PORTCLEAR	GPIO9_DR_CLEAR

  231. #define CORE_PIN6_PORTCLEAR	GPIO7_DR_CLEAR

  232. #define CORE_PIN7_PORTCLEAR	GPIO7_DR_CLEAR

  233. #define CORE_PIN8_PORTCLEAR	GPIO7_DR_CLEAR

  234. #define CORE_PIN9_PORTCLEAR	GPIO7_DR_CLEAR

  235. #define CORE_PIN10_PORTCLEAR	GPIO7_DR_CLEAR

  236. #define CORE_PIN11_PORTCLEAR	GPIO7_DR_CLEAR

  237. #define CORE_PIN12_PORTCLEAR	GPIO7_DR_CLEAR

  238. #define CORE_PIN13_PORTCLEAR	GPIO7_DR_CLEAR

  239. #define CORE_PIN14_PORTCLEAR	GPIO6_DR_CLEAR

  240. #define CORE_PIN15_PORTCLEAR	GPIO6_DR_CLEAR

  241. #define CORE_PIN16_PORTCLEAR	GPIO6_DR_CLEAR

  242. #define CORE_PIN17_PORTCLEAR	GPIO6_DR_CLEAR

  243. #define CORE_PIN18_PORTCLEAR	GPIO6_DR_CLEAR

  244. #define CORE_PIN19_PORTCLEAR	GPIO6_DR_CLEAR

  245. #define CORE_PIN20_PORTCLEAR	GPIO6_DR_CLEAR

  246. #define CORE_PIN21_PORTCLEAR	GPIO6_DR_CLEAR

  247. #define CORE_PIN22_PORTCLEAR	GPIO6_DR_CLEAR

  248. #define CORE_PIN23_PORTCLEAR	GPIO6_DR_CLEAR

  249. #define CORE_PIN24_PORTCLEAR	GPIO6_DR_CLEAR

  250. #define CORE_PIN25_PORTCLEAR	GPIO6_DR_CLEAR

  251. #define CORE_PIN26_PORTCLEAR	GPIO6_DR_CLEAR

  252. #define CORE_PIN27_PORTCLEAR	GPIO6_DR_CLEAR

  253. #define CORE_PIN28_PORTCLEAR	GPIO8_DR_CLEAR

  254. #define CORE_PIN29_PORTCLEAR	GPIO9_DR_CLEAR

  255. #define CORE_PIN30_PORTCLEAR	GPIO8_DR_CLEAR

  256. #define CORE_PIN31_PORTCLEAR	GPIO8_DR_CLEAR

  257. #define CORE_PIN32_PORTCLEAR	GPIO7_DR_CLEAR

  258. #define CORE_PIN33_PORTCLEAR	GPIO9_DR_CLEAR

  259. #define CORE_PIN34_PORTCLEAR	GPIO8_DR_CLEAR

  260. #define CORE_PIN35_PORTCLEAR	GPIO8_DR_CLEAR

  261. #define CORE_PIN36_PORTCLEAR	GPIO8_DR_CLEAR

  262. #define CORE_PIN37_PORTCLEAR	GPIO8_DR_CLEAR

  263. #define CORE_PIN38_PORTCLEAR	GPIO8_DR_CLEAR

  264. #define CORE_PIN39_PORTCLEAR	GPIO8_DR_CLEAR

  265. 

  266. #define CORE_PIN0_DDRREG	GPIO6_GDIR

  267. #define CORE_PIN1_DDRREG	GPIO6_GDIR

  268. #define CORE_PIN2_DDRREG	GPIO9_GDIR

  269. #define CORE_PIN3_DDRREG	GPIO9_GDIR

  270. #define CORE_PIN4_DDRREG	GPIO9_GDIR

  271. #define CORE_PIN5_DDRREG	GPIO9_GDIR

  272. #define CORE_PIN6_DDRREG	GPIO7_GDIR

  273. #define CORE_PIN7_DDRREG	GPIO7_GDIR

  274. #define CORE_PIN8_DDRREG	GPIO7_GDIR

  275. #define CORE_PIN9_DDRREG	GPIO7_GDIR

  276. #define CORE_PIN10_DDRREG	GPIO7_GDIR

  277. #define CORE_PIN11_DDRREG	GPIO7_GDIR

  278. #define CORE_PIN12_DDRREG	GPIO7_GDIR

  279. #define CORE_PIN13_DDRREG	GPIO7_GDIR

  280. #define CORE_PIN14_DDRREG	GPIO6_GDIR

  281. #define CORE_PIN15_DDRREG	GPIO6_GDIR

  282. #define CORE_PIN16_DDRREG	GPIO6_GDIR

  283. #define CORE_PIN17_DDRREG	GPIO6_GDIR

  284. #define CORE_PIN18_DDRREG	GPIO6_GDIR

  285. #define CORE_PIN19_DDRREG	GPIO6_GDIR

  286. #define CORE_PIN20_DDRREG	GPIO6_GDIR

  287. #define CORE_PIN21_DDRREG	GPIO6_GDIR

  288. #define CORE_PIN22_DDRREG	GPIO6_GDIR

  289. #define CORE_PIN23_DDRREG	GPIO6_GDIR

  290. #define CORE_PIN24_DDRREG	GPIO6_GDIR

  291. #define CORE_PIN25_DDRREG	GPIO6_GDIR

  292. #define CORE_PIN26_DDRREG	GPIO6_GDIR

  293. #define CORE_PIN27_DDRREG	GPIO6_GDIR

  294. #define CORE_PIN28_DDRREG	GPIO8_GDIR

  295. #define CORE_PIN29_DDRREG	GPIO9_GDIR

  296. #define CORE_PIN30_DDRREG	GPIO8_GDIR

  297. #define CORE_PIN31_DDRREG	GPIO8_GDIR

  298. #define CORE_PIN32_DDRREG	GPIO7_GDIR

  299. #define CORE_PIN33_DDRREG	GPIO9_GDIR

  300. #define CORE_PIN34_DDRREG	GPIO8_GDIR

  301. #define CORE_PIN35_DDRREG	GPIO8_GDIR

  302. #define CORE_PIN36_DDRREG	GPIO8_GDIR

  303. #define CORE_PIN37_DDRREG	GPIO8_GDIR

  304. #define CORE_PIN38_DDRREG	GPIO8_GDIR

  305. #define CORE_PIN39_DDRREG	GPIO8_GDIR

  306. 

  307. #define CORE_PIN0_PINREG	GPIO6_PSR

  308. #define CORE_PIN1_PINREG	GPIO6_PSR

  309. #define CORE_PIN2_PINREG	GPIO9_PSR

  310. #define CORE_PIN3_PINREG	GPIO9_PSR

  311. #define CORE_PIN4_PINREG	GPIO9_PSR

  312. #define CORE_PIN5_PINREG	GPIO9_PSR

  313. #define CORE_PIN6_PINREG	GPIO7_PSR

  314. #define CORE_PIN7_PINREG	GPIO7_PSR

  315. #define CORE_PIN8_PINREG	GPIO7_PSR

  316. #define CORE_PIN9_PINREG	GPIO7_PSR

  317. #define CORE_PIN10_PINREG	GPIO7_PSR

  318. #define CORE_PIN11_PINREG	GPIO7_PSR

  319. #define CORE_PIN12_PINREG	GPIO7_PSR

  320. #define CORE_PIN13_PINREG	GPIO7_PSR

  321. #define CORE_PIN14_PINREG	GPIO6_PSR

  322. #define CORE_PIN15_PINREG	GPIO6_PSR

  323. #define CORE_PIN16_PINREG	GPIO6_PSR

  324. #define CORE_PIN17_PINREG	GPIO6_PSR

  325. #define CORE_PIN18_PINREG	GPIO6_PSR

  326. #define CORE_PIN19_PINREG	GPIO6_PSR

  327. #define CORE_PIN20_PINREG	GPIO6_PSR

  328. #define CORE_PIN21_PINREG	GPIO6_PSR

  329. #define CORE_PIN22_PINREG	GPIO6_PSR

  330. #define CORE_PIN23_PINREG	GPIO6_PSR

  331. #define CORE_PIN24_PINREG	GPIO6_PSR

  332. #define CORE_PIN25_PINREG	GPIO6_PSR

  333. #define CORE_PIN26_PINREG	GPIO6_PSR

  334. #define CORE_PIN27_PINREG	GPIO6_PSR

  335. #define CORE_PIN28_PINREG	GPIO8_PSR

  336. #define CORE_PIN29_PINREG	GPIO9_PSR

  337. #define CORE_PIN30_PINREG	GPIO8_PSR

  338. #define CORE_PIN31_PINREG	GPIO8_PSR

  339. #define CORE_PIN32_PINREG	GPIO7_PSR

  340. #define CORE_PIN33_PINREG	GPIO9_PSR

  341. #define CORE_PIN34_PINREG	GPIO8_PSR

  342. #define CORE_PIN35_PINREG	GPIO8_PSR

  343. #define CORE_PIN36_PINREG	GPIO8_PSR

  344. #define CORE_PIN37_PINREG	GPIO8_PSR

  345. #define CORE_PIN38_PINREG	GPIO8_PSR

  346. #define CORE_PIN39_PINREG	GPIO8_PSR

  347. 

  348. 

  349. 

  350. // mux config registers control which peripheral uses the pin

  351. #define CORE_PIN0_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03

  352. #define CORE_PIN1_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02

  353. #define CORE_PIN2_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04

  354. #define CORE_PIN3_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05

  355. #define CORE_PIN4_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06

  356. #define CORE_PIN5_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08

  357. #define CORE_PIN6_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10

  358. #define CORE_PIN7_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01

  359. #define CORE_PIN8_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00

  360. #define CORE_PIN9_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11

  361. #define CORE_PIN10_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00

  362. #define CORE_PIN11_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02

  363. #define CORE_PIN12_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01

  364. #define CORE_PIN13_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03

  365. #define CORE_PIN14_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02

  366. #define CORE_PIN15_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03

  367. #define CORE_PIN16_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07

  368. #define CORE_PIN17_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06

  369. #define CORE_PIN18_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01

  370. #define CORE_PIN19_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00

  371. #define CORE_PIN20_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10

  372. #define CORE_PIN21_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11

  373. #define CORE_PIN22_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08

  374. #define CORE_PIN23_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09

  375. #define CORE_PIN24_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12

  376. #define CORE_PIN25_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13

  377. #define CORE_PIN26_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14

  378. #define CORE_PIN27_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15

  379. #define CORE_PIN28_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32

  380. #define CORE_PIN29_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31

  381. #define CORE_PIN30_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37

  382. #define CORE_PIN31_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36

  383. #define CORE_PIN32_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12

  384. #define CORE_PIN33_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07

  385. #define CORE_PIN34_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03

  386. #define CORE_PIN35_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02

  387. #define CORE_PIN36_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01

  388. #define CORE_PIN37_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00

  389. #define CORE_PIN38_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05

  390. #define CORE_PIN39_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04

  391. 

  392. // pad config registers control pullup/pulldown/keeper, drive strength, etc

  393. #define CORE_PIN0_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03

  394. #define CORE_PIN1_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02

  395. #define CORE_PIN2_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04

  396. #define CORE_PIN3_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05

  397. #define CORE_PIN4_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06

  398. #define CORE_PIN5_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08

  399. #define CORE_PIN6_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10

  400. #define CORE_PIN7_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01

  401. #define CORE_PIN8_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00

  402. #define CORE_PIN9_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11

  403. #define CORE_PIN10_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00

  404. #define CORE_PIN11_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02

  405. #define CORE_PIN12_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01

  406. #define CORE_PIN13_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03

  407. #define CORE_PIN14_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02

  408. #define CORE_PIN15_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03

  409. #define CORE_PIN16_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07

  410. #define CORE_PIN17_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06

  411. #define CORE_PIN18_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01

  412. #define CORE_PIN19_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00

  413. #define CORE_PIN20_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10

  414. #define CORE_PIN21_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11

  415. #define CORE_PIN22_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08

  416. #define CORE_PIN23_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09

  417. #define CORE_PIN24_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12

  418. #define CORE_PIN25_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13

  419. #define CORE_PIN26_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14

  420. #define CORE_PIN27_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15

  421. #define CORE_PIN28_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32

  422. #define CORE_PIN29_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31

  423. #define CORE_PIN30_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37

  424. #define CORE_PIN31_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36

  425. #define CORE_PIN32_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12

  426. #define CORE_PIN33_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07

  427. #define CORE_PIN34_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03

  428. #define CORE_PIN35_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02

  429. #define CORE_PIN36_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01

  430. #define CORE_PIN37_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00

  431. #define CORE_PIN38_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05

  432. #define CORE_PIN39_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04

  433. 

  434. #define CORE_LED0_PIN		13

  435. 

  436. #define CORE_ADC0_PIN		14

  437. #define CORE_ADC1_PIN		15

  438. #define CORE_ADC2_PIN		16

  439. #define CORE_ADC3_PIN		17

  440. #define CORE_ADC4_PIN		18

  441. #define CORE_ADC5_PIN		19

  442. #define CORE_ADC6_PIN		20

  443. #define CORE_ADC7_PIN		21

  444. #define CORE_ADC8_PIN		22

  445. #define CORE_ADC9_PIN		23

  446. 

  447. #define CORE_RXD0_PIN		0

  448. #define CORE_TXD0_PIN		1

  449. #define CORE_RXD1_PIN		7

  450. #define CORE_TXD1_PIN		8

  451. #define CORE_RXD2_PIN		15

  452. #define CORE_TXD2_PIN		14

  453. #define CORE_RXD3_PIN		16

  454. #define CORE_TXD3_PIN		17

  455. #define CORE_RXD4_PIN		21

  456. #define CORE_TXD4_PIN		20

  457. #define CORE_RXD5_PIN		25

  458. #define CORE_TXD5_PIN		24

  459. #define CORE_RXD6_PIN		28

  460. #define CORE_TXD6_PIN		29

  461. 

  462. #define CORE_INT0_PIN		0

  463. #define CORE_INT1_PIN		1

  464. #define CORE_INT2_PIN		2

  465. #define CORE_INT3_PIN		3

  466. #define CORE_INT4_PIN		4

  467. #define CORE_INT5_PIN		5

  468. #define CORE_INT6_PIN		6

  469. #define CORE_INT7_PIN		7

  470. #define CORE_INT8_PIN		8

  471. #define CORE_INT9_PIN		9

  472. #define CORE_INT10_PIN		10

  473. #define CORE_INT11_PIN		11

  474. #define CORE_INT12_PIN		12

  475. #define CORE_INT13_PIN		13

  476. #define CORE_INT14_PIN		14

  477. #define CORE_INT15_PIN		15

  478. #define CORE_INT16_PIN		16

  479. #define CORE_INT17_PIN		17

  480. #define CORE_INT18_PIN		18

  481. #define CORE_INT19_PIN		19

  482. #define CORE_INT20_PIN		20

  483. #define CORE_INT21_PIN		21

  484. #define CORE_INT22_PIN		22

  485. #define CORE_INT23_PIN		23

  486. #define CORE_INT24_PIN		24

  487. #define CORE_INT25_PIN		25

  488. #define CORE_INT26_PIN		26

  489. #define CORE_INT27_PIN		27

  490. #define CORE_INT28_PIN		28

  491. #define CORE_INT29_PIN		29

  492. #define CORE_INT30_PIN		30

  493. #define CORE_INT31_PIN		31

  494. #define CORE_INT32_PIN		32

  495. #define CORE_INT33_PIN		33

  496. #define CORE_INT34_PIN		34

  497. #define CORE_INT35_PIN		35

  498. #define CORE_INT36_PIN		36

  499. #define CORE_INT37_PIN		37

  500. #define CORE_INT38_PIN		38

  501. #define CORE_INT39_PIN		39

  502. #define CORE_INT_EVERY_PIN	1

  503. 

  504. 

  505. 

  506. 

  507. 

  508. #elif defined(__IMXRT1062__) && defined(ARDUINO_TEENSY41)

  509. 

  510. #define CORE_NUM_TOTAL_PINS	55

  511. #define CORE_NUM_DIGITAL	55

  512. #define CORE_NUM_INTERRUPT	55

  513. #define CORE_NUM_ANALOG		18

  514. #define CORE_NUM_PWM		31

  515. 

  516. #define CORE_PIN0_BIT		3

  517. #define CORE_PIN1_BIT		2

  518. #define CORE_PIN2_BIT		4

  519. #define CORE_PIN3_BIT		5

  520. #define CORE_PIN4_BIT		6

  521. #define CORE_PIN5_BIT		8

  522. #define CORE_PIN6_BIT		10

  523. #define CORE_PIN7_BIT		17

  524. #define CORE_PIN8_BIT		16

  525. #define CORE_PIN9_BIT		11

  526. #define CORE_PIN10_BIT		0

  527. #define CORE_PIN11_BIT		2

  528. #define CORE_PIN12_BIT		1

  529. #define CORE_PIN13_BIT		3

  530. #define CORE_PIN14_BIT		18

  531. #define CORE_PIN15_BIT		19

  532. #define CORE_PIN16_BIT		23

  533. #define CORE_PIN17_BIT		22

  534. #define CORE_PIN18_BIT		17

  535. #define CORE_PIN19_BIT		16

  536. #define CORE_PIN20_BIT		26

  537. #define CORE_PIN21_BIT		27

  538. #define CORE_PIN22_BIT		24

  539. #define CORE_PIN23_BIT		25

  540. #define CORE_PIN24_BIT		12

  541. #define CORE_PIN25_BIT		13

  542. #define CORE_PIN26_BIT		30

  543. #define CORE_PIN27_BIT		31

  544. #define CORE_PIN28_BIT		18

  545. #define CORE_PIN29_BIT		31

  546. #define CORE_PIN30_BIT		23

  547. #define CORE_PIN31_BIT		22

  548. #define CORE_PIN32_BIT		12

  549. #define CORE_PIN33_BIT		7

  550. #define CORE_PIN34_BIT		29

  551. #define CORE_PIN35_BIT		28

  552. #define CORE_PIN36_BIT		18

  553. #define CORE_PIN37_BIT		19

  554. #define CORE_PIN38_BIT		28

  555. #define CORE_PIN39_BIT		29

  556. #define CORE_PIN40_BIT		20

  557. #define CORE_PIN41_BIT		21

  558. #define CORE_PIN42_BIT		15

  559. #define CORE_PIN43_BIT		14

  560. #define CORE_PIN44_BIT		13

  561. #define CORE_PIN45_BIT		12

  562. #define CORE_PIN46_BIT		17

  563. #define CORE_PIN47_BIT		16

  564. #define CORE_PIN48_BIT		24

  565. #define CORE_PIN49_BIT		27

  566. #define CORE_PIN50_BIT		28

  567. #define CORE_PIN51_BIT		22

  568. #define CORE_PIN52_BIT		26

  569. #define CORE_PIN53_BIT		25

  570. #define CORE_PIN54_BIT		29

  571. 

  572. #define CORE_PIN0_BITMASK	(1<<(CORE_PIN0_BIT))

  573. #define CORE_PIN1_BITMASK	(1<<(CORE_PIN1_BIT))

  574. #define CORE_PIN2_BITMASK	(1<<(CORE_PIN2_BIT))

  575. #define CORE_PIN3_BITMASK	(1<<(CORE_PIN3_BIT))

  576. #define CORE_PIN4_BITMASK	(1<<(CORE_PIN4_BIT))

  577. #define CORE_PIN5_BITMASK	(1<<(CORE_PIN5_BIT))

  578. #define CORE_PIN6_BITMASK	(1<<(CORE_PIN6_BIT))

  579. #define CORE_PIN7_BITMASK	(1<<(CORE_PIN7_BIT))

  580. #define CORE_PIN8_BITMASK	(1<<(CORE_PIN8_BIT))

  581. #define CORE_PIN9_BITMASK	(1<<(CORE_PIN9_BIT))

  582. #define CORE_PIN10_BITMASK	(1<<(CORE_PIN10_BIT))

  583. #define CORE_PIN11_BITMASK	(1<<(CORE_PIN11_BIT))

  584. #define CORE_PIN12_BITMASK	(1<<(CORE_PIN12_BIT))

  585. #define CORE_PIN13_BITMASK	(1<<(CORE_PIN13_BIT))

  586. #define CORE_PIN14_BITMASK	(1<<(CORE_PIN14_BIT))

  587. #define CORE_PIN15_BITMASK	(1<<(CORE_PIN15_BIT))

  588. #define CORE_PIN16_BITMASK	(1<<(CORE_PIN16_BIT))

  589. #define CORE_PIN17_BITMASK	(1<<(CORE_PIN17_BIT))

  590. #define CORE_PIN18_BITMASK	(1<<(CORE_PIN18_BIT))

  591. #define CORE_PIN19_BITMASK	(1<<(CORE_PIN19_BIT))

  592. #define CORE_PIN20_BITMASK	(1<<(CORE_PIN20_BIT))

  593. #define CORE_PIN21_BITMASK	(1<<(CORE_PIN21_BIT))

  594. #define CORE_PIN22_BITMASK	(1<<(CORE_PIN22_BIT))

  595. #define CORE_PIN23_BITMASK	(1<<(CORE_PIN23_BIT))

  596. #define CORE_PIN24_BITMASK	(1<<(CORE_PIN24_BIT))

  597. #define CORE_PIN25_BITMASK	(1<<(CORE_PIN25_BIT))

  598. #define CORE_PIN26_BITMASK	(1<<(CORE_PIN26_BIT))

  599. #define CORE_PIN27_BITMASK	(1<<(CORE_PIN27_BIT))

  600. #define CORE_PIN28_BITMASK	(1<<(CORE_PIN28_BIT))

  601. #define CORE_PIN29_BITMASK	(1<<(CORE_PIN29_BIT))

  602. #define CORE_PIN30_BITMASK	(1<<(CORE_PIN30_BIT))

  603. #define CORE_PIN31_BITMASK	(1<<(CORE_PIN31_BIT))

  604. #define CORE_PIN32_BITMASK	(1<<(CORE_PIN32_BIT))

  605. #define CORE_PIN33_BITMASK	(1<<(CORE_PIN33_BIT))

  606. #define CORE_PIN34_BITMASK	(1<<(CORE_PIN34_BIT))

  607. #define CORE_PIN35_BITMASK	(1<<(CORE_PIN35_BIT))

  608. #define CORE_PIN36_BITMASK	(1<<(CORE_PIN36_BIT))

  609. #define CORE_PIN37_BITMASK	(1<<(CORE_PIN37_BIT))

  610. #define CORE_PIN38_BITMASK	(1<<(CORE_PIN38_BIT))

  611. #define CORE_PIN39_BITMASK	(1<<(CORE_PIN39_BIT))

  612. #define CORE_PIN40_BITMASK	(1<<(CORE_PIN40_BIT))

  613. #define CORE_PIN41_BITMASK	(1<<(CORE_PIN41_BIT))

  614. #define CORE_PIN42_BITMASK	(1<<(CORE_PIN42_BIT))

  615. #define CORE_PIN43_BITMASK	(1<<(CORE_PIN43_BIT))

  616. #define CORE_PIN44_BITMASK	(1<<(CORE_PIN44_BIT))

  617. #define CORE_PIN45_BITMASK	(1<<(CORE_PIN45_BIT))

  618. #define CORE_PIN46_BITMASK	(1<<(CORE_PIN46_BIT))

  619. #define CORE_PIN47_BITMASK	(1<<(CORE_PIN47_BIT))

  620. #define CORE_PIN48_BITMASK	(1<<(CORE_PIN48_BIT))

  621. #define CORE_PIN49_BITMASK	(1<<(CORE_PIN49_BIT))

  622. #define CORE_PIN50_BITMASK	(1<<(CORE_PIN50_BIT))

  623. #define CORE_PIN51_BITMASK	(1<<(CORE_PIN51_BIT))

  624. #define CORE_PIN52_BITMASK	(1<<(CORE_PIN52_BIT))

  625. #define CORE_PIN53_BITMASK	(1<<(CORE_PIN53_BIT))

  626. #define CORE_PIN54_BITMASK	(1<<(CORE_PIN54_BIT))

  627. 

  628. // Fast GPIO

  629. #define CORE_PIN0_PORTREG	GPIO6_DR

  630. #define CORE_PIN1_PORTREG	GPIO6_DR

  631. #define CORE_PIN2_PORTREG	GPIO9_DR

  632. #define CORE_PIN3_PORTREG	GPIO9_DR

  633. #define CORE_PIN4_PORTREG	GPIO9_DR

  634. #define CORE_PIN5_PORTREG	GPIO9_DR

  635. #define CORE_PIN6_PORTREG	GPIO7_DR

  636. #define CORE_PIN7_PORTREG	GPIO7_DR

  637. #define CORE_PIN8_PORTREG	GPIO7_DR

  638. #define CORE_PIN9_PORTREG	GPIO7_DR

  639. #define CORE_PIN10_PORTREG	GPIO7_DR

  640. #define CORE_PIN11_PORTREG	GPIO7_DR

  641. #define CORE_PIN12_PORTREG	GPIO7_DR

  642. #define CORE_PIN13_PORTREG	GPIO7_DR

  643. #define CORE_PIN14_PORTREG	GPIO6_DR

  644. #define CORE_PIN15_PORTREG	GPIO6_DR

  645. #define CORE_PIN16_PORTREG	GPIO6_DR

  646. #define CORE_PIN17_PORTREG	GPIO6_DR

  647. #define CORE_PIN18_PORTREG	GPIO6_DR

  648. #define CORE_PIN19_PORTREG	GPIO6_DR

  649. #define CORE_PIN20_PORTREG	GPIO6_DR

  650. #define CORE_PIN21_PORTREG	GPIO6_DR

  651. #define CORE_PIN22_PORTREG	GPIO6_DR

  652. #define CORE_PIN23_PORTREG	GPIO6_DR

  653. #define CORE_PIN24_PORTREG	GPIO6_DR

  654. #define CORE_PIN25_PORTREG	GPIO6_DR

  655. #define CORE_PIN26_PORTREG	GPIO6_DR

  656. #define CORE_PIN27_PORTREG	GPIO6_DR

  657. #define CORE_PIN28_PORTREG	GPIO8_DR

  658. #define CORE_PIN29_PORTREG	GPIO9_DR

  659. #define CORE_PIN30_PORTREG	GPIO8_DR

  660. #define CORE_PIN31_PORTREG	GPIO8_DR

  661. #define CORE_PIN32_PORTREG	GPIO7_DR

  662. #define CORE_PIN33_PORTREG	GPIO9_DR

  663. #define CORE_PIN34_PORTREG	GPIO7_DR

  664. #define CORE_PIN35_PORTREG	GPIO7_DR

  665. #define CORE_PIN36_PORTREG	GPIO7_DR

  666. #define CORE_PIN37_PORTREG	GPIO7_DR

  667. #define CORE_PIN38_PORTREG	GPIO6_DR

  668. #define CORE_PIN39_PORTREG	GPIO6_DR

  669. #define CORE_PIN40_PORTREG	GPIO6_DR

  670. #define CORE_PIN41_PORTREG	GPIO6_DR

  671. #define CORE_PIN42_PORTREG	GPIO8_DR

  672. #define CORE_PIN43_PORTREG	GPIO8_DR

  673. #define CORE_PIN44_PORTREG	GPIO8_DR

  674. #define CORE_PIN45_PORTREG	GPIO8_DR

  675. #define CORE_PIN46_PORTREG	GPIO8_DR

  676. #define CORE_PIN47_PORTREG	GPIO8_DR

  677. #define CORE_PIN48_PORTREG	GPIO9_DR

  678. #define CORE_PIN49_PORTREG	GPIO9_DR

  679. #define CORE_PIN50_PORTREG	GPIO9_DR

  680. #define CORE_PIN51_PORTREG	GPIO9_DR

  681. #define CORE_PIN52_PORTREG	GPIO9_DR

  682. #define CORE_PIN53_PORTREG	GPIO9_DR

  683. #define CORE_PIN54_PORTREG	GPIO9_DR

  684. 

  685. #define CORE_PIN0_PORTSET	GPIO6_DR_SET

  686. #define CORE_PIN1_PORTSET	GPIO6_DR_SET

  687. #define CORE_PIN2_PORTSET	GPIO9_DR_SET

  688. #define CORE_PIN3_PORTSET	GPIO9_DR_SET

  689. #define CORE_PIN4_PORTSET	GPIO9_DR_SET

  690. #define CORE_PIN5_PORTSET	GPIO9_DR_SET

  691. #define CORE_PIN6_PORTSET	GPIO7_DR_SET

  692. #define CORE_PIN7_PORTSET	GPIO7_DR_SET

  693. #define CORE_PIN8_PORTSET	GPIO7_DR_SET

  694. #define CORE_PIN9_PORTSET	GPIO7_DR_SET

  695. #define CORE_PIN10_PORTSET	GPIO7_DR_SET

  696. #define CORE_PIN11_PORTSET	GPIO7_DR_SET

  697. #define CORE_PIN12_PORTSET	GPIO7_DR_SET

  698. #define CORE_PIN13_PORTSET	GPIO7_DR_SET

  699. #define CORE_PIN14_PORTSET	GPIO6_DR_SET

  700. #define CORE_PIN15_PORTSET	GPIO6_DR_SET

  701. #define CORE_PIN16_PORTSET	GPIO6_DR_SET

  702. #define CORE_PIN17_PORTSET	GPIO6_DR_SET

  703. #define CORE_PIN18_PORTSET	GPIO6_DR_SET

  704. #define CORE_PIN19_PORTSET	GPIO6_DR_SET

  705. #define CORE_PIN20_PORTSET	GPIO6_DR_SET

  706. #define CORE_PIN21_PORTSET	GPIO6_DR_SET

  707. #define CORE_PIN22_PORTSET	GPIO6_DR_SET

  708. #define CORE_PIN23_PORTSET	GPIO6_DR_SET

  709. #define CORE_PIN24_PORTSET	GPIO6_DR_SET

  710. #define CORE_PIN25_PORTSET	GPIO6_DR_SET

  711. #define CORE_PIN26_PORTSET	GPIO6_DR_SET

  712. #define CORE_PIN27_PORTSET	GPIO6_DR_SET

  713. #define CORE_PIN28_PORTSET	GPIO8_DR_SET

  714. #define CORE_PIN29_PORTSET	GPIO9_DR_SET

  715. #define CORE_PIN30_PORTSET	GPIO8_DR_SET

  716. #define CORE_PIN31_PORTSET	GPIO8_DR_SET

  717. #define CORE_PIN32_PORTSET	GPIO7_DR_SET

  718. #define CORE_PIN33_PORTSET	GPIO9_DR_SET

  719. #define CORE_PIN34_PORTSET	GPIO7_DR_SET

  720. #define CORE_PIN35_PORTSET	GPIO7_DR_SET

  721. #define CORE_PIN36_PORTSET	GPIO7_DR_SET

  722. #define CORE_PIN37_PORTSET	GPIO7_DR_SET

  723. #define CORE_PIN38_PORTSET	GPIO6_DR_SET

  724. #define CORE_PIN39_PORTSET	GPIO6_DR_SET

  725. #define CORE_PIN40_PORTSET	GPIO6_DR_SET

  726. #define CORE_PIN41_PORTSET	GPIO6_DR_SET

  727. #define CORE_PIN42_PORTSET	GPIO8_DR_SET

  728. #define CORE_PIN43_PORTSET	GPIO8_DR_SET

  729. #define CORE_PIN44_PORTSET	GPIO8_DR_SET

  730. #define CORE_PIN45_PORTSET	GPIO8_DR_SET

  731. #define CORE_PIN46_PORTSET	GPIO8_DR_SET

  732. #define CORE_PIN47_PORTSET	GPIO8_DR_SET

  733. #define CORE_PIN48_PORTSET	GPIO9_DR_SET

  734. #define CORE_PIN49_PORTSET	GPIO9_DR_SET

  735. #define CORE_PIN50_PORTSET	GPIO9_DR_SET

  736. #define CORE_PIN51_PORTSET	GPIO9_DR_SET

  737. #define CORE_PIN52_PORTSET	GPIO9_DR_SET

  738. #define CORE_PIN53_PORTSET	GPIO9_DR_SET

  739. #define CORE_PIN54_PORTSET	GPIO9_DR_SET

  740. 

  741. #define CORE_PIN0_PORTCLEAR	GPIO6_DR_CLEAR

  742. #define CORE_PIN1_PORTCLEAR	GPIO6_DR_CLEAR

  743. #define CORE_PIN2_PORTCLEAR	GPIO9_DR_CLEAR

  744. #define CORE_PIN3_PORTCLEAR	GPIO9_DR_CLEAR

  745. #define CORE_PIN4_PORTCLEAR	GPIO9_DR_CLEAR

  746. #define CORE_PIN5_PORTCLEAR	GPIO9_DR_CLEAR

  747. #define CORE_PIN6_PORTCLEAR	GPIO7_DR_CLEAR

  748. #define CORE_PIN7_PORTCLEAR	GPIO7_DR_CLEAR

  749. #define CORE_PIN8_PORTCLEAR	GPIO7_DR_CLEAR

  750. #define CORE_PIN9_PORTCLEAR	GPIO7_DR_CLEAR

  751. #define CORE_PIN10_PORTCLEAR	GPIO7_DR_CLEAR

  752. #define CORE_PIN11_PORTCLEAR	GPIO7_DR_CLEAR

  753. #define CORE_PIN12_PORTCLEAR	GPIO7_DR_CLEAR

  754. #define CORE_PIN13_PORTCLEAR	GPIO7_DR_CLEAR

  755. #define CORE_PIN14_PORTCLEAR	GPIO6_DR_CLEAR

  756. #define CORE_PIN15_PORTCLEAR	GPIO6_DR_CLEAR

  757. #define CORE_PIN16_PORTCLEAR	GPIO6_DR_CLEAR

  758. #define CORE_PIN17_PORTCLEAR	GPIO6_DR_CLEAR

  759. #define CORE_PIN18_PORTCLEAR	GPIO6_DR_CLEAR

  760. #define CORE_PIN19_PORTCLEAR	GPIO6_DR_CLEAR

  761. #define CORE_PIN20_PORTCLEAR	GPIO6_DR_CLEAR

  762. #define CORE_PIN21_PORTCLEAR	GPIO6_DR_CLEAR

  763. #define CORE_PIN22_PORTCLEAR	GPIO6_DR_CLEAR

  764. #define CORE_PIN23_PORTCLEAR	GPIO6_DR_CLEAR

  765. #define CORE_PIN24_PORTCLEAR	GPIO6_DR_CLEAR

  766. #define CORE_PIN25_PORTCLEAR	GPIO6_DR_CLEAR

  767. #define CORE_PIN26_PORTCLEAR	GPIO6_DR_CLEAR

  768. #define CORE_PIN27_PORTCLEAR	GPIO6_DR_CLEAR

  769. #define CORE_PIN28_PORTCLEAR	GPIO8_DR_CLEAR

  770. #define CORE_PIN29_PORTCLEAR	GPIO9_DR_CLEAR

  771. #define CORE_PIN30_PORTCLEAR	GPIO8_DR_CLEAR

  772. #define CORE_PIN31_PORTCLEAR	GPIO8_DR_CLEAR

  773. #define CORE_PIN32_PORTCLEAR	GPIO7_DR_CLEAR

  774. #define CORE_PIN33_PORTCLEAR	GPIO9_DR_CLEAR

  775. #define CORE_PIN34_PORTCLEAR	GPIO7_DR_CLEAR

  776. #define CORE_PIN35_PORTCLEAR	GPIO7_DR_CLEAR

  777. #define CORE_PIN36_PORTCLEAR	GPIO7_DR_CLEAR

  778. #define CORE_PIN37_PORTCLEAR	GPIO7_DR_CLEAR

  779. #define CORE_PIN38_PORTCLEAR	GPIO6_DR_CLEAR

  780. #define CORE_PIN39_PORTCLEAR	GPIO6_DR_CLEAR

  781. #define CORE_PIN40_PORTCLEAR	GPIO6_DR_CLEAR

  782. #define CORE_PIN41_PORTCLEAR	GPIO6_DR_CLEAR

  783. #define CORE_PIN42_PORTCLEAR	GPIO8_DR_CLEAR

  784. #define CORE_PIN43_PORTCLEAR	GPIO8_DR_CLEAR

  785. #define CORE_PIN44_PORTCLEAR	GPIO8_DR_CLEAR

  786. #define CORE_PIN45_PORTCLEAR	GPIO8_DR_CLEAR

  787. #define CORE_PIN46_PORTCLEAR	GPIO8_DR_CLEAR

  788. #define CORE_PIN47_PORTCLEAR	GPIO8_DR_CLEAR

  789. #define CORE_PIN48_PORTCLEAR	GPIO9_DR_CLEAR

  790. #define CORE_PIN49_PORTCLEAR	GPIO9_DR_CLEAR

  791. #define CORE_PIN50_PORTCLEAR	GPIO9_DR_CLEAR

  792. #define CORE_PIN51_PORTCLEAR	GPIO9_DR_CLEAR

  793. #define CORE_PIN52_PORTCLEAR	GPIO9_DR_CLEAR

  794. #define CORE_PIN53_PORTCLEAR	GPIO9_DR_CLEAR

  795. #define CORE_PIN54_PORTCLEAR	GPIO9_DR_CLEAR

  796. 

  797. #define CORE_PIN0_DDRREG	GPIO6_GDIR

  798. #define CORE_PIN1_DDRREG	GPIO6_GDIR

  799. #define CORE_PIN2_DDRREG	GPIO9_GDIR

  800. #define CORE_PIN3_DDRREG	GPIO9_GDIR

  801. #define CORE_PIN4_DDRREG	GPIO9_GDIR

  802. #define CORE_PIN5_DDRREG	GPIO9_GDIR

  803. #define CORE_PIN6_DDRREG	GPIO7_GDIR

  804. #define CORE_PIN7_DDRREG	GPIO7_GDIR

  805. #define CORE_PIN8_DDRREG	GPIO7_GDIR

  806. #define CORE_PIN9_DDRREG	GPIO7_GDIR

  807. #define CORE_PIN10_DDRREG	GPIO7_GDIR

  808. #define CORE_PIN11_DDRREG	GPIO7_GDIR

  809. #define CORE_PIN12_DDRREG	GPIO7_GDIR

  810. #define CORE_PIN13_DDRREG	GPIO7_GDIR

  811. #define CORE_PIN14_DDRREG	GPIO6_GDIR

  812. #define CORE_PIN15_DDRREG	GPIO6_GDIR

  813. #define CORE_PIN16_DDRREG	GPIO6_GDIR

  814. #define CORE_PIN17_DDRREG	GPIO6_GDIR

  815. #define CORE_PIN18_DDRREG	GPIO6_GDIR

  816. #define CORE_PIN19_DDRREG	GPIO6_GDIR

  817. #define CORE_PIN20_DDRREG	GPIO6_GDIR

  818. #define CORE_PIN21_DDRREG	GPIO6_GDIR

  819. #define CORE_PIN22_DDRREG	GPIO6_GDIR

  820. #define CORE_PIN23_DDRREG	GPIO6_GDIR

  821. #define CORE_PIN24_DDRREG	GPIO6_GDIR

  822. #define CORE_PIN25_DDRREG	GPIO6_GDIR

  823. #define CORE_PIN26_DDRREG	GPIO6_GDIR

  824. #define CORE_PIN27_DDRREG	GPIO6_GDIR

  825. #define CORE_PIN28_DDRREG	GPIO8_GDIR

  826. #define CORE_PIN29_DDRREG	GPIO9_GDIR

  827. #define CORE_PIN30_DDRREG	GPIO8_GDIR

  828. #define CORE_PIN31_DDRREG	GPIO8_GDIR

  829. #define CORE_PIN32_DDRREG	GPIO7_GDIR

  830. #define CORE_PIN33_DDRREG	GPIO9_GDIR

  831. #define CORE_PIN34_DDRREG	GPIO7_GDIR

  832. #define CORE_PIN35_DDRREG	GPIO7_GDIR

  833. #define CORE_PIN36_DDRREG	GPIO7_GDIR

  834. #define CORE_PIN37_DDRREG	GPIO7_GDIR

  835. #define CORE_PIN38_DDRREG	GPIO6_GDIR

  836. #define CORE_PIN39_DDRREG	GPIO6_GDIR

  837. #define CORE_PIN40_DDRREG	GPIO6_GDIR

  838. #define CORE_PIN41_DDRREG	GPIO6_GDIR

  839. #define CORE_PIN42_DDRREG	GPIO8_GDIR

  840. #define CORE_PIN43_DDRREG	GPIO8_GDIR

  841. #define CORE_PIN44_DDRREG	GPIO8_GDIR

  842. #define CORE_PIN45_DDRREG	GPIO8_GDIR

  843. #define CORE_PIN46_DDRREG	GPIO8_GDIR

  844. #define CORE_PIN47_DDRREG	GPIO8_GDIR

  845. #define CORE_PIN48_DDRREG	GPIO9_GDIR

  846. #define CORE_PIN49_DDRREG	GPIO9_GDIR

  847. #define CORE_PIN50_DDRREG	GPIO9_GDIR

  848. #define CORE_PIN51_DDRREG	GPIO9_GDIR

  849. #define CORE_PIN52_DDRREG	GPIO9_GDIR

  850. #define CORE_PIN53_DDRREG	GPIO9_GDIR

  851. #define CORE_PIN54_DDRREG	GPIO9_GDIR

  852. 

  853. #define CORE_PIN0_PINREG	GPIO6_PSR

  854. #define CORE_PIN1_PINREG	GPIO6_PSR

  855. #define CORE_PIN2_PINREG	GPIO9_PSR

  856. #define CORE_PIN3_PINREG	GPIO9_PSR

  857. #define CORE_PIN4_PINREG	GPIO9_PSR

  858. #define CORE_PIN5_PINREG	GPIO9_PSR

  859. #define CORE_PIN6_PINREG	GPIO7_PSR

  860. #define CORE_PIN7_PINREG	GPIO7_PSR

  861. #define CORE_PIN8_PINREG	GPIO7_PSR

  862. #define CORE_PIN9_PINREG	GPIO7_PSR

  863. #define CORE_PIN10_PINREG	GPIO7_PSR

  864. #define CORE_PIN11_PINREG	GPIO7_PSR

  865. #define CORE_PIN12_PINREG	GPIO7_PSR

  866. #define CORE_PIN13_PINREG	GPIO7_PSR

  867. #define CORE_PIN14_PINREG	GPIO6_PSR

  868. #define CORE_PIN15_PINREG	GPIO6_PSR

  869. #define CORE_PIN16_PINREG	GPIO6_PSR

  870. #define CORE_PIN17_PINREG	GPIO6_PSR

  871. #define CORE_PIN18_PINREG	GPIO6_PSR

  872. #define CORE_PIN19_PINREG	GPIO6_PSR

  873. #define CORE_PIN20_PINREG	GPIO6_PSR

  874. #define CORE_PIN21_PINREG	GPIO6_PSR

  875. #define CORE_PIN22_PINREG	GPIO6_PSR

  876. #define CORE_PIN23_PINREG	GPIO6_PSR

  877. #define CORE_PIN24_PINREG	GPIO6_PSR

  878. #define CORE_PIN25_PINREG	GPIO6_PSR

  879. #define CORE_PIN26_PINREG	GPIO6_PSR

  880. #define CORE_PIN27_PINREG	GPIO6_PSR

  881. #define CORE_PIN28_PINREG	GPIO8_PSR

  882. #define CORE_PIN29_PINREG	GPIO9_PSR

  883. #define CORE_PIN30_PINREG	GPIO8_PSR

  884. #define CORE_PIN31_PINREG	GPIO8_PSR

  885. #define CORE_PIN32_PINREG	GPIO7_PSR

  886. #define CORE_PIN33_PINREG	GPIO9_PSR

  887. #define CORE_PIN34_PINREG	GPIO7_PSR

  888. #define CORE_PIN35_PINREG	GPIO7_PSR

  889. #define CORE_PIN36_PINREG	GPIO7_PSR

  890. #define CORE_PIN37_PINREG	GPIO7_PSR

  891. #define CORE_PIN38_PINREG	GPIO6_PSR

  892. #define CORE_PIN39_PINREG	GPIO6_PSR

  893. #define CORE_PIN40_PINREG	GPIO6_PSR

  894. #define CORE_PIN41_PINREG	GPIO6_PSR

  895. #define CORE_PIN42_PINREG	GPIO8_PSR

  896. #define CORE_PIN43_PINREG	GPIO8_PSR

  897. #define CORE_PIN44_PINREG	GPIO8_PSR

  898. #define CORE_PIN45_PINREG	GPIO8_PSR

  899. #define CORE_PIN46_PINREG	GPIO8_PSR

  900. #define CORE_PIN47_PINREG	GPIO8_PSR

  901. #define CORE_PIN48_PINREG	GPIO9_PSR

  902. #define CORE_PIN49_PINREG	GPIO9_PSR

  903. #define CORE_PIN50_PINREG	GPIO9_PSR

  904. #define CORE_PIN51_PINREG	GPIO9_PSR

  905. #define CORE_PIN52_PINREG	GPIO9_PSR

  906. #define CORE_PIN53_PINREG	GPIO9_PSR

  907. #define CORE_PIN54_PINREG	GPIO9_PSR

  908. 

  909. // mux config registers control which peripheral uses the pin

  910. #define CORE_PIN0_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03

  911. #define CORE_PIN1_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02

  912. #define CORE_PIN2_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04

  913. #define CORE_PIN3_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05

  914. #define CORE_PIN4_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06

  915. #define CORE_PIN5_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08

  916. #define CORE_PIN6_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10

  917. #define CORE_PIN7_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01

  918. #define CORE_PIN8_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00

  919. #define CORE_PIN9_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11

  920. #define CORE_PIN10_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00

  921. #define CORE_PIN11_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02

  922. #define CORE_PIN12_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01

  923. #define CORE_PIN13_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03

  924. #define CORE_PIN14_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02

  925. #define CORE_PIN15_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03

  926. #define CORE_PIN16_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07

  927. #define CORE_PIN17_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06

  928. #define CORE_PIN18_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01

  929. #define CORE_PIN19_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00

  930. #define CORE_PIN20_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10

  931. #define CORE_PIN21_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11

  932. #define CORE_PIN22_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08

  933. #define CORE_PIN23_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09

  934. #define CORE_PIN24_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12

  935. #define CORE_PIN25_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13

  936. #define CORE_PIN26_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14

  937. #define CORE_PIN27_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15

  938. #define CORE_PIN28_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32

  939. #define CORE_PIN29_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31

  940. #define CORE_PIN30_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37

  941. #define CORE_PIN31_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36

  942. #define CORE_PIN32_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12

  943. #define CORE_PIN33_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07

  944. #define CORE_PIN34_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13

  945. #define CORE_PIN35_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12

  946. #define CORE_PIN36_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02

  947. #define CORE_PIN37_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03

  948. #define CORE_PIN38_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12

  949. #define CORE_PIN39_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13

  950. #define CORE_PIN40_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04

  951. #define CORE_PIN41_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05

  952. #define CORE_PIN42_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03

  953. #define CORE_PIN43_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02

  954. #define CORE_PIN44_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01

  955. #define CORE_PIN45_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00

  956. #define CORE_PIN46_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05

  957. #define CORE_PIN47_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04

  958. #define CORE_PIN48_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24

  959. #define CORE_PIN49_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27

  960. #define CORE_PIN50_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28

  961. #define CORE_PIN51_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22

  962. #define CORE_PIN52_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26

  963. #define CORE_PIN53_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25

  964. #define CORE_PIN54_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29

  965. 

  966. // pad config registers control pullup/pulldown/keeper, drive strength, etc

  967. #define CORE_PIN0_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03

  968. #define CORE_PIN1_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02

  969. #define CORE_PIN2_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04

  970. #define CORE_PIN3_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05

  971. #define CORE_PIN4_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06

  972. #define CORE_PIN5_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08

  973. #define CORE_PIN6_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10

  974. #define CORE_PIN7_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01

  975. #define CORE_PIN8_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00

  976. #define CORE_PIN9_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11

  977. #define CORE_PIN10_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00

  978. #define CORE_PIN11_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02

  979. #define CORE_PIN12_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01

  980. #define CORE_PIN13_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03

  981. #define CORE_PIN14_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02

  982. #define CORE_PIN15_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03

  983. #define CORE_PIN16_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07

  984. #define CORE_PIN17_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06

  985. #define CORE_PIN18_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01

  986. #define CORE_PIN19_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00

  987. #define CORE_PIN20_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10

  988. #define CORE_PIN21_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11

  989. #define CORE_PIN22_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08

  990. #define CORE_PIN23_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09

  991. #define CORE_PIN24_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12

  992. #define CORE_PIN25_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13

  993. #define CORE_PIN26_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14

  994. #define CORE_PIN27_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15

  995. #define CORE_PIN28_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32

  996. #define CORE_PIN29_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31

  997. #define CORE_PIN30_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37

  998. #define CORE_PIN31_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36

  999. #define CORE_PIN32_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12

  1000. #define CORE_PIN33_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07

  1001. #define CORE_PIN34_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13

  1002. #define CORE_PIN35_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12

  1003. #define CORE_PIN36_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02

  1004. #define CORE_PIN37_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03

  1005. #define CORE_PIN38_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12

  1006. #define CORE_PIN39_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13

  1007. #define CORE_PIN40_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04

  1008. #define CORE_PIN41_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05

  1009. #define CORE_PIN42_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03

  1010. #define CORE_PIN43_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02

  1011. #define CORE_PIN44_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01

  1012. #define CORE_PIN45_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00

  1013. #define CORE_PIN46_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05

  1014. #define CORE_PIN47_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04

  1015. #define CORE_PIN48_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24

  1016. #define CORE_PIN49_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27

  1017. #define CORE_PIN50_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28

  1018. #define CORE_PIN51_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22

  1019. #define CORE_PIN52_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26

  1020. #define CORE_PIN53_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25

  1021. #define CORE_PIN54_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29

  1022. 

  1023. #define CORE_LED0_PIN		13

  1024. 

  1025. #define CORE_ADC0_PIN		14

  1026. #define CORE_ADC1_PIN		15

  1027. #define CORE_ADC2_PIN		16

  1028. #define CORE_ADC3_PIN		17

  1029. #define CORE_ADC4_PIN		18

  1030. #define CORE_ADC5_PIN		19

  1031. #define CORE_ADC6_PIN		20

  1032. #define CORE_ADC7_PIN		21

  1033. #define CORE_ADC8_PIN		22

  1034. #define CORE_ADC9_PIN		23

  1035. 

  1036. #define CORE_RXD0_PIN		0

  1037. #define CORE_TXD0_PIN		1

  1038. #define CORE_RXD1_PIN		7

  1039. #define CORE_TXD1_PIN		8

  1040. #define CORE_RXD2_PIN		15

  1041. #define CORE_TXD2_PIN		14

  1042. #define CORE_RXD3_PIN		16

  1043. #define CORE_TXD3_PIN		17

  1044. #define CORE_RXD4_PIN		21

  1045. #define CORE_TXD4_PIN		20

  1046. #define CORE_RXD5_PIN		25

  1047. #define CORE_TXD5_PIN		24

  1048. #define CORE_RXD6_PIN		28

  1049. #define CORE_TXD6_PIN		29

  1050. #define CORE_RXD7_PIN		34

  1051. #define CORE_TXD7_PIN		35

  1052. 

  1053. #define CORE_INT0_PIN		0

  1054. #define CORE_INT1_PIN		1

  1055. #define CORE_INT2_PIN		2

  1056. #define CORE_INT3_PIN		3

  1057. #define CORE_INT4_PIN		4

  1058. #define CORE_INT5_PIN		5

  1059. #define CORE_INT6_PIN		6

  1060. #define CORE_INT7_PIN		7

  1061. #define CORE_INT8_PIN		8

  1062. #define CORE_INT9_PIN		9

  1063. #define CORE_INT10_PIN		10

  1064. #define CORE_INT11_PIN		11

  1065. #define CORE_INT12_PIN		12

  1066. #define CORE_INT13_PIN		13

  1067. #define CORE_INT14_PIN		14

  1068. #define CORE_INT15_PIN		15

  1069. #define CORE_INT16_PIN		16

  1070. #define CORE_INT17_PIN		17

  1071. #define CORE_INT18_PIN		18

  1072. #define CORE_INT19_PIN		19

  1073. #define CORE_INT20_PIN		20

  1074. #define CORE_INT21_PIN		21

  1075. #define CORE_INT22_PIN		22

  1076. #define CORE_INT23_PIN		23

  1077. #define CORE_INT24_PIN		24

  1078. #define CORE_INT25_PIN		25

  1079. #define CORE_INT26_PIN		26

  1080. #define CORE_INT27_PIN		27

  1081. #define CORE_INT28_PIN		28

  1082. #define CORE_INT29_PIN		29

  1083. #define CORE_INT30_PIN		30

  1084. #define CORE_INT31_PIN		31

  1085. #define CORE_INT32_PIN		32

  1086. #define CORE_INT33_PIN		33

  1087. #define CORE_INT34_PIN		34

  1088. #define CORE_INT35_PIN		35

  1089. #define CORE_INT36_PIN		36

  1090. #define CORE_INT37_PIN		37

  1091. #define CORE_INT38_PIN		38

  1092. #define CORE_INT39_PIN		39

  1093. #define CORE_INT40_PIN		40

  1094. #define CORE_INT41_PIN		41

  1095. #define CORE_INT42_PIN		42

  1096. #define CORE_INT43_PIN		43

  1097. #define CORE_INT44_PIN		44

  1098. #define CORE_INT45_PIN		45

  1099. #define CORE_INT46_PIN		46

  1100. #define CORE_INT47_PIN		47

  1101. #define CORE_INT48_PIN		48

  1102. #define CORE_INT49_PIN		49

  1103. #define CORE_INT50_PIN		50

  1104. #define CORE_INT51_PIN		51

  1105. #define CORE_INT52_PIN		52

  1106. #define CORE_INT53_PIN		53

  1107. #define CORE_INT54_PIN		54

  1108. #define CORE_INT_EVERY_PIN	1

  1109. 

  1110. 

  1111. 

  1112. 

  1113. 

  1114. 

  1115. 

  1116. #endif // __IMXRT1062__

  1117. 

  1118. #ifdef __cplusplus

  1119. extern "C" {

  1120. #endif

  1121. 

  1122. //TODO:

  1123. //#define analogInputToDigitalPin(p)

  1124. //#define digitalPinHasPWM(p)

  1125. #define digitalPinToInterrupt(p)  ((p) < NUM_DIGITAL_PINS ? (p) : -1)

  1126. 

  1127. void digitalWrite(uint8_t pin, uint8_t val);

  1128. static inline void digitalWriteFast(uint8_t pin, uint8_t val) __attribute__((always_inline, unused));

  1129. static inline void digitalWriteFast(uint8_t pin, uint8_t val)

  1130. {

  1131. 	if (__builtin_constant_p(pin)) {

  1132. 		if (val) {

  1133. 			if (pin == 0) {

  1134. 				CORE_PIN0_PORTSET = CORE_PIN0_BITMASK;

  1135. 			} else if (pin == 1) {

  1136. 				CORE_PIN1_PORTSET = CORE_PIN1_BITMASK;

  1137. 			} else if (pin == 2) {

  1138. 				CORE_PIN2_PORTSET = CORE_PIN2_BITMASK;

  1139. 			} else if (pin == 3) {

  1140. 				CORE_PIN3_PORTSET = CORE_PIN3_BITMASK;

  1141. 			} else if (pin == 4) {

  1142. 				CORE_PIN4_PORTSET = CORE_PIN4_BITMASK;

  1143. 			} else if (pin == 5) {

  1144. 				CORE_PIN5_PORTSET = CORE_PIN5_BITMASK;

  1145. 			} else if (pin == 6) {

  1146. 				CORE_PIN6_PORTSET = CORE_PIN6_BITMASK;

  1147. 			} else if (pin == 7) {

  1148. 				CORE_PIN7_PORTSET = CORE_PIN7_BITMASK;

  1149. 			} else if (pin == 8) {

  1150. 				CORE_PIN8_PORTSET = CORE_PIN8_BITMASK;

  1151. 			} else if (pin == 9) {

  1152. 				CORE_PIN9_PORTSET = CORE_PIN9_BITMASK;

  1153. 			} else if (pin == 10) {

  1154. 				CORE_PIN10_PORTSET = CORE_PIN10_BITMASK;

  1155. 			} else if (pin == 11) {

  1156. 				CORE_PIN11_PORTSET = CORE_PIN11_BITMASK;

  1157. 			} else if (pin == 12) {

  1158. 				CORE_PIN12_PORTSET = CORE_PIN12_BITMASK;

  1159. 			} else if (pin == 13) {

  1160. 				CORE_PIN13_PORTSET = CORE_PIN13_BITMASK;

  1161. 			} else if (pin == 14) {

  1162. 				CORE_PIN14_PORTSET = CORE_PIN14_BITMASK;

  1163. 			} else if (pin == 15) {

  1164. 				CORE_PIN15_PORTSET = CORE_PIN15_BITMASK;

  1165. 			} else if (pin == 16) {

  1166. 				CORE_PIN16_PORTSET = CORE_PIN16_BITMASK;

  1167. 			} else if (pin == 17) {

  1168. 				CORE_PIN17_PORTSET = CORE_PIN17_BITMASK;

  1169. 			} else if (pin == 18) {

  1170. 				CORE_PIN18_PORTSET = CORE_PIN18_BITMASK;

  1171. 			} else if (pin == 19) {

  1172. 				CORE_PIN19_PORTSET = CORE_PIN19_BITMASK;

  1173. 			} else if (pin == 20) {

  1174. 				CORE_PIN20_PORTSET = CORE_PIN20_BITMASK;

  1175. 			} else if (pin == 21) {

  1176. 				CORE_PIN21_PORTSET = CORE_PIN21_BITMASK;

  1177. 			} else if (pin == 22) {

  1178. 				CORE_PIN22_PORTSET = CORE_PIN22_BITMASK;

  1179. 			} else if (pin == 23) {

  1180. 				CORE_PIN23_PORTSET = CORE_PIN23_BITMASK;

  1181. 			} else if (pin == 24) {

  1182. 				CORE_PIN24_PORTSET = CORE_PIN24_BITMASK;

  1183. 			} else if (pin == 25) {

  1184. 				CORE_PIN25_PORTSET = CORE_PIN25_BITMASK;

  1185. 			} else if (pin == 26) {

  1186. 				CORE_PIN26_PORTSET = CORE_PIN26_BITMASK;

  1187. 			} else if (pin == 27) {

  1188. 				CORE_PIN27_PORTSET = CORE_PIN27_BITMASK;

  1189. 			} else if (pin == 28) {

  1190. 				CORE_PIN28_PORTSET = CORE_PIN28_BITMASK;

  1191. 			} else if (pin == 29) {

  1192. 				CORE_PIN29_PORTSET = CORE_PIN29_BITMASK;

  1193. 			} else if (pin == 30) {

  1194. 				CORE_PIN30_PORTSET = CORE_PIN30_BITMASK;

  1195. 			} else if (pin == 31) {

  1196. 				CORE_PIN31_PORTSET = CORE_PIN31_BITMASK;

  1197. 			} else if (pin == 32) {

  1198. 				CORE_PIN32_PORTSET = CORE_PIN32_BITMASK;

  1199. 			} else if (pin == 33) {

  1200. 				CORE_PIN33_PORTSET = CORE_PIN33_BITMASK;

  1201. 			} else if (pin == 34) {

  1202. 				CORE_PIN34_PORTSET = CORE_PIN34_BITMASK;

  1203. 			} else if (pin == 35) {

  1204. 				CORE_PIN35_PORTSET = CORE_PIN35_BITMASK;

  1205. 			} else if (pin == 36) {

  1206. 				CORE_PIN36_PORTSET = CORE_PIN36_BITMASK;

  1207. 			} else if (pin == 37) {

  1208. 				CORE_PIN37_PORTSET = CORE_PIN37_BITMASK;

  1209. 			} else if (pin == 38) {

  1210. 				CORE_PIN38_PORTSET = CORE_PIN38_BITMASK;

  1211. 			} else if (pin == 39) {

  1212. 				CORE_PIN39_PORTSET = CORE_PIN39_BITMASK;

  1213. #if CORE_NUM_DIGITAL >= 55

  1214. 			} else if (pin == 40) {

  1215. 				CORE_PIN40_PORTSET = CORE_PIN40_BITMASK;

  1216. 			} else if (pin == 41) {

  1217. 				CORE_PIN41_PORTSET = CORE_PIN41_BITMASK;

  1218. 			} else if (pin == 42) {

  1219. 				CORE_PIN42_PORTSET = CORE_PIN42_BITMASK;

  1220. 			} else if (pin == 43) {

  1221. 				CORE_PIN43_PORTSET = CORE_PIN43_BITMASK;

  1222. 			} else if (pin == 44) {

  1223. 				CORE_PIN44_PORTSET = CORE_PIN44_BITMASK;

  1224. 			} else if (pin == 45) {

  1225. 				CORE_PIN45_PORTSET = CORE_PIN45_BITMASK;

  1226. 			} else if (pin == 46) {

  1227. 				CORE_PIN46_PORTSET = CORE_PIN46_BITMASK;

  1228. 			} else if (pin == 47) {

  1229. 				CORE_PIN47_PORTSET = CORE_PIN47_BITMASK;

  1230. 			} else if (pin == 48) {

  1231. 				CORE_PIN48_PORTSET = CORE_PIN48_BITMASK;

  1232. 			} else if (pin == 49) {

  1233. 				CORE_PIN49_PORTSET = CORE_PIN49_BITMASK;

  1234. 			} else if (pin == 50) {

  1235. 				CORE_PIN50_PORTSET = CORE_PIN50_BITMASK;

  1236. 			} else if (pin == 51) {

  1237. 				CORE_PIN51_PORTSET = CORE_PIN51_BITMASK;

  1238. 			} else if (pin == 52) {

  1239. 				CORE_PIN52_PORTSET = CORE_PIN52_BITMASK;

  1240. 			} else if (pin == 53) {

  1241. 				CORE_PIN53_PORTSET = CORE_PIN53_BITMASK;

  1242. 			} else if (pin == 54) {

  1243. 				CORE_PIN54_PORTSET = CORE_PIN54_BITMASK;

  1244. #endif

  1245. 			}

  1246. 		} else {

  1247. 			if (pin == 0) {

  1248. 				CORE_PIN0_PORTCLEAR = CORE_PIN0_BITMASK;

  1249. 			} else if (pin == 1) {

  1250. 				CORE_PIN1_PORTCLEAR = CORE_PIN1_BITMASK;

  1251. 			} else if (pin == 2) {

  1252. 				CORE_PIN2_PORTCLEAR = CORE_PIN2_BITMASK;

  1253. 			} else if (pin == 3) {

  1254. 				CORE_PIN3_PORTCLEAR = CORE_PIN3_BITMASK;

  1255. 			} else if (pin == 4) {

  1256. 				CORE_PIN4_PORTCLEAR = CORE_PIN4_BITMASK;

  1257. 			} else if (pin == 5) {

  1258. 				CORE_PIN5_PORTCLEAR = CORE_PIN5_BITMASK;

  1259. 			} else if (pin == 6) {

  1260. 				CORE_PIN6_PORTCLEAR = CORE_PIN6_BITMASK;

  1261. 			} else if (pin == 7) {

  1262. 				CORE_PIN7_PORTCLEAR = CORE_PIN7_BITMASK;

  1263. 			} else if (pin == 8) {

  1264. 				CORE_PIN8_PORTCLEAR = CORE_PIN8_BITMASK;

  1265. 			} else if (pin == 9) {

  1266. 				CORE_PIN9_PORTCLEAR = CORE_PIN9_BITMASK;

  1267. 			} else if (pin == 10) {

  1268. 				CORE_PIN10_PORTCLEAR = CORE_PIN10_BITMASK;

  1269. 			} else if (pin == 11) {

  1270. 				CORE_PIN11_PORTCLEAR = CORE_PIN11_BITMASK;

  1271. 			} else if (pin == 12) {

  1272. 				CORE_PIN12_PORTCLEAR = CORE_PIN12_BITMASK;

  1273. 			} else if (pin == 13) {

  1274. 				CORE_PIN13_PORTCLEAR = CORE_PIN13_BITMASK;

  1275. 			} else if (pin == 14) {

  1276. 				CORE_PIN14_PORTCLEAR = CORE_PIN14_BITMASK;

  1277. 			} else if (pin == 15) {

  1278. 				CORE_PIN15_PORTCLEAR = CORE_PIN15_BITMASK;

  1279. 			} else if (pin == 16) {

  1280. 				CORE_PIN16_PORTCLEAR = CORE_PIN16_BITMASK;

  1281. 			} else if (pin == 17) {

  1282. 				CORE_PIN17_PORTCLEAR = CORE_PIN17_BITMASK;

  1283. 			} else if (pin == 18) {

  1284. 				CORE_PIN18_PORTCLEAR = CORE_PIN18_BITMASK;

  1285. 			} else if (pin == 19) {

  1286. 				CORE_PIN19_PORTCLEAR = CORE_PIN19_BITMASK;

  1287. 			} else if (pin == 20) {

  1288. 				CORE_PIN20_PORTCLEAR = CORE_PIN20_BITMASK;

  1289. 			} else if (pin == 21) {

  1290. 				CORE_PIN21_PORTCLEAR = CORE_PIN21_BITMASK;

  1291. 			} else if (pin == 22) {

  1292. 				CORE_PIN22_PORTCLEAR = CORE_PIN22_BITMASK;

  1293. 			} else if (pin == 23) {

  1294. 				CORE_PIN23_PORTCLEAR = CORE_PIN23_BITMASK;

  1295. 			} else if (pin == 24) {

  1296. 				CORE_PIN24_PORTCLEAR = CORE_PIN24_BITMASK;

  1297. 			} else if (pin == 25) {

  1298. 				CORE_PIN25_PORTCLEAR = CORE_PIN25_BITMASK;

  1299. 			} else if (pin == 26) {

  1300. 				CORE_PIN26_PORTCLEAR = CORE_PIN26_BITMASK;

  1301. 			} else if (pin == 27) {

  1302. 				CORE_PIN27_PORTCLEAR = CORE_PIN27_BITMASK;

  1303. 			} else if (pin == 28) {

  1304. 				CORE_PIN28_PORTCLEAR = CORE_PIN28_BITMASK;

  1305. 			} else if (pin == 29) {

  1306. 				CORE_PIN29_PORTCLEAR = CORE_PIN29_BITMASK;

  1307. 			} else if (pin == 30) {

  1308. 				CORE_PIN30_PORTCLEAR = CORE_PIN30_BITMASK;

  1309. 			} else if (pin == 31) {

  1310. 				CORE_PIN31_PORTCLEAR = CORE_PIN31_BITMASK;

  1311. 			} else if (pin == 32) {

  1312. 				CORE_PIN32_PORTCLEAR = CORE_PIN32_BITMASK;

  1313. 			} else if (pin == 33) {

  1314. 				CORE_PIN33_PORTCLEAR = CORE_PIN33_BITMASK;

  1315. 			} else if (pin == 34) {

  1316. 				CORE_PIN34_PORTCLEAR = CORE_PIN34_BITMASK;

  1317. 			} else if (pin == 35) {

  1318. 				CORE_PIN35_PORTCLEAR = CORE_PIN35_BITMASK;

  1319. 			} else if (pin == 36) {

  1320. 				CORE_PIN36_PORTCLEAR = CORE_PIN36_BITMASK;

  1321. 			} else if (pin == 37) {

  1322. 				CORE_PIN37_PORTCLEAR = CORE_PIN37_BITMASK;

  1323. 			} else if (pin == 38) {

  1324. 				CORE_PIN38_PORTCLEAR = CORE_PIN38_BITMASK;

  1325. 			} else if (pin == 39) {

  1326. 				CORE_PIN39_PORTCLEAR = CORE_PIN39_BITMASK;

  1327. #if CORE_NUM_DIGITAL >= 55

  1328. 			} else if (pin == 40) {

  1329. 				CORE_PIN40_PORTCLEAR = CORE_PIN40_BITMASK;

  1330. 			} else if (pin == 41) {

  1331. 				CORE_PIN41_PORTCLEAR = CORE_PIN41_BITMASK;

  1332. 			} else if (pin == 42) {

  1333. 				CORE_PIN42_PORTCLEAR = CORE_PIN42_BITMASK;

  1334. 			} else if (pin == 43) {

  1335. 				CORE_PIN43_PORTCLEAR = CORE_PIN43_BITMASK;

  1336. 			} else if (pin == 44) {

  1337. 				CORE_PIN44_PORTCLEAR = CORE_PIN44_BITMASK;

  1338. 			} else if (pin == 45) {

  1339. 				CORE_PIN45_PORTCLEAR = CORE_PIN45_BITMASK;

  1340. 			} else if (pin == 46) {

  1341. 				CORE_PIN46_PORTCLEAR = CORE_PIN46_BITMASK;

  1342. 			} else if (pin == 47) {

  1343. 				CORE_PIN47_PORTCLEAR = CORE_PIN47_BITMASK;

  1344. 			} else if (pin == 48) {

  1345. 				CORE_PIN48_PORTCLEAR = CORE_PIN48_BITMASK;

  1346. 			} else if (pin == 49) {

  1347. 				CORE_PIN49_PORTCLEAR = CORE_PIN49_BITMASK;

  1348. 			} else if (pin == 50) {

  1349. 				CORE_PIN50_PORTCLEAR = CORE_PIN50_BITMASK;

  1350. 			} else if (pin == 51) {

  1351. 				CORE_PIN51_PORTCLEAR = CORE_PIN51_BITMASK;

  1352. 			} else if (pin == 52) {

  1353. 				CORE_PIN52_PORTCLEAR = CORE_PIN52_BITMASK;

  1354. 			} else if (pin == 53) {

  1355. 				CORE_PIN53_PORTCLEAR = CORE_PIN53_BITMASK;

  1356. 			} else if (pin == 54) {

  1357. 				CORE_PIN54_PORTCLEAR = CORE_PIN54_BITMASK;

  1358. #endif

  1359. 			}

  1360. 		}

  1361. 	} else {

  1362. 		if(val) *portSetRegister(pin) = digitalPinToBitMask(pin);

  1363. 		else *portClearRegister(pin) = digitalPinToBitMask(pin);

  1364. 	}

  1365. }

  1366. 

  1367. uint8_t digitalRead(uint8_t pin);

  1368. static inline uint8_t digitalReadFast(uint8_t pin) __attribute__((always_inline, unused));

  1369. static inline uint8_t digitalReadFast(uint8_t pin)

  1370. {

  1371. 	if (__builtin_constant_p(pin)) {

  1372. 		if (pin == 0) {

  1373. 			return (CORE_PIN0_PINREG & CORE_PIN0_BITMASK) ? 1 : 0;

  1374. 		} else if (pin == 1) {

  1375. 			return (CORE_PIN1_PINREG & CORE_PIN1_BITMASK) ? 1 : 0;

  1376. 		} else if (pin == 2) {

  1377. 			return (CORE_PIN2_PINREG & CORE_PIN2_BITMASK) ? 1 : 0;

  1378. 		} else if (pin == 3) {

  1379. 			return (CORE_PIN3_PINREG & CORE_PIN3_BITMASK) ? 1 : 0;

  1380. 		} else if (pin == 4) {

  1381. 			return (CORE_PIN4_PINREG & CORE_PIN4_BITMASK) ? 1 : 0;

  1382. 		} else if (pin == 5) {

  1383. 			return (CORE_PIN5_PINREG & CORE_PIN5_BITMASK) ? 1 : 0;

  1384. 		} else if (pin == 6) {

  1385. 			return (CORE_PIN6_PINREG & CORE_PIN6_BITMASK) ? 1 : 0;

  1386. 		} else if (pin == 7) {

  1387. 			return (CORE_PIN7_PINREG & CORE_PIN7_BITMASK) ? 1 : 0;

  1388. 		} else if (pin == 8) {

  1389. 			return (CORE_PIN8_PINREG & CORE_PIN8_BITMASK) ? 1 : 0;

  1390. 		} else if (pin == 9) {

  1391. 			return (CORE_PIN9_PINREG & CORE_PIN9_BITMASK) ? 1 : 0;

  1392. 		} else if (pin == 10) {

  1393. 			return (CORE_PIN10_PINREG & CORE_PIN10_BITMASK) ? 1 : 0;

  1394. 		} else if (pin == 11) {

  1395. 			return (CORE_PIN11_PINREG & CORE_PIN11_BITMASK) ? 1 : 0;

  1396. 		} else if (pin == 12) {

  1397. 			return (CORE_PIN12_PINREG & CORE_PIN12_BITMASK) ? 1 : 0;

  1398. 		} else if (pin == 13) {

  1399. 			return (CORE_PIN13_PINREG & CORE_PIN13_BITMASK) ? 1 : 0;

  1400. 		} else if (pin == 14) {

  1401. 			return (CORE_PIN14_PINREG & CORE_PIN14_BITMASK) ? 1 : 0;

  1402. 		} else if (pin == 15) {

  1403. 			return (CORE_PIN15_PINREG & CORE_PIN15_BITMASK) ? 1 : 0;

  1404. 		} else if (pin == 16) {

  1405. 			return (CORE_PIN16_PINREG & CORE_PIN16_BITMASK) ? 1 : 0;

  1406. 		} else if (pin == 17) {

  1407. 			return (CORE_PIN17_PINREG & CORE_PIN17_BITMASK) ? 1 : 0;

  1408. 		} else if (pin == 18) {

  1409. 			return (CORE_PIN18_PINREG & CORE_PIN18_BITMASK) ? 1 : 0;

  1410. 		} else if (pin == 19) {

  1411. 			return (CORE_PIN19_PINREG & CORE_PIN19_BITMASK) ? 1 : 0;

  1412. 		} else if (pin == 20) {

  1413. 			return (CORE_PIN20_PINREG & CORE_PIN20_BITMASK) ? 1 : 0;

  1414. 		} else if (pin == 21) {

  1415. 			return (CORE_PIN21_PINREG & CORE_PIN21_BITMASK) ? 1 : 0;

  1416. 		} else if (pin == 22) {

  1417. 			return (CORE_PIN22_PINREG & CORE_PIN22_BITMASK) ? 1 : 0;

  1418. 		} else if (pin == 23) {

  1419. 			return (CORE_PIN23_PINREG & CORE_PIN23_BITMASK) ? 1 : 0;

  1420. 		} else if (pin == 24) {

  1421. 			return (CORE_PIN24_PINREG & CORE_PIN24_BITMASK) ? 1 : 0;

  1422. 		} else if (pin == 25) {

  1423. 			return (CORE_PIN25_PINREG & CORE_PIN25_BITMASK) ? 1 : 0;

  1424. 		} else if (pin == 26) {

  1425. 			return (CORE_PIN26_PINREG & CORE_PIN26_BITMASK) ? 1 : 0;

  1426. 		} else if (pin == 27) {

  1427. 			return (CORE_PIN27_PINREG & CORE_PIN27_BITMASK) ? 1 : 0;

  1428. 		} else if (pin == 28) {

  1429. 			return (CORE_PIN28_PINREG & CORE_PIN28_BITMASK) ? 1 : 0;

  1430. 		} else if (pin == 29) {

  1431. 			return (CORE_PIN29_PINREG & CORE_PIN29_BITMASK) ? 1 : 0;

  1432. 		} else if (pin == 30) {

  1433. 			return (CORE_PIN30_PINREG & CORE_PIN30_BITMASK) ? 1 : 0;

  1434. 		} else if (pin == 31) {

  1435. 			return (CORE_PIN31_PINREG & CORE_PIN31_BITMASK) ? 1 : 0;

  1436. 		} else if (pin == 32) {

  1437. 			return (CORE_PIN32_PINREG & CORE_PIN32_BITMASK) ? 1 : 0;

  1438. 		} else if (pin == 33) {

  1439. 			return (CORE_PIN33_PINREG & CORE_PIN33_BITMASK) ? 1 : 0;

  1440. 		} else if (pin == 34) {

  1441. 			return (CORE_PIN34_PINREG & CORE_PIN34_BITMASK) ? 1 : 0;

  1442. 		} else if (pin == 35) {

  1443. 			return (CORE_PIN35_PINREG & CORE_PIN35_BITMASK) ? 1 : 0;

  1444. 		} else if (pin == 36) {

  1445. 			return (CORE_PIN36_PINREG & CORE_PIN36_BITMASK) ? 1 : 0;

  1446. 		} else if (pin == 37) {

  1447. 			return (CORE_PIN37_PINREG & CORE_PIN37_BITMASK) ? 1 : 0;

  1448. 		} else if (pin == 38) {

  1449. 			return (CORE_PIN38_PINREG & CORE_PIN38_BITMASK) ? 1 : 0;

  1450. 		} else if (pin == 39) {

  1451. 			return (CORE_PIN39_PINREG & CORE_PIN39_BITMASK) ? 1 : 0;

  1452. #if CORE_NUM_DIGITAL >= 55

  1453. 		} else if (pin == 40) {

  1454. 			return (CORE_PIN40_PINREG & CORE_PIN40_BITMASK) ? 1 : 0;

  1455. 		} else if (pin == 41) {

  1456. 			return (CORE_PIN41_PINREG & CORE_PIN41_BITMASK) ? 1 : 0;

  1457. 		} else if (pin == 42) {

  1458. 			return (CORE_PIN42_PINREG & CORE_PIN42_BITMASK) ? 1 : 0;

  1459. 		} else if (pin == 43) {

  1460. 			return (CORE_PIN43_PINREG & CORE_PIN43_BITMASK) ? 1 : 0;

  1461. 		} else if (pin == 44) {

  1462. 			return (CORE_PIN44_PINREG & CORE_PIN44_BITMASK) ? 1 : 0;

  1463. 		} else if (pin == 45) {

  1464. 			return (CORE_PIN45_PINREG & CORE_PIN45_BITMASK) ? 1 : 0;

  1465. 		} else if (pin == 46) {

  1466. 			return (CORE_PIN46_PINREG & CORE_PIN46_BITMASK) ? 1 : 0;

  1467. 		} else if (pin == 47) {

  1468. 			return (CORE_PIN47_PINREG & CORE_PIN47_BITMASK) ? 1 : 0;

  1469. 		} else if (pin == 48) {

  1470. 			return (CORE_PIN48_PINREG & CORE_PIN48_BITMASK) ? 1 : 0;

  1471. 		} else if (pin == 49) {

  1472. 			return (CORE_PIN49_PINREG & CORE_PIN49_BITMASK) ? 1 : 0;

  1473. 		} else if (pin == 50) {

  1474. 			return (CORE_PIN50_PINREG & CORE_PIN50_BITMASK) ? 1 : 0;

  1475. 		} else if (pin == 51) {

  1476. 			return (CORE_PIN51_PINREG & CORE_PIN51_BITMASK) ? 1 : 0;

  1477. 		} else if (pin == 52) {

  1478. 			return (CORE_PIN52_PINREG & CORE_PIN52_BITMASK) ? 1 : 0;

  1479. 		} else if (pin == 53) {

  1480. 			return (CORE_PIN53_PINREG & CORE_PIN53_BITMASK) ? 1 : 0;

  1481. 		} else if (pin == 54) {

  1482. 			return (CORE_PIN54_PINREG & CORE_PIN54_BITMASK) ? 1 : 0;

  1483. #endif

  1484. 		} else {

  1485. 			return 0;

  1486. 		}

  1487. 	} else {

  1488. 		return (*portInputRegister(pin) & digitalPinToBitMask(pin)) ? 1 : 0;

  1489. 	}

  1490. }

  1491. 

  1492. 

  1493. void pinMode(uint8_t pin, uint8_t mode);

  1494. void init_pins(void);

  1495. void analogWrite(uint8_t pin, int val);

  1496. uint32_t analogWriteRes(uint32_t bits);

  1497. static inline uint32_t analogWriteResolution(uint32_t bits) { return analogWriteRes(bits); }

  1498. void analogWriteFrequency(uint8_t pin, float frequency);

  1499. void attachInterrupt(uint8_t pin, void (*function)(void), int mode);

  1500. void detachInterrupt(uint8_t pin);

  1501. void _init_Teensyduino_internal_(void);

  1502. int analogRead(uint8_t pin);

  1503. void analogReference(uint8_t type);

  1504. void analogReadRes(unsigned int bits);

  1505. static inline void analogReadResolution(unsigned int bits) { analogReadRes(bits); }

  1506. void analogReadAveraging(unsigned int num);

  1507. void analog_init(void);

  1508. int touchRead(uint8_t pin);

  1509. 

  1510. static inline void shiftOut(uint8_t, uint8_t, uint8_t, uint8_t) __attribute__((always_inline, unused));

  1511. extern void _shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t value) __attribute__((noinline));

  1512. extern void shiftOut_lsbFirst(uint8_t dataPin, uint8_t clockPin, uint8_t value) __attribute__((noinline));

  1513. extern void shiftOut_msbFirst(uint8_t dataPin, uint8_t clockPin, uint8_t value) __attribute__((noinline));

  1514. 

  1515. static inline void shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t value)

  1516. {

  1517.         if (__builtin_constant_p(bitOrder)) {

  1518.                 if (bitOrder == LSBFIRST) {

  1519.                         shiftOut_lsbFirst(dataPin, clockPin, value);

  1520.                 } else {

  1521.                         shiftOut_msbFirst(dataPin, clockPin, value);

  1522.                 }

  1523.         } else {

  1524.                 _shiftOut(dataPin, clockPin, bitOrder, value);

  1525.         }

  1526. }

  1527. 

  1528. static inline uint8_t shiftIn(uint8_t, uint8_t, uint8_t) __attribute__((always_inline, unused));

  1529. extern uint8_t _shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder) __attribute__((noinline));

  1530. extern uint8_t shiftIn_lsbFirst(uint8_t dataPin, uint8_t clockPin) __attribute__((noinline));

  1531. extern uint8_t shiftIn_msbFirst(uint8_t dataPin, uint8_t clockPin) __attribute__((noinline));

  1532. 

  1533. static inline uint8_t shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder)

  1534. {

  1535.         if (__builtin_constant_p(bitOrder)) {

  1536.                 if (bitOrder == LSBFIRST) {

  1537.                         return shiftIn_lsbFirst(dataPin, clockPin);

  1538.                 } else {

  1539.                         return shiftIn_msbFirst(dataPin, clockPin);

  1540.                 }

  1541.         } else {

  1542.                 return _shiftIn(dataPin, clockPin, bitOrder);

  1543.         }

  1544. }

  1545. 

  1546. void _reboot_Teensyduino_(void) __attribute__((noreturn));

  1547. void _restart_Teensyduino_(void) __attribute__((noreturn));

  1548. 

  1549. void yield(void);

  1550. 

  1551. void delay(uint32_t msec);

  1552. 

  1553. extern volatile uint32_t F_CPU_ACTUAL;

  1554. extern volatile uint32_t F_BUS_ACTUAL;

  1555. extern volatile uint32_t scale_cpu_cycles_to_microseconds;

  1556. extern volatile uint32_t systick_millis_count;

  1557. 

  1558. static inline uint32_t millis(void) __attribute__((always_inline, unused));

  1559. static inline uint32_t millis(void)

  1560. {

  1561. 	return systick_millis_count;

  1562. }

  1563. 

  1564. uint32_t micros(void);

  1565. 

  1566. static inline void delayMicroseconds(uint32_t) __attribute__((always_inline, unused));

  1567. static inline void delayMicroseconds(uint32_t usec)

  1568. {

  1569. 	uint32_t begin = ARM_DWT_CYCCNT;

  1570. 	uint32_t cycles = F_CPU_ACTUAL / 1000000 * usec;

  1571. 	// TODO: check if cycles is large, do a wait with yield calls until it's smaller

  1572. 	while (ARM_DWT_CYCCNT - begin < cycles) ; // wait

  1573. }

  1574. 

  1575. static inline void delayNanoseconds(uint32_t) __attribute__((always_inline, unused));

  1576. static inline void delayNanoseconds(uint32_t nsec)

  1577. {

  1578. 	uint32_t begin = ARM_DWT_CYCCNT;

  1579. 	uint32_t cycles =   ((F_CPU_ACTUAL>>16) * nsec) / (1000000000UL>>16);

  1580. 	while (ARM_DWT_CYCCNT - begin < cycles) ; // wait

  1581. }

  1582. 

  1583. 

  1584. unsigned long rtc_get(void);

  1585. void rtc_set(unsigned long t);

  1586. void rtc_compensate(int adjust);

  1587. 

  1588. void tempmon_init(void);

  1589. float tempmonGetTemp(void);

  1590. void tempmon_Start();

  1591. void tempmon_Stop();

  1592. void tempmon_PwrDwn();

  1593. 

  1594. #ifdef __cplusplus

  1595. }

  1596. 

  1597. class teensy3_clock_class

  1598. {

  1599. public:

  1600.         static unsigned long get(void) __attribute__((always_inline)) { return rtc_get(); }

  1601.         static void set(unsigned long t) __attribute__((always_inline)) { rtc_set(t); }

  1602.         static void compensate(int adj) __attribute__((always_inline)) { rtc_compensate(adj); }

  1603. };

  1604. extern teensy3_clock_class Teensy3Clock;

  1605. 

  1606. #endif // __cplusplus

  1607. 

  1608. 

  1609.