Teensy 4.1 core updated for C++20
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  1. #include "imxrt.h"
  2. #include "wiring.h"
  3. #include "usb_dev.h"
  4. #include "avr/pgmspace.h"
  5. #include "debug/printf.h"
  6. // from the linker
  7. extern unsigned long _stextload;
  8. extern unsigned long _stext;
  9. extern unsigned long _etext;
  10. extern unsigned long _sdataload;
  11. extern unsigned long _sdata;
  12. extern unsigned long _edata;
  13. extern unsigned long _sbss;
  14. extern unsigned long _ebss;
  15. extern unsigned long _flexram_bank_config;
  16. extern unsigned long _estack;
  17. __attribute__ ((used, aligned(1024)))
  18. void (* _VectorsRam[NVIC_NUM_INTERRUPTS+16])(void);
  19. static void memory_copy(uint32_t *dest, const uint32_t *src, uint32_t *dest_end);
  20. static void memory_clear(uint32_t *dest, uint32_t *dest_end);
  21. static void configure_systick(void);
  22. static void reset_PFD();
  23. extern void systick_isr(void);
  24. extern void pendablesrvreq_isr(void);
  25. void configure_cache(void);
  26. void unused_interrupt_vector(void);
  27. void usb_pll_start();
  28. extern void analog_init(void); // analog.c
  29. extern void pwm_init(void); // pwm.c
  30. extern void tempmon_init(void); //tempmon.c
  31. uint32_t set_arm_clock(uint32_t frequency); // clockspeed.c
  32. extern void __libc_init_array(void); // C++ standard library
  33. extern int main (void);
  34. void startup_default_early_hook(void) {}
  35. void startup_early_hook(void) __attribute__ ((weak, alias("startup_default_early_hook")));
  36. void startup_default_late_hook(void) {}
  37. void startup_late_hook(void) __attribute__ ((weak, alias("startup_default_late_hook")));
  38. __attribute__((section(".startup"), optimize("no-tree-loop-distribute-patterns"), naked))
  39. void ResetHandler(void)
  40. {
  41. unsigned int i;
  42. #if defined(__IMXRT1062__)
  43. IOMUXC_GPR_GPR17 = (uint32_t)&_flexram_bank_config;
  44. IOMUXC_GPR_GPR16 = 0x00200007;
  45. IOMUXC_GPR_GPR14 = 0x00AA0000;
  46. __asm__ volatile("mov sp, %0" : : "r" ((uint32_t)&_estack) : );
  47. #endif
  48. // pin 13 - if startup crashes, use this to turn on the LED early for troubleshooting
  49. //IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 5;
  50. //IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = IOMUXC_PAD_DSE(7);
  51. //IOMUXC_GPR_GPR27 = 0xFFFFFFFF;
  52. //GPIO7_GDIR |= (1<<3);
  53. //GPIO7_DR_SET = (1<<3); // digitalWrite(13, HIGH);
  54. // Initialize memory
  55. memory_copy(&_stext, &_stextload, &_etext);
  56. memory_copy(&_sdata, &_sdataload, &_edata);
  57. memory_clear(&_sbss, &_ebss);
  58. // enable FPU
  59. SCB_CPACR = 0x00F00000;
  60. // set up blank interrupt & exception vector table
  61. for (i=0; i < NVIC_NUM_INTERRUPTS + 16; i++) _VectorsRam[i] = &unused_interrupt_vector;
  62. for (i=0; i < NVIC_NUM_INTERRUPTS; i++) NVIC_SET_PRIORITY(i, 128);
  63. SCB_VTOR = (uint32_t)_VectorsRam;
  64. reset_PFD();
  65. // Configure clocks
  66. // TODO: make sure all affected peripherals are turned off!
  67. // PIT & GPT timers to run from 24 MHz clock (independent of CPU speed)
  68. CCM_CSCMR1 = (CCM_CSCMR1 & ~CCM_CSCMR1_PERCLK_PODF(0x3F)) | CCM_CSCMR1_PERCLK_CLK_SEL;
  69. // UARTs run from 24 MHz clock (works if PLL3 off or bypassed)
  70. CCM_CSCDR1 = (CCM_CSCDR1 & ~CCM_CSCDR1_UART_CLK_PODF(0x3F)) | CCM_CSCDR1_UART_CLK_SEL;
  71. #if defined(__IMXRT1062__)
  72. // Use fast GPIO6, GPIO7, GPIO8, GPIO9
  73. IOMUXC_GPR_GPR26 = 0xFFFFFFFF;
  74. IOMUXC_GPR_GPR27 = 0xFFFFFFFF;
  75. IOMUXC_GPR_GPR28 = 0xFFFFFFFF;
  76. IOMUXC_GPR_GPR29 = 0xFFFFFFFF;
  77. #endif
  78. // must enable PRINT_DEBUG_STUFF in debug/print.h
  79. printf_debug_init();
  80. printf("\n***********IMXRT Startup**********\n");
  81. printf("test %d %d %d\n", 1, -1234567, 3);
  82. configure_cache();
  83. configure_systick();
  84. usb_pll_start();
  85. reset_PFD(); //TODO: is this really needed?
  86. #ifdef F_CPU
  87. set_arm_clock(F_CPU);
  88. #endif
  89. asm volatile("nop\n nop\n nop\n nop": : :"memory"); // why oh why?
  90. // Undo PIT timer usage by ROM startup
  91. CCM_CCGR1 |= CCM_CCGR1_PIT(CCM_CCGR_ON);
  92. PIT_MCR = 0;
  93. PIT_TCTRL0 = 0;
  94. PIT_TCTRL1 = 0;
  95. PIT_TCTRL2 = 0;
  96. PIT_TCTRL3 = 0;
  97. // initialize RTC
  98. if (!(SNVS_LPCR & SNVS_LPCR_SRTC_ENV)) {
  99. // if SRTC isn't running, start it with default Jan 1, 2019
  100. SNVS_LPSRTCLR = 1546300800u << 15;
  101. SNVS_LPSRTCMR = 1546300800u >> 17;
  102. SNVS_LPCR |= SNVS_LPCR_SRTC_ENV;
  103. }
  104. SNVS_HPCR |= SNVS_HPCR_RTC_EN | SNVS_HPCR_HP_TS;
  105. startup_early_hook();
  106. while (millis() < 20) ; // wait at least 20ms before starting USB
  107. usb_init();
  108. analog_init();
  109. pwm_init();
  110. tempmon_init();
  111. startup_late_hook();
  112. while (millis() < 300) ; // wait at least 300ms before calling user code
  113. //printf("before C++ constructors\n");
  114. __libc_init_array();
  115. //printf("after C++ constructors\n");
  116. //printf("before setup\n");
  117. main();
  118. while (1) ;
  119. }
  120. // ARM SysTick is used for most Ardiuno timing functions, delay(), millis(),
  121. // micros(). SysTick can run from either the ARM core clock, or from an
  122. // "external" clock. NXP documents it as "24 MHz XTALOSC can be the external
  123. // clock source of SYSTICK" (RT1052 ref manual, rev 1, page 411). However,
  124. // NXP actually hid an undocumented divide-by-240 circuit in the hardware, so
  125. // the external clock is really 100 kHz. We use this clock rather than the
  126. // ARM clock, to allow SysTick to maintain correct timing even when we change
  127. // the ARM clock to run at different speeds.
  128. #define SYSTICK_EXT_FREQ 100000
  129. extern volatile uint32_t systick_cycle_count;
  130. static void configure_systick(void)
  131. {
  132. _VectorsRam[14] = pendablesrvreq_isr;
  133. _VectorsRam[15] = systick_isr;
  134. SYST_RVR = (SYSTICK_EXT_FREQ / 1000) - 1;
  135. SYST_CVR = 0;
  136. SYST_CSR = SYST_CSR_TICKINT | SYST_CSR_ENABLE;
  137. SCB_SHPR3 = 0x20200000; // Systick, pendablesrvreq_isr = priority 32;
  138. ARM_DEMCR |= ARM_DEMCR_TRCENA;
  139. ARM_DWT_CTRL |= ARM_DWT_CTRL_CYCCNTENA; // turn on cycle counter
  140. systick_cycle_count = ARM_DWT_CYCCNT; // compiled 0, corrected w/1st systick
  141. }
  142. // concise defines for SCB_MPU_RASR and SCB_MPU_RBAR, ARM DDI0403E, pg 696
  143. #define NOEXEC SCB_MPU_RASR_XN
  144. #define READONLY SCB_MPU_RASR_AP(7)
  145. #define READWRITE SCB_MPU_RASR_AP(3)
  146. #define NOACCESS SCB_MPU_RASR_AP(0)
  147. #define MEM_CACHE_WT SCB_MPU_RASR_TEX(0) | SCB_MPU_RASR_C
  148. #define MEM_CACHE_WB SCB_MPU_RASR_TEX(0) | SCB_MPU_RASR_C | SCB_MPU_RASR_B
  149. #define MEM_CACHE_WBWA SCB_MPU_RASR_TEX(1) | SCB_MPU_RASR_C | SCB_MPU_RASR_B
  150. #define MEM_NOCACHE SCB_MPU_RASR_TEX(1)
  151. #define DEV_NOCACHE SCB_MPU_RASR_TEX(2)
  152. #define SIZE_128K (SCB_MPU_RASR_SIZE(16) | SCB_MPU_RASR_ENABLE)
  153. #define SIZE_256K (SCB_MPU_RASR_SIZE(17) | SCB_MPU_RASR_ENABLE)
  154. #define SIZE_512K (SCB_MPU_RASR_SIZE(18) | SCB_MPU_RASR_ENABLE)
  155. #define SIZE_1M (SCB_MPU_RASR_SIZE(19) | SCB_MPU_RASR_ENABLE)
  156. #define SIZE_2M (SCB_MPU_RASR_SIZE(20) | SCB_MPU_RASR_ENABLE)
  157. #define SIZE_4M (SCB_MPU_RASR_SIZE(21) | SCB_MPU_RASR_ENABLE)
  158. #define SIZE_8M (SCB_MPU_RASR_SIZE(22) | SCB_MPU_RASR_ENABLE)
  159. #define SIZE_16M (SCB_MPU_RASR_SIZE(23) | SCB_MPU_RASR_ENABLE)
  160. #define SIZE_32M (SCB_MPU_RASR_SIZE(24) | SCB_MPU_RASR_ENABLE)
  161. #define SIZE_64M (SCB_MPU_RASR_SIZE(25) | SCB_MPU_RASR_ENABLE)
  162. #define SIZE_256M (SCB_MPU_RASR_SIZE(26) | SCB_MPU_RASR_ENABLE)
  163. #define REGION(n) (SCB_MPU_RBAR_REGION(n) | SCB_MPU_RBAR_VALID)
  164. FLASHMEM void configure_cache(void)
  165. {
  166. //printf("MPU_TYPE = %08lX\n", SCB_MPU_TYPE);
  167. //printf("CCR = %08lX\n", SCB_CCR);
  168. // TODO: check if caches already active - skip?
  169. SCB_MPU_CTRL = 0; // turn off MPU
  170. SCB_MPU_RBAR = 0x00000000 | REGION(0); // ITCM
  171. SCB_MPU_RASR = MEM_NOCACHE | READWRITE | SIZE_512K;
  172. SCB_MPU_RBAR = 0x00200000 | REGION(1); // Boot ROM
  173. SCB_MPU_RASR = MEM_CACHE_WT | READONLY | SIZE_128K;
  174. SCB_MPU_RBAR = 0x20000000 | REGION(2); // DTCM
  175. SCB_MPU_RASR = MEM_NOCACHE | READWRITE | NOEXEC | SIZE_512K;
  176. SCB_MPU_RBAR = 0x20200000 | REGION(3); // RAM (AXI bus)
  177. SCB_MPU_RASR = MEM_CACHE_WBWA | READWRITE | NOEXEC | SIZE_1M;
  178. SCB_MPU_RBAR = 0x40000000 | REGION(4); // Peripherals
  179. SCB_MPU_RASR = DEV_NOCACHE | READWRITE | NOEXEC | SIZE_64M;
  180. SCB_MPU_RBAR = 0x60000000 | REGION(5); // QSPI Flash
  181. SCB_MPU_RASR = MEM_CACHE_WBWA | READONLY | SIZE_16M;
  182. SCB_MPU_RBAR = 0x70000000 | REGION(6); // FlexSPI2
  183. SCB_MPU_RASR = MEM_CACHE_WBWA | READONLY | SIZE_256M;
  184. SCB_MPU_RBAR = 0x70000000 | REGION(7); // FlexSPI2
  185. SCB_MPU_RASR = MEM_CACHE_WBWA | READWRITE | SIZE_16M;
  186. // TODO: 32 byte sub-region at 0x00000000 with NOACCESS, to trap NULL pointer deref
  187. // TODO: protect access to power supply config
  188. // TODO: 32 byte sub-region at end of .bss section with NOACCESS, to trap stack overflow
  189. SCB_MPU_CTRL = SCB_MPU_CTRL_ENABLE;
  190. // cache enable, ARM DDI0403E, pg 628
  191. asm("dsb");
  192. asm("isb");
  193. SCB_CACHE_ICIALLU = 0;
  194. asm("dsb");
  195. asm("isb");
  196. SCB_CCR |= (SCB_CCR_IC | SCB_CCR_DC);
  197. }
  198. FLASHMEM void usb_pll_start()
  199. {
  200. while (1) {
  201. uint32_t n = CCM_ANALOG_PLL_USB1; // pg 759
  202. printf("CCM_ANALOG_PLL_USB1=%08lX\n", n);
  203. if (n & CCM_ANALOG_PLL_USB1_DIV_SELECT) {
  204. printf(" ERROR, 528 MHz mode!\n"); // never supposed to use this mode!
  205. CCM_ANALOG_PLL_USB1_CLR = 0xC000; // bypass 24 MHz
  206. CCM_ANALOG_PLL_USB1_SET = CCM_ANALOG_PLL_USB1_BYPASS; // bypass
  207. CCM_ANALOG_PLL_USB1_CLR = CCM_ANALOG_PLL_USB1_POWER | // power down
  208. CCM_ANALOG_PLL_USB1_DIV_SELECT | // use 480 MHz
  209. CCM_ANALOG_PLL_USB1_ENABLE | // disable
  210. CCM_ANALOG_PLL_USB1_EN_USB_CLKS; // disable usb
  211. continue;
  212. }
  213. if (!(n & CCM_ANALOG_PLL_USB1_ENABLE)) {
  214. printf(" enable PLL\n");
  215. // TODO: should this be done so early, or later??
  216. CCM_ANALOG_PLL_USB1_SET = CCM_ANALOG_PLL_USB1_ENABLE;
  217. continue;
  218. }
  219. if (!(n & CCM_ANALOG_PLL_USB1_POWER)) {
  220. printf(" power up PLL\n");
  221. CCM_ANALOG_PLL_USB1_SET = CCM_ANALOG_PLL_USB1_POWER;
  222. continue;
  223. }
  224. if (!(n & CCM_ANALOG_PLL_USB1_LOCK)) {
  225. printf(" wait for lock\n");
  226. continue;
  227. }
  228. if (n & CCM_ANALOG_PLL_USB1_BYPASS) {
  229. printf(" turn off bypass\n");
  230. CCM_ANALOG_PLL_USB1_CLR = CCM_ANALOG_PLL_USB1_BYPASS;
  231. continue;
  232. }
  233. if (!(n & CCM_ANALOG_PLL_USB1_EN_USB_CLKS)) {
  234. printf(" enable USB clocks\n");
  235. CCM_ANALOG_PLL_USB1_SET = CCM_ANALOG_PLL_USB1_EN_USB_CLKS;
  236. continue;
  237. }
  238. return; // everything is as it should be :-)
  239. }
  240. }
  241. FLASHMEM void reset_PFD()
  242. {
  243. //Reset PLL2 PFDs, set default frequencies:
  244. CCM_ANALOG_PFD_528_SET = (1 << 31) | (1 << 23) | (1 << 15) | (1 << 7);
  245. CCM_ANALOG_PFD_528 = 0x2018101B; // PFD0:352, PFD1:594, PFD2:396, PFD3:297 MHz
  246. //PLL3:
  247. CCM_ANALOG_PFD_480_SET = (1 << 31) | (1 << 23) | (1 << 15) | (1 << 7);
  248. CCM_ANALOG_PFD_480 = 0x13110D0C; // PFD0:720, PFD1:664, PFD2:508, PFD3:454 MHz
  249. }
  250. // Stack frame
  251. // xPSR
  252. // ReturnAddress
  253. // LR (R14) - typically FFFFFFF9 for IRQ or Exception
  254. // R12
  255. // R3
  256. // R2
  257. // R1
  258. // R0
  259. // Code from :: https://community.nxp.com/thread/389002
  260. __attribute__((naked))
  261. void unused_interrupt_vector(void)
  262. {
  263. __asm( ".syntax unified\n"
  264. "MOVS R0, #4 \n"
  265. "MOV R1, LR \n"
  266. "TST R0, R1 \n"
  267. "BEQ _MSP \n"
  268. "MRS R0, PSP \n"
  269. "B HardFault_HandlerC \n"
  270. "_MSP: \n"
  271. "MRS R0, MSP \n"
  272. "B HardFault_HandlerC \n"
  273. ".syntax divided\n") ;
  274. }
  275. __attribute__((weak))
  276. void HardFault_HandlerC(unsigned int *hardfault_args)
  277. {
  278. volatile unsigned int nn ;
  279. #ifdef PRINT_DEBUG_STUFF
  280. volatile unsigned int stacked_r0 ;
  281. volatile unsigned int stacked_r1 ;
  282. volatile unsigned int stacked_r2 ;
  283. volatile unsigned int stacked_r3 ;
  284. volatile unsigned int stacked_r12 ;
  285. volatile unsigned int stacked_lr ;
  286. volatile unsigned int stacked_pc ;
  287. volatile unsigned int stacked_psr ;
  288. volatile unsigned int _CFSR ;
  289. volatile unsigned int _HFSR ;
  290. volatile unsigned int _DFSR ;
  291. volatile unsigned int _AFSR ;
  292. volatile unsigned int _BFAR ;
  293. volatile unsigned int _MMAR ;
  294. volatile unsigned int addr ;
  295. stacked_r0 = ((unsigned int)hardfault_args[0]) ;
  296. stacked_r1 = ((unsigned int)hardfault_args[1]) ;
  297. stacked_r2 = ((unsigned int)hardfault_args[2]) ;
  298. stacked_r3 = ((unsigned int)hardfault_args[3]) ;
  299. stacked_r12 = ((unsigned int)hardfault_args[4]) ;
  300. stacked_lr = ((unsigned int)hardfault_args[5]) ;
  301. stacked_pc = ((unsigned int)hardfault_args[6]) ;
  302. stacked_psr = ((unsigned int)hardfault_args[7]) ;
  303. // Configurable Fault Status Register
  304. // Consists of MMSR, BFSR and UFSR
  305. //(n & ( 1 << k )) >> k
  306. _CFSR = (*((volatile unsigned int *)(0xE000ED28))) ;
  307. // Hard Fault Status Register
  308. _HFSR = (*((volatile unsigned int *)(0xE000ED2C))) ;
  309. // Debug Fault Status Register
  310. _DFSR = (*((volatile unsigned int *)(0xE000ED30))) ;
  311. // Auxiliary Fault Status Register
  312. _AFSR = (*((volatile unsigned int *)(0xE000ED3C))) ;
  313. // Read the Fault Address Registers. These may not contain valid values.
  314. // Check BFARVALID/MMARVALID to see if they are valid values
  315. // MemManage Fault Address Register
  316. _MMAR = (*((volatile unsigned int *)(0xE000ED34))) ;
  317. // Bus Fault Address Register
  318. _BFAR = (*((volatile unsigned int *)(0xE000ED38))) ;
  319. //__asm("BKPT #0\n") ; // Break into the debugger // NO Debugger here.
  320. asm volatile("mrs %0, ipsr\n" : "=r" (addr)::);
  321. printf("\nFault irq %d\n", addr & 0x1FF);
  322. printf(" stacked_r0 :: %x\n", stacked_r0);
  323. printf(" stacked_r1 :: %x\n", stacked_r1);
  324. printf(" stacked_r2 :: %x\n", stacked_r2);
  325. printf(" stacked_r3 :: %x\n", stacked_r3);
  326. printf(" stacked_r12 :: %x\n", stacked_r12);
  327. printf(" stacked_lr :: %x\n", stacked_lr);
  328. printf(" stacked_pc :: %x\n", stacked_pc);
  329. printf(" stacked_psr :: %x\n", stacked_psr);
  330. printf(" _CFSR :: %x\n", _CFSR);
  331. if(_CFSR > 0){
  332. //Memory Management Faults
  333. if((_CFSR & 1) == 1){
  334. printf(" (IACCVIOL) Instruction Access Violation\n");
  335. } else if(((_CFSR & (0x02))>>1) == 1){
  336. printf(" (DACCVIOL) Data Access Violation\n");
  337. } else if(((_CFSR & (0x08))>>3) == 1){
  338. printf(" (MUNSTKERR) MemMange Fault on Unstacking\n");
  339. } else if(((_CFSR & (0x10))>>4) == 1){
  340. printf(" (MSTKERR) MemMange Fault on stacking\n");
  341. } else if(((_CFSR & (0x20))>>5) == 1){
  342. printf(" (MLSPERR) MemMange Fault on FP Lazy State\n");
  343. }
  344. if(((_CFSR & (0x80))>>7) == 1){
  345. printf(" (MMARVALID) MemMange Fault Address Valid\n");
  346. }
  347. //Bus Fault Status Register
  348. if(((_CFSR & 0x100)>>8) == 1){
  349. printf(" (IBUSERR) Instruction Bus Error\n");
  350. } else if(((_CFSR & (0x200))>>9) == 1){
  351. printf(" (PRECISERR) Data bus error(address in BFAR)\n");
  352. } else if(((_CFSR & (0x400))>>10) == 1){
  353. printf(" (IMPRECISERR) Data bus error but address not related to instruction\n");
  354. } else if(((_CFSR & (0x800))>>11) == 1){
  355. printf(" (UNSTKERR) Bus Fault on unstacking for a return from exception \n");
  356. } else if(((_CFSR & (0x1000))>>12) == 1){
  357. printf(" (STKERR) Bus Fault on stacking for exception entry\n");
  358. } else if(((_CFSR & (0x2000))>>13) == 1){
  359. printf(" (LSPERR) Bus Fault on FP lazy state preservation\n");
  360. }
  361. if(((_CFSR & (0x8000))>>15) == 1){
  362. printf(" (BFARVALID) Bus Fault Address Valid\n");
  363. }
  364. //Usuage Fault Status Register
  365. if(((_CFSR & 0x10000)>>16) == 1){
  366. printf(" (UNDEFINSTR) Undefined instruction\n");
  367. } else if(((_CFSR & (0x20000))>>17) == 1){
  368. printf(" (INVSTATE) Instruction makes illegal use of EPSR)\n");
  369. } else if(((_CFSR & (0x40000))>>18) == 1){
  370. printf(" (INVPC) Usage fault: invalid EXC_RETURN\n");
  371. } else if(((_CFSR & (0x80000))>>19) == 1){
  372. printf(" (NOCP) No Coprocessor \n");
  373. } else if(((_CFSR & (0x1000000))>>24) == 1){
  374. printf(" (UNALIGNED) Unaligned access UsageFault\n");
  375. } else if(((_CFSR & (0x2000000))>>25) == 1){
  376. printf(" (DIVBYZERO) Divide by zero\n");
  377. }
  378. }
  379. printf(" _HFSR :: %x\n", _HFSR);
  380. if(_HFSR > 0){
  381. //Memory Management Faults
  382. if(((_HFSR & (0x02))>>1) == 1){
  383. printf(" (VECTTBL) Bus Fault on Vec Table Read\n");
  384. } else if(((_HFSR & (0x40000000))>>30) == 1){
  385. printf(" (FORCED) Forced Hard Fault\n");
  386. } else if(((_HFSR & (0x80000000))>>31) == 31){
  387. printf(" (DEBUGEVT) Reserved for Debug\n");
  388. }
  389. }
  390. printf(" _DFSR :: %x\n", _DFSR);
  391. printf(" _AFSR :: %x\n", _AFSR);
  392. printf(" _BFAR :: %x\n", _BFAR);
  393. printf(" _MMAR :: %x\n", _MMAR);
  394. #endif
  395. IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 5; // pin 13
  396. IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = IOMUXC_PAD_DSE(7);
  397. GPIO2_GDIR |= (1 << 3);
  398. GPIO2_DR_SET = (1 << 3);
  399. GPIO2_DR_CLEAR = (1 << 3); //digitalWrite(13, LOW);
  400. if ( F_CPU_ACTUAL >= 600000000 )
  401. set_arm_clock(300000000);
  402. while (1)
  403. {
  404. GPIO2_DR_SET = (1 << 3); //digitalWrite(13, HIGH);
  405. // digitalWrite(13, HIGH);
  406. for (nn = 0; nn < 2000000/2; nn++) ;
  407. GPIO2_DR_CLEAR = (1 << 3); //digitalWrite(13, LOW);
  408. // digitalWrite(13, LOW);
  409. for (nn = 0; nn < 18000000/2; nn++) ;
  410. }
  411. }
  412. __attribute__((weak))
  413. void userDebugDump(){
  414. volatile unsigned int nn;
  415. printf("\nuserDebugDump() in startup.c ___ \n");
  416. while (1)
  417. {
  418. GPIO2_DR_SET = (1 << 3); //digitalWrite(13, HIGH);
  419. // digitalWrite(13, HIGH);
  420. for (nn = 0; nn < 2000000; nn++) ;
  421. GPIO2_DR_CLEAR = (1 << 3); //digitalWrite(13, LOW);
  422. // digitalWrite(13, LOW);
  423. for (nn = 0; nn < 18000000; nn++) ;
  424. GPIO2_DR_SET = (1 << 3); //digitalWrite(13, HIGH);
  425. // digitalWrite(13, HIGH);
  426. for (nn = 0; nn < 20000000; nn++) ;
  427. GPIO2_DR_CLEAR = (1 << 3); //digitalWrite(13, LOW);
  428. // digitalWrite(13, LOW);
  429. for (nn = 0; nn < 10000000; nn++) ;
  430. }
  431. }
  432. __attribute__((weak))
  433. void PJRCunused_interrupt_vector(void)
  434. {
  435. // TODO: polling Serial to complete buffered transmits
  436. #ifdef PRINT_DEBUG_STUFF
  437. uint32_t addr;
  438. asm volatile("mrs %0, ipsr\n" : "=r" (addr)::);
  439. printf("\nirq %d\n", addr & 0x1FF);
  440. asm("ldr %0, [sp, #52]" : "=r" (addr) ::);
  441. printf(" %x\n", addr);
  442. asm("ldr %0, [sp, #48]" : "=r" (addr) ::);
  443. printf(" %x\n", addr);
  444. asm("ldr %0, [sp, #44]" : "=r" (addr) ::);
  445. printf(" %x\n", addr);
  446. asm("ldr %0, [sp, #40]" : "=r" (addr) ::);
  447. printf(" %x\n", addr);
  448. asm("ldr %0, [sp, #36]" : "=r" (addr) ::);
  449. printf(" %x\n", addr);
  450. asm("ldr %0, [sp, #33]" : "=r" (addr) ::);
  451. printf(" %x\n", addr);
  452. asm("ldr %0, [sp, #34]" : "=r" (addr) ::);
  453. printf(" %x\n", addr);
  454. asm("ldr %0, [sp, #28]" : "=r" (addr) ::);
  455. printf(" %x\n", addr);
  456. asm("ldr %0, [sp, #24]" : "=r" (addr) ::);
  457. printf(" %x\n", addr);
  458. asm("ldr %0, [sp, #20]" : "=r" (addr) ::);
  459. printf(" %x\n", addr);
  460. asm("ldr %0, [sp, #16]" : "=r" (addr) ::);
  461. printf(" %x\n", addr);
  462. asm("ldr %0, [sp, #12]" : "=r" (addr) ::);
  463. printf(" %x\n", addr);
  464. asm("ldr %0, [sp, #8]" : "=r" (addr) ::);
  465. printf(" %x\n", addr);
  466. asm("ldr %0, [sp, #4]" : "=r" (addr) ::);
  467. printf(" %x\n", addr);
  468. asm("ldr %0, [sp, #0]" : "=r" (addr) ::);
  469. printf(" %x\n", addr);
  470. #endif
  471. #if 1
  472. if ( F_CPU_ACTUAL >= 600000000 )
  473. set_arm_clock(100000000);
  474. IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 5; // pin 13
  475. IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = IOMUXC_PAD_DSE(7);
  476. GPIO2_GDIR |= (1<<3);
  477. GPIO2_DR_SET = (1<<3);
  478. while (1) {
  479. volatile uint32_t n;
  480. GPIO2_DR_SET = (1<<3); //digitalWrite(13, HIGH);
  481. for (n=0; n < 2000000/6; n++) ;
  482. GPIO2_DR_CLEAR = (1<<3); //digitalWrite(13, LOW);
  483. for (n=0; n < 1500000/6; n++) ;
  484. }
  485. #else
  486. if ( F_CPU_ACTUAL >= 600000000 )
  487. set_arm_clock(100000000);
  488. while (1) asm ("WFI");
  489. #endif
  490. }
  491. __attribute__((section(".startup"), optimize("no-tree-loop-distribute-patterns")))
  492. static void memory_copy(uint32_t *dest, const uint32_t *src, uint32_t *dest_end)
  493. {
  494. if (dest == src) return;
  495. while (dest < dest_end) {
  496. *dest++ = *src++;
  497. }
  498. }
  499. __attribute__((section(".startup"), optimize("no-tree-loop-distribute-patterns")))
  500. static void memory_clear(uint32_t *dest, uint32_t *dest_end)
  501. {
  502. while (dest < dest_end) {
  503. *dest++ = 0;
  504. }
  505. }
  506. // syscall functions need to be in the same C file as the entry point "ResetVector"
  507. // otherwise the linker will discard them in some cases.
  508. #include <errno.h>
  509. // from the linker script
  510. extern unsigned long _heap_start;
  511. extern unsigned long _heap_end;
  512. char *__brkval = (char *)&_heap_start;
  513. void * _sbrk(int incr)
  514. {
  515. char *prev = __brkval;
  516. if (incr != 0) {
  517. if (prev + incr > (char *)&_heap_end) {
  518. errno = ENOMEM;
  519. return (void *)-1;
  520. }
  521. __brkval = prev + incr;
  522. }
  523. return prev;
  524. }
  525. __attribute__((weak))
  526. int _read(int file, char *ptr, int len)
  527. {
  528. return 0;
  529. }
  530. __attribute__((weak))
  531. int _close(int fd)
  532. {
  533. return -1;
  534. }
  535. #include <sys/stat.h>
  536. __attribute__((weak))
  537. int _fstat(int fd, struct stat *st)
  538. {
  539. st->st_mode = S_IFCHR;
  540. return 0;
  541. }
  542. __attribute__((weak))
  543. int _isatty(int fd)
  544. {
  545. return 1;
  546. }
  547. __attribute__((weak))
  548. int _lseek(int fd, long long offset, int whence)
  549. {
  550. return -1;
  551. }
  552. __attribute__((weak))
  553. void _exit(int status)
  554. {
  555. while (1) asm ("WFI");
  556. }
  557. __attribute__((weak))
  558. void __cxa_pure_virtual()
  559. {
  560. while (1) asm ("WFI");
  561. }
  562. __attribute__((weak))
  563. int __cxa_guard_acquire (char *g)
  564. {
  565. return !(*g);
  566. }
  567. __attribute__((weak))
  568. void __cxa_guard_release(char *g)
  569. {
  570. *g = 1;
  571. }
  572. __attribute__((weak))
  573. void abort(void)
  574. {
  575. while (1) asm ("WFI");
  576. }