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Teensy 4.1 core updated for C++20
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teensy-core-4.1/teensy3/SPIFIFO.h

238 rindas
10KB
Neapstrādāts Vainot Vēsture 

  1. #ifndef _SPIFIFO_h_

  2. #define _SPIFIFO_h_

  3. 

  4. #include "avr_emulation.h"

  5. 

  6. #ifdef KINETISK

  7. 

  8. #if F_BUS == 60000000

  9. #define HAS_SPIFIFO

  10. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(60 / 3) * ((1+1)/2) = 20 MHz

  11. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0))                //(60 / 2) * ((1+0)/2) = 15 MHz

  12. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(60 / 5) * ((1+1)/2)

  13. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1))                //(60 / 2) * ((1+0)/4) = 7.5 MHz

  14. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(2) | SPI_CTAR_BR(0))                //(60 / 5) * ((1+0)/2)

  15. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(2) | SPI_CTAR_BR(2) | SPI_CTAR_DBR) //(60 / 5) * ((1+1)/6)

  16. 

  17. #elif F_BUS == 56000000

  18. #define HAS_SPIFIFO

  19. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(56 / 3) * ((1+1)/2) = 18.67

  20. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0))                //(56 / 2) * ((1+0)/2) = 14

  21. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(56 / 5) * ((1+1)/2) = 11.2

  22. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(3) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(56 / 7) * ((1+1)/2)

  23. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(2) | SPI_CTAR_BR(0))                //(56 / 5) * ((1+0)/2)

  24. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(3) | SPI_CTAR_BR(0))                //(56 / 7) * ((1+0)/2)

  25. 

  26. #elif F_BUS == 48000000

  27. #define HAS_SPIFIFO

  28. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(48 / 2) * ((1+1)/2)

  29. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(48 / 3) * ((1+1)/2)

  30. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0))                //(48 / 2) * ((1+0)/2)

  31. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(2) | SPI_CTAR_DBR) //(48 / 2) * ((1+1)/6)

  32. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1))                //(48 / 2) * ((1+0)/4)

  33. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(2))                //(48 / 2) * ((1+0)/6)

  34. 

  35. #elif F_BUS == 40000000

  36. #define HAS_SPIFIFO

  37. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(40 / 2) * ((1+1)/2) = 20

  38. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(40 / 3) * ((1+1)/2) = 13.33

  39. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0))                //(40 / 2) * ((1+0)/2) = 10

  40. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(40 / 5) * ((1+1)/2)

  41. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(3) | SPI_CTAR_BR(1) | SPI_CTAR_DBR) //(40 / 7) * ((1+1)/2) = 5.71

  42. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(2) | SPI_CTAR_BR(1))                //(40 / 5) * ((1+0)/2)

  43. 

  44. #elif F_BUS == 36000000

  45. #define HAS_SPIFIFO

  46. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(36 / 2) * ((1+1)/2) = 18

  47. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(36 / 3) * ((1+1)/2) = 12

  48. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(36 / 3) * ((1+1)/2) = 12

  49. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(36 / 5) * ((1+1)/2) = 7.2

  50. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(2) | SPI_CTAR_DBR) //(36 / 2) * ((1+1)/6)

  51. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(1) | SPI_CTAR_BR(2) | SPI_CTAR_DBR) //(36 / 3) * ((1+1)/6)

  52. 

  53. #elif F_BUS == 24000000

  54. #define HAS_SPIFIFO

  55. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(24 / 2) * ((1+1)/2)  12 MHz

  56. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(24 / 2) * ((1+1)/2)  12 MHz

  57. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(24 / 2) * ((1+1)/2)

  58. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(24 / 3) * ((1+1)/2)

  59. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0))                //(24 / 2) * ((1+0)/2)

  60. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(2) | SPI_CTAR_DBR) //(24 / 2) * ((1+1)/6)

  61. 

  62. #elif F_BUS == 16000000

  63. #define HAS_SPIFIFO

  64. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) | SPI_CTAR_DBR) //(16 / 2) * ((1+1)/8) = 2 MHz

  65. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) | SPI_CTAR_DBR) //(16 / 2) * ((1+1)/8) = 2 MHz

  66. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) | SPI_CTAR_DBR) //(16 / 2) * ((1+1)/8) = 2 MHz

  67. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) | SPI_CTAR_DBR) //(16 / 2) * ((1+1)/8) = 2 MHz

  68. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) | SPI_CTAR_DBR) //(16 / 2) * ((1+1)/8) = 2 MHz

  69. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) | SPI_CTAR_DBR) //(16 / 2) * ((1+1)/8) = 2 MHz

  70. 

  71. #elif F_BUS == 8000000

  72. #define HAS_SPIFIFO

  73. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1) | SPI_CTAR_DBR) //(8 / 2) * ((1+1)/4) = 2 MHz

  74. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1) | SPI_CTAR_DBR) //(8 / 2) * ((1+1)/4) = 2 MHz

  75. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1) | SPI_CTAR_DBR) //(8 / 2) * ((1+1)/4) = 2 MHz

  76. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1) | SPI_CTAR_DBR) //(8 / 2) * ((1+1)/4) = 2 MHz

  77. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1) | SPI_CTAR_DBR) //(8 / 2) * ((1+1)/4) = 2 MHz

  78. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1) | SPI_CTAR_DBR) //(8 / 2) * ((1+1)/4) = 2 MHz

  79. 

  80. #elif F_BUS == 4000000

  81. #define HAS_SPIFIFO

  82. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 2 MHz

  83. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 2 MHz

  84. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 2 MHz

  85. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 2 MHz

  86. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 2 MHz

  87. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 2 MHz

  88. 

  89. #elif F_BUS == 2000000

  90. #define HAS_SPIFIFO

  91. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 1 MHz

  92. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 1 MHz

  93. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 1 MHz

  94. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 1 MHz

  95. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 1 MHz

  96. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 1 MHz

  97. 

  98. #endif // F_BUS

  99. 

  100. #endif // KINETISK

  101. 

  102. /*

  103. #! /usr/bin/perl

  104. $clock = 60;

  105. for $i (2, 3, 5, 7) {

  106.         for $j (0, 1) {

  107.                 for $k (2, 4, 6, 8, 16, 32) {

  108.                         $out = $clock / $i * (1 + $j) / $k;

  109.                         printf "%0.2f :  ", $out;

  110.                         print "$clock / $i * (1 + $j) / $k = $out\n";

  111.                 }

  112.         }

  113. }

  114. */

  115. 

  116. // sck = F_BUS / PBR * ((1+DBR)/BR)

  117. //  PBR = 2, 3, 5, 7

  118. //  DBR = 0, 1         -- zero preferred

  119. //  BR = 2, 4, 6, 8, 16, 32, 64, 128, 256, 512

  120. 

  121. 

  122. #ifdef HAS_SPIFIFO

  123. 

  124. #ifndef SPI_MODE0

  125. #define SPI_MODE0 0x00  // CPOL = 0, CPHA = 0

  126. #define SPI_MODE1 0x04  // CPOL = 0, CPHA = 1

  127. #define SPI_MODE2 0x08  // CPOL = 1, CPHA = 0

  128. #define SPI_MODE3 0x0C  // CPOL = 1, CPHA = 1

  129. #endif

  130. 

  131. #define SPI_CONTINUE 1

  132. 

  133. class SPIFIFOclass

  134. {

  135. public:

  136. 	inline void begin(uint8_t pin, uint32_t speed, uint32_t mode=SPI_MODE0) __attribute__((always_inline)) {

  137. 		uint32_t p, ctar = speed;

  138. 		SIM_SCGC6 |= SIM_SCGC6_SPI0;

  139. 

  140. 		KINETISK_SPI0.MCR = SPI_MCR_MSTR | SPI_MCR_MDIS | SPI_MCR_HALT | SPI_MCR_PCSIS(0x1F);

  141. 		if (mode & 0x08) ctar |= SPI_CTAR_CPOL;

  142. 		if (mode & 0x04) {

  143. 			ctar |= SPI_CTAR_CPHA;

  144. 			ctar |= (ctar & 0x0F) << 8;

  145. 		} else {

  146. 			ctar |= (ctar & 0x0F) << 12;

  147. 		}

  148. 		KINETISK_SPI0.CTAR0 = ctar | SPI_CTAR_FMSZ(7);

  149. 		KINETISK_SPI0.CTAR1 = ctar | SPI_CTAR_FMSZ(15);

  150. 		if (pin == 10) {         // PTC4

  151. 			CORE_PIN10_CONFIG = PORT_PCR_MUX(2);

  152. 			p = 0x01;

  153. 		} else if (pin == 2) {   // PTD0

  154. 			CORE_PIN2_CONFIG = PORT_PCR_MUX(2);

  155. 			p = 0x01;

  156. 		} else if (pin == 9) {   // PTC3

  157. 			CORE_PIN9_CONFIG = PORT_PCR_MUX(2);

  158. 			p = 0x02;

  159. 		} else if (pin == 6) {   // PTD4

  160. 			CORE_PIN6_CONFIG = PORT_PCR_MUX(2);

  161. 			p = 0x02;

  162. 		} else if (pin == 20) {  // PTD5

  163. 			CORE_PIN20_CONFIG = PORT_PCR_MUX(2);

  164. 			p = 0x04;

  165. 		} else if (pin == 23) {  // PTC2

  166. 			CORE_PIN23_CONFIG = PORT_PCR_MUX(2);

  167. 			p = 0x04;

  168. 		} else if (pin == 21) {  // PTD6

  169. 			CORE_PIN21_CONFIG = PORT_PCR_MUX(2);

  170. 			p = 0x08;

  171. 		} else if (pin == 22) {  // PTC1

  172. 			CORE_PIN22_CONFIG = PORT_PCR_MUX(2);

  173. 			p = 0x08;

  174. 		} else if (pin == 15) {  // PTC0

  175. 			CORE_PIN15_CONFIG = PORT_PCR_MUX(2);

  176. 			p = 0x10;

  177. 		} else {

  178. 			reg = portOutputRegister(pin);

  179. 			pinMode(pin, OUTPUT);

  180. 			*reg = 1;

  181. 			p = 0;

  182. 		}

  183. 		pcs = p;

  184. 		clear();

  185. 		SPCR.enable_pins();

  186. 	}

  187. 	inline void write(uint32_t b, uint32_t cont=0) __attribute__((always_inline)) {

  188. 		uint32_t pcsbits = pcs << 16;

  189. 		if (pcsbits) {

  190. 			KINETISK_SPI0.PUSHR = (b & 0xFF) | pcsbits | (cont ? SPI_PUSHR_CONT : 0);

  191. 			while (((KINETISK_SPI0.SR) & (15 << 12)) > (3 << 12)) ; // wait if FIFO full

  192. 		} else {

  193. 			*reg = 0;

  194. 			KINETISK_SPI0.SR = SPI_SR_EOQF;

  195. 			KINETISK_SPI0.PUSHR = (b & 0xFF) | (cont ? 0 : SPI_PUSHR_EOQ);

  196. 			if (cont) {

  197. 				while (((KINETISK_SPI0.SR) & (15 << 12)) > (3 << 12)) ;

  198. 			} else {

  199. 				while (!(KINETISK_SPI0.SR & SPI_SR_EOQF)) ;

  200. 				*reg = 1;

  201. 			}

  202. 		}

  203. 	}

  204. 	inline void write16(uint32_t b, uint32_t cont=0) __attribute__((always_inline)) {

  205. 		uint32_t pcsbits = pcs << 16;

  206. 		if (pcsbits) {

  207. 			KINETISK_SPI0.PUSHR = (b & 0xFFFF) | (pcs << 16) |

  208. 				(cont ? SPI_PUSHR_CONT : 0) | SPI_PUSHR_CTAS(1);

  209. 			while (((KINETISK_SPI0.SR) & (15 << 12)) > (3 << 12)) ;

  210. 		} else {

  211. 			*reg = 0;

  212. 			KINETISK_SPI0.SR = SPI_SR_EOQF;

  213. 			KINETISK_SPI0.PUSHR = (b & 0xFFFF) | (cont ? 0 : SPI_PUSHR_EOQ) | SPI_PUSHR_CTAS(1);

  214. 			if (cont) {

  215. 				while (((KINETISK_SPI0.SR) & (15 << 12)) > (3 << 12)) ;

  216. 			} else {

  217. 				while (!(KINETISK_SPI0.SR & SPI_SR_EOQF)) ;

  218. 				*reg = 1;

  219. 			}

  220. 		}

  221. 	}

  222. 	inline uint32_t read(void) __attribute__((always_inline)) {

  223. 		while ((KINETISK_SPI0.SR & (15 << 4)) == 0) ;  // TODO, could wait forever

  224. 		return KINETISK_SPI0.POPR;

  225. 	}

  226. 	inline void clear(void) __attribute__((always_inline)) {

  227. 		KINETISK_SPI0.MCR = SPI_MCR_MSTR | SPI_MCR_PCSIS(0x1F) | SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF;

  228. 	}

  229. private:

  230. 	static uint8_t pcs;

  231. 	static volatile uint8_t *reg;

  232. };

  233. extern SPIFIFOclass SPIFIFO;

  234. 

  235. #endif // HAS_SPIFIFO

  236. 

  237. #endif