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Teensy 4.1 core updated for C++20
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teensy-core-4.1/teensy3/DMAChannel.h

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Neapstrādāts Vainot Vēsture 

  1. #ifndef DMAChannel_h_

  2. #define DMAChannel_h_

  3. 

  4. #include "kinetis.h"

  5. 

  6. // This code is a work-in-progress.  It's incomplete and not usable yet...

  7. //

  8. // http://forum.pjrc.com/threads/25778-Could-there-be-something-like-an-ISR-template-function/page3

  9. 

  10. 

  11. // known libraries with DMA usage (in need of porting to this new scheme):

  12. //

  13. // https://github.com/PaulStoffregen/Audio

  14. // https://github.com/PaulStoffregen/OctoWS2811

  15. // https://github.com/pedvide/ADC

  16. // https://github.com/duff2013/SerialEvent

  17. // https://github.com/pixelmatix/SmartMatrix

  18. // https://github.com/crteensy/DmaSpi <-- DmaSpi has adopted this scheme

  19. 

  20. #ifdef __cplusplus

  21. 

  22. #define DMACHANNEL_HAS_BEGIN

  23. #define DMACHANNEL_HAS_BOOLEAN_CTOR

  24. 

  25. class DMABaseClass {

  26. public:

  27. 	typedef struct __attribute__((packed)) {

  28. 		volatile const void * volatile SADDR;

  29. 		int16_t SOFF;

  30. 		union { uint16_t ATTR;

  31. 			struct { uint8_t ATTR_DST; uint8_t ATTR_SRC; }; };

  32. 		union { uint32_t NBYTES; uint32_t NBYTES_MLNO;

  33. 			uint32_t NBYTES_MLOFFNO; uint32_t NBYTES_MLOFFYES; };

  34. 		int32_t SLAST;

  35. 		volatile void * volatile DADDR;

  36. 		int16_t DOFF;

  37. 		union { volatile uint16_t CITER;

  38. 			volatile uint16_t CITER_ELINKYES; volatile uint16_t CITER_ELINKNO; };

  39. 		int32_t DLASTSGA;

  40. 		volatile uint16_t CSR;

  41. 		union { volatile uint16_t BITER;

  42. 			volatile uint16_t BITER_ELINKYES; volatile uint16_t BITER_ELINKNO; };

  43. 	} TCD_t;

  44. 	TCD_t *TCD;

  45. 

  46. 	/***************************************/

  47. 	/**    Data Transfer                  **/

  48. 	/***************************************/

  49. 

  50. 	// Use a single variable as the data source.  Typically a register

  51. 	// for receiving data from one of the hardware peripherals is used.

  52. 	void source(volatile const signed char &p) { source(*(volatile const uint8_t *)&p); }

  53. 	void source(volatile const unsigned char &p) {

  54. 		TCD->SADDR = &p;

  55. 		TCD->SOFF = 0;

  56. 		TCD->ATTR_SRC = 0;

  57. 		if ((uint32_t)&p < 0x40000000 || TCD->NBYTES == 0) TCD->NBYTES = 1;

  58. 		TCD->SLAST = 0;

  59. 	}

  60. 	void source(volatile const signed short &p) { source(*(volatile const uint16_t *)&p); }

  61. 	void source(volatile const unsigned short &p) {

  62. 		TCD->SADDR = &p;

  63. 		TCD->SOFF = 0;

  64. 		TCD->ATTR_SRC = 1;

  65. 		if ((uint32_t)&p < 0x40000000 || TCD->NBYTES == 0) TCD->NBYTES = 2;

  66. 		TCD->SLAST = 0;

  67. 	}

  68. 	void source(volatile const signed int &p) { source(*(volatile const uint32_t *)&p); }

  69. 	void source(volatile const unsigned int &p) { source(*(volatile const uint32_t *)&p); }

  70. 	void source(volatile const signed long &p) { source(*(volatile const uint32_t *)&p); }

  71. 	void source(volatile const unsigned long &p) {

  72. 		TCD->SADDR = &p;

  73. 		TCD->SOFF = 0;

  74. 		TCD->ATTR_SRC = 2;

  75. 		if ((uint32_t)&p < 0x40000000 || TCD->NBYTES == 0) TCD->NBYTES = 4;

  76. 		TCD->SLAST = 0;

  77. 	}

  78. 

  79. 	// Use a buffer (array of data) as the data source.  Typically a

  80. 	// buffer for transmitting data is used.

  81. 	void sourceBuffer(volatile const signed char p[], unsigned int len) {

  82. 		sourceBuffer((volatile const uint8_t *)p, len); }

  83. 	void sourceBuffer(volatile const unsigned char p[], unsigned int len) {

  84. 		TCD->SADDR = p;

  85. 		TCD->SOFF = 1;

  86. 		TCD->ATTR_SRC = 0;

  87. 		TCD->NBYTES = 1;

  88. 		TCD->SLAST = -len;

  89. 		TCD->BITER = len;

  90. 		TCD->CITER = len;

  91. 	}

  92. 	void sourceBuffer(volatile const signed short p[], unsigned int len) {

  93. 		sourceBuffer((volatile const uint16_t *)p, len); }

  94. 	void sourceBuffer(volatile const unsigned short p[], unsigned int len) {

  95. 		TCD->SADDR = p;

  96. 		TCD->SOFF = 2;

  97. 		TCD->ATTR_SRC = 1;

  98. 		TCD->NBYTES = 2;

  99. 		TCD->SLAST = -len;

  100. 		TCD->BITER = len / 2;

  101. 		TCD->CITER = len / 2;

  102. 	}

  103. 	void sourceBuffer(volatile const signed int p[], unsigned int len) {

  104. 		sourceBuffer((volatile const uint32_t *)p, len); }

  105. 	void sourceBuffer(volatile const unsigned int p[], unsigned int len) {

  106. 		sourceBuffer((volatile const uint32_t *)p, len); }

  107. 	void sourceBuffer(volatile const signed long p[], unsigned int len) {

  108. 		sourceBuffer((volatile const uint32_t *)p, len); }

  109. 	void sourceBuffer(volatile const unsigned long p[], unsigned int len) {

  110. 		TCD->SADDR = p;

  111. 		TCD->SOFF = 4;

  112. 		TCD->ATTR_SRC = 2;

  113. 		TCD->NBYTES = 4;

  114. 		TCD->SLAST = -len;

  115. 		TCD->BITER = len / 4;

  116. 		TCD->CITER = len / 4;

  117. 	}

  118. 

  119. 	// Use a circular buffer as the data source

  120. 	void sourceCircular(volatile const signed char p[], unsigned int len) {

  121. 		sourceCircular((volatile const uint8_t *)p, len); }

  122. 	void sourceCircular(volatile const unsigned char p[], unsigned int len) {

  123. 		TCD->SADDR = p;

  124. 		TCD->SOFF = 1;

  125. 		TCD->ATTR_SRC = ((31 - __builtin_clz(len)) << 3);

  126. 		TCD->NBYTES = 1;

  127. 		TCD->SLAST = 0;

  128. 		TCD->BITER = len;

  129. 		TCD->CITER = len;

  130. 	}

  131. 	void sourceCircular(volatile const signed short p[], unsigned int len) {

  132. 		sourceCircular((volatile const uint16_t *)p, len); }

  133. 	void sourceCircular(volatile const unsigned short p[], unsigned int len) {

  134. 		TCD->SADDR = p;

  135. 		TCD->SOFF = 2;

  136. 		TCD->ATTR_SRC = ((31 - __builtin_clz(len)) << 3) | 1;

  137. 		TCD->NBYTES = 2;

  138. 		TCD->SLAST = 0;

  139. 		TCD->BITER = len / 2;

  140. 		TCD->CITER = len / 2;

  141. 	}

  142. 	void sourceCircular(volatile const signed int p[], unsigned int len) {

  143. 		sourceCircular((volatile const uint32_t *)p, len); }

  144. 	void sourceCircular(volatile const unsigned int p[], unsigned int len) {

  145. 		sourceCircular((volatile const uint32_t *)p, len); }

  146. 	void sourceCircular(volatile const signed long p[], unsigned int len) {

  147. 		sourceCircular((volatile const uint32_t *)p, len); }

  148. 	void sourceCircular(volatile const unsigned long p[], unsigned int len) {

  149. 		TCD->SADDR = p;

  150. 		TCD->SOFF = 4;

  151. 		TCD->ATTR_SRC = ((31 - __builtin_clz(len)) << 3) | 2;

  152. 		TCD->NBYTES = 4;

  153. 		TCD->SLAST = 0;

  154. 		TCD->BITER = len / 4;

  155. 		TCD->CITER = len / 4;

  156. 	}

  157. 

  158. 	// Use a single variable as the data destination.  Typically a register

  159. 	// for transmitting data to one of the hardware peripherals is used.

  160. 	void destination(volatile signed char &p) { destination(*(volatile uint8_t *)&p); }

  161. 	void destination(volatile unsigned char &p) {

  162. 		TCD->DADDR = &p;

  163. 		TCD->DOFF = 0;

  164. 		TCD->ATTR_DST = 0;

  165. 		if ((uint32_t)&p < 0x40000000 || TCD->NBYTES == 0) TCD->NBYTES = 1;

  166. 		TCD->DLASTSGA = 0;

  167. 	}

  168. 	void destination(volatile signed short &p) { destination(*(volatile uint16_t *)&p); }

  169. 	void destination(volatile unsigned short &p) {

  170. 		TCD->DADDR = &p;

  171. 		TCD->DOFF = 0;

  172. 		TCD->ATTR_DST = 1;

  173. 		if ((uint32_t)&p < 0x40000000 || TCD->NBYTES == 0) TCD->NBYTES = 2;

  174. 		TCD->DLASTSGA = 0;

  175. 	}

  176. 	void destination(volatile signed int &p) { destination(*(volatile uint32_t *)&p); }

  177. 	void destination(volatile unsigned int &p) { destination(*(volatile uint32_t *)&p); }

  178. 	void destination(volatile signed long &p) { destination(*(volatile uint32_t *)&p); }

  179. 	void destination(volatile unsigned long &p) {

  180. 		TCD->DADDR = &p;

  181. 		TCD->DOFF = 0;

  182. 		TCD->ATTR_DST = 2;

  183. 		if ((uint32_t)&p < 0x40000000 || TCD->NBYTES == 0) TCD->NBYTES = 4;

  184. 		TCD->DLASTSGA = 0;

  185. 	}

  186. 

  187. 	// Use a buffer (array of data) as the data destination.  Typically a

  188. 	// buffer for receiving data is used.

  189. 	void destinationBuffer(volatile signed char p[], unsigned int len) {

  190. 		destinationBuffer((volatile uint8_t *)p, len); }

  191. 	void destinationBuffer(volatile unsigned char p[], unsigned int len) {

  192. 		TCD->DADDR = p;

  193. 		TCD->DOFF = 1;

  194. 		TCD->ATTR_DST = 0;

  195. 		TCD->NBYTES = 1;

  196. 		TCD->DLASTSGA = -len;

  197. 		TCD->BITER = len;

  198. 		TCD->CITER = len;

  199. 	}

  200. 	void destinationBuffer(volatile signed short p[], unsigned int len) {

  201. 		destinationBuffer((volatile uint16_t *)p, len); }

  202. 	void destinationBuffer(volatile unsigned short p[], unsigned int len) {

  203. 		TCD->DADDR = p;

  204. 		TCD->DOFF = 2;

  205. 		TCD->ATTR_DST = 1;

  206. 		TCD->NBYTES = 2;

  207. 		TCD->DLASTSGA = -len;

  208. 		TCD->BITER = len / 2;

  209. 		TCD->CITER = len / 2;

  210. 	}

  211. 	void destinationBuffer(volatile signed int p[], unsigned int len) {

  212. 		destinationBuffer((volatile uint32_t *)p, len); }

  213. 	void destinationBuffer(volatile unsigned int p[], unsigned int len) {

  214. 		destinationBuffer((volatile uint32_t *)p, len); }

  215. 	void destinationBuffer(volatile signed long p[], unsigned int len) {

  216. 		destinationBuffer((volatile uint32_t *)p, len); }

  217. 	void destinationBuffer(volatile unsigned long p[], unsigned int len) {

  218. 		TCD->DADDR = p;

  219. 		TCD->DOFF = 4;

  220. 		TCD->ATTR_DST = 2;

  221. 		TCD->NBYTES = 4;

  222. 		TCD->DLASTSGA = -len;

  223. 		TCD->BITER = len / 4;

  224. 		TCD->CITER = len / 4;

  225. 	}

  226. 

  227. 	// Use a circular buffer as the data destination

  228. 	void destinationCircular(volatile signed char p[], unsigned int len) {

  229. 		destinationCircular((volatile uint8_t *)p, len); }

  230. 	void destinationCircular(volatile unsigned char p[], unsigned int len) {

  231. 		TCD->DADDR = p;

  232. 		TCD->DOFF = 1;

  233. 		TCD->ATTR_DST = ((31 - __builtin_clz(len)) << 3);

  234. 		TCD->NBYTES = 1;

  235. 		TCD->DLASTSGA = 0;

  236. 		TCD->BITER = len;

  237. 		TCD->CITER = len;

  238. 	}

  239. 	void destinationCircular(volatile signed short p[], unsigned int len) {

  240. 		destinationCircular((volatile uint16_t *)p, len); }

  241. 	void destinationCircular(volatile unsigned short p[], unsigned int len) {

  242. 		TCD->DADDR = p;

  243. 		TCD->DOFF = 2;

  244. 		TCD->ATTR_DST = ((31 - __builtin_clz(len)) << 3) | 1;

  245. 		TCD->NBYTES = 2;

  246. 		TCD->DLASTSGA = 0;

  247. 		TCD->BITER = len / 2;

  248. 		TCD->CITER = len / 2;

  249. 	}

  250. 	void destinationCircular(volatile signed int p[], unsigned int len) {

  251. 		destinationCircular((volatile uint32_t *)p, len); }

  252. 	void destinationCircular(volatile unsigned int p[], unsigned int len) {

  253. 		destinationCircular((volatile uint32_t *)p, len); }

  254. 	void destinationCircular(volatile signed long p[], unsigned int len) {

  255. 		destinationCircular((volatile uint32_t *)p, len); }

  256. 	void destinationCircular(volatile unsigned long p[], unsigned int len) {

  257. 		TCD->DADDR = p;

  258. 		TCD->DOFF = 4;

  259. 		TCD->ATTR_DST = ((31 - __builtin_clz(len)) << 3) | 2;

  260. 		TCD->NBYTES = 4;

  261. 		TCD->DLASTSGA = 0;

  262. 		TCD->BITER = len / 4;

  263. 		TCD->CITER = len / 4;

  264. 	}

  265. 

  266. 	/*************************************************/

  267. 	/**    Quantity of Data to Transfer             **/

  268. 	/*************************************************/

  269. 

  270. 	// Set the data size used for each triggered transfer

  271. 	void transferSize(unsigned int len) {

  272. 		if (len == 4) {

  273. 			TCD->NBYTES = 4;

  274. 			if (TCD->SOFF != 0) TCD->SOFF = 4;

  275. 			if (TCD->DOFF != 0) TCD->DOFF = 4;

  276. 			TCD->ATTR = (TCD->ATTR & 0xF8F8) | 0x0202;

  277. 		} else if (len == 2) {

  278. 			TCD->NBYTES = 2;

  279. 			if (TCD->SOFF != 0) TCD->SOFF = 2;

  280. 			if (TCD->DOFF != 0) TCD->DOFF = 2;

  281. 			TCD->ATTR = (TCD->ATTR & 0xF8F8) | 0x0101;

  282. 		} else {

  283. 			TCD->NBYTES = 1;

  284. 			if (TCD->SOFF != 0) TCD->SOFF = 1;

  285. 			if (TCD->DOFF != 0) TCD->DOFF = 1;

  286. 			TCD->ATTR = TCD->ATTR & 0xF8F8;

  287. 		}

  288. 	}

  289. 

  290. 	// Set the number of transfers (number of triggers until complete)

  291. 	void transferCount(unsigned int len) {

  292. 		if (len > 32767) return;

  293. 		if (len >= 512) {

  294. 			TCD->BITER = len;

  295. 			TCD->CITER = len;

  296. 		} else {

  297. 			TCD->BITER = (TCD->BITER & 0xFE00) | len;

  298. 			TCD->CITER = (TCD->CITER & 0xFE00) | len;

  299. 		}

  300. 	}

  301. 

  302. 	/*************************************************/

  303. 	/**    Special Options / Features               **/

  304. 	/*************************************************/

  305. 

  306. 	void interruptAtCompletion(void) {

  307. 		TCD->CSR |= DMA_TCD_CSR_INTMAJOR;

  308. 	}

  309. 

  310. 	void interruptAtHalf(void) {

  311. 		TCD->CSR |= DMA_TCD_CSR_INTHALF;

  312. 	}

  313. 

  314. 	void disableOnCompletion(void) {

  315. 		TCD->CSR |= DMA_TCD_CSR_DREQ;

  316. 	}

  317. 

  318. 	void replaceSettingsOnCompletion(const DMABaseClass &settings) {

  319. 		TCD->DLASTSGA = (int32_t)(settings.TCD);

  320. 		TCD->CSR &= ~DMA_TCD_CSR_DONE;

  321. 		TCD->CSR |= DMA_TCD_CSR_ESG;

  322. 	}

  323. 

  324. protected:

  325. 	// users should not be able to create instances of DMABaseClass, which

  326. 	// require the inheriting class to initialize the TCD pointer.

  327. 	DMABaseClass() {}

  328. 

  329. 	static inline void copy_tcd(TCD_t *dst, const TCD_t *src) {

  330. 		const uint32_t *p = (const uint32_t *)src;

  331. 		uint32_t *q = (uint32_t *)dst;

  332. 		uint32_t t1, t2, t3, t4;

  333. 		t1 = *p++; t2 = *p++; t3 = *p++; t4 = *p++;

  334. 		*q++ = t1; *q++ = t2; *q++ = t3; *q++ = t4;

  335. 		t1 = *p++; t2 = *p++; t3 = *p++; t4 = *p++;

  336. 		*q++ = t1; *q++ = t2; *q++ = t3; *q++ = t4;

  337. 	}

  338. };

  339. 

  340. 

  341. // DMASetting represents settings stored only in memory, which can be

  342. // applied to any DMA channel.

  343. 

  344. class DMASetting : public DMABaseClass {

  345. public:

  346. 	DMASetting() {

  347. 		TCD = &tcddata;

  348. 	}

  349. 	DMASetting(const DMASetting &c) {

  350. 		TCD = &tcddata;

  351. 		*this = c;

  352. 	}

  353. 	DMASetting(const DMABaseClass &c) {

  354. 		TCD = &tcddata;

  355. 		*this = c;

  356. 	}

  357. 	DMASetting & operator = (const DMABaseClass &rhs) {

  358. 		copy_tcd(TCD, rhs.TCD);

  359. 		return *this;

  360. 	}

  361. private:

  362. 	TCD_t tcddata __attribute__((aligned(32)));

  363. };

  364. 

  365. 

  366. // DMAChannel reprents an actual DMA channel and its current settings

  367. 

  368. class DMAChannel : public DMABaseClass {

  369. public:

  370. 	/*************************************************/

  371. 	/**    Channel Allocation                       **/

  372. 	/*************************************************/

  373. 

  374. 	DMAChannel() {

  375. 		begin();

  376. 	}

  377. 	DMAChannel(const DMAChannel &c) {

  378. 		TCD = c.TCD;

  379. 		channel = c.channel;

  380. 	}

  381. 	DMAChannel(const DMASetting &c) {

  382. 		begin();

  383. 		copy_tcd(TCD, c.TCD);

  384. 	}

  385. 	DMAChannel(bool allocate) {

  386. 		if (allocate) begin();

  387. 	}

  388. 	DMAChannel & operator = (const DMAChannel &rhs) {

  389. 		if (channel != rhs.channel) {

  390. 			release();

  391. 			TCD = rhs.TCD;

  392. 			channel = rhs.channel;

  393. 		}

  394. 		return *this;

  395. 	}

  396. 	DMAChannel & operator = (const DMASetting &rhs) {

  397. 		copy_tcd(TCD, rhs.TCD);

  398. 		return *this;

  399. 	}

  400. 	~DMAChannel() {

  401. 		release();

  402. 	}

  403. 	void begin(bool force_initialization = false);

  404. private:

  405. 	void release(void);

  406. 

  407. public:

  408. 	/***************************************/

  409. 	/**    Triggering                     **/

  410. 	/***************************************/

  411. 

  412. 	// Triggers cause the DMA channel to actually move data.  Each

  413. 	// trigger moves a single data unit, which is typically 8, 16 or

  414. 	// 32 bits.  If a channel is configured for 200 transfers

  415. 

  416. 	// Use a hardware trigger to make the DMA channel run

  417. 	void triggerAtHardwareEvent(uint8_t source) {

  418. 		volatile uint8_t *mux;

  419. 		mux = (volatile uint8_t *)&(DMAMUX0_CHCFG0) + channel;

  420. 		*mux = 0;

  421. 		*mux = (source & 63) | DMAMUX_ENABLE;

  422. 	}

  423. 

  424. 	// Use another DMA channel as the trigger, causing this

  425. 	// channel to trigger after each transfer is makes, except

  426. 	// the its last transfer.  This effectively makes the 2

  427. 	// channels run in parallel until the last transfer

  428. 	void triggerAtTransfersOf(DMABaseClass &ch) {

  429. 		ch.TCD->BITER = (ch.TCD->BITER & ~DMA_TCD_BITER_ELINKYES_LINKCH_MASK)

  430. 		  | DMA_TCD_BITER_ELINKYES_LINKCH(channel) | DMA_TCD_BITER_ELINKYES_ELINK;

  431. 		ch.TCD->CITER = ch.TCD->BITER ;

  432. 	}

  433. 

  434. 	// Use another DMA channel as the trigger, causing this

  435. 	// channel to trigger when the other channel completes.

  436. 	void triggerAtCompletionOf(DMABaseClass &ch) {

  437. 		ch.TCD->CSR = (ch.TCD->CSR & ~(DMA_TCD_CSR_MAJORLINKCH_MASK|DMA_TCD_CSR_DONE))

  438. 		  | DMA_TCD_CSR_MAJORLINKCH(channel) | DMA_TCD_CSR_MAJORELINK;

  439. 	}

  440. 

  441. 	// Cause this DMA channel to be continuously triggered, so

  442. 	// it will move data as rapidly as possible, without waiting.

  443. 	// Normally this would be used with disableOnCompletion().

  444. 	void triggerContinuously(void) {

  445. 		volatile uint8_t *mux = (volatile uint8_t *)&DMAMUX0_CHCFG0;

  446. 		mux[channel] = 0;

  447. #if DMAMUX_NUM_SOURCE_ALWAYS >= DMA_NUM_CHANNELS

  448. 		mux[channel] = DMAMUX_SOURCE_ALWAYS0 + channel;	

  449. #else

  450. 		// search for an unused "always on" source

  451. 		unsigned int i = DMAMUX_SOURCE_ALWAYS0;

  452. 		for (i = DMAMUX_SOURCE_ALWAYS0;

  453. 		  i < DMAMUX_SOURCE_ALWAYS0 + DMAMUX_NUM_SOURCE_ALWAYS; i++) {

  454. 			unsigned int ch;

  455. 			for (ch=0; ch < DMA_NUM_CHANNELS; ch++) {

  456. 				if (mux[ch] == i) break;

  457. 			}

  458. 			if (ch >= DMA_NUM_CHANNELS) {

  459. 				mux[channel] = (i | DMAMUX_ENABLE);

  460. 				return;

  461. 			}

  462. 		}

  463. #endif

  464. 	}

  465. 

  466. 	// Manually trigger the DMA channel.

  467. 	void triggerManual(void) {

  468. 		DMA_SSRT = channel;

  469. 	}

  470. 

  471. 

  472. 	/***************************************/

  473. 	/**    Interrupts                     **/

  474. 	/***************************************/

  475. 

  476. 	// An interrupt routine can be run when the DMA channel completes

  477. 	// the entire transfer, and also optionally when half of the

  478. 	// transfer is completed.

  479. 	void attachInterrupt(void (*isr)(void)) {

  480. 		_VectorsRam[channel + IRQ_DMA_CH0 + 16] = isr;

  481. 		NVIC_ENABLE_IRQ(IRQ_DMA_CH0 + channel);

  482. 	}

  483. 

  484. 	void detachInterrupt(void) {

  485. 		NVIC_DISABLE_IRQ(IRQ_DMA_CH0 + channel);

  486. 	}

  487. 

  488. 	void clearInterrupt(void) {

  489. 		DMA_CINT = channel;

  490. 	}

  491. 

  492. 

  493. 	/***************************************/

  494. 	/**    Enable / Disable               **/

  495. 	/***************************************/

  496. 

  497. 	void enable(void) {

  498. 		DMA_SERQ = channel;

  499. 	}

  500. 	void disable(void) {

  501. 		DMA_CERQ = channel;

  502. 	}

  503. 

  504. 	/***************************************/

  505. 	/**    Status                         **/

  506. 	/***************************************/

  507. 

  508. 	bool complete(void) {

  509. 		if (TCD->CSR & DMA_TCD_CSR_DONE) return true;

  510. 		return false;

  511. 	}

  512. 	void clearComplete(void) {

  513. 		DMA_CDNE = channel;

  514. 	}

  515. 	bool error(void) {

  516. 		if (DMA_ERR & (1<<channel)) return true;

  517. 		return false;

  518. 	}

  519. 	void clearError(void) {

  520. 		DMA_CERR = channel;

  521. 	}

  522. 	void * sourceAddress(void) {

  523. 		return (void *)(TCD->SADDR);

  524. 	}

  525. 	void * destinationAddress(void) {

  526. 		return (void *)(TCD->DADDR);

  527. 	}

  528. 

  529. 	/***************************************/

  530. 	/**    Direct Hardware Access         **/

  531. 	/***************************************/

  532. 

  533. 	// For complex and unusual configurations not possible with the above

  534. 	// functions, the Transfer Control Descriptor (TCD) and channel number

  535. 	// can be used directly.  This leads to less portable and less readable

  536. 	// code, but direct control of all parameters is possible.

  537. 	uint8_t channel;

  538. 	// TCD is accessible due to inheritance from DMABaseClass

  539. 

  540. /* usage cases:

  541. 

  542. ************************

  543. OctoWS2811:

  544. ************************

  545. 

  546.         // enable clocks to the DMA controller and DMAMUX

  547.         SIM_SCGC7 |= SIM_SCGC7_DMA;

  548.         SIM_SCGC6 |= SIM_SCGC6_DMAMUX;

  549.         DMA_CR = 0;

  550.         DMA_CERQ = 1;

  551.         DMA_CERQ = 2;

  552.         DMA_CERQ = 3;

  553. 

  554.         // DMA channel #1 sets WS2811 high at the beginning of each cycle

  555.          DMA_TCD1_SADDR = &ones;

  556.          DMA_TCD1_SOFF = 0;

  557.          DMA_TCD1_ATTR = DMA_TCD_ATTR_SSIZE(0) | DMA_TCD_ATTR_DSIZE(0);

  558.          DMA_TCD1_NBYTES_MLNO = 1;

  559.          DMA_TCD1_SLAST = 0;

  560.          DMA_TCD1_DADDR = &GPIOD_PSOR;

  561.          DMA_TCD1_DOFF = 0;

  562.          DMA_TCD1_CITER_ELINKNO = bufsize;

  563.          DMA_TCD1_DLASTSGA = 0;

  564.          DMA_TCD1_CSR = DMA_TCD_CSR_DREQ;

  565.          DMA_TCD1_BITER_ELINKNO = bufsize;

  566. 	dma1.source(ones);

  567. 	dma1.destination(GPIOD_PSOR);

  568. 	dma1.size(1);

  569. 	dma1.count(bufsize);

  570. 	dma1.disableOnCompletion();

  571. 

  572.         // DMA channel #2 writes the pixel data at 20% of the cycle

  573.          DMA_TCD2_SADDR = frameBuffer;

  574.          DMA_TCD2_SOFF = 1;

  575.          DMA_TCD2_ATTR = DMA_TCD_ATTR_SSIZE(0) | DMA_TCD_ATTR_DSIZE(0);

  576.          DMA_TCD2_NBYTES_MLNO = 1;

  577.          DMA_TCD2_SLAST = -bufsize;

  578.          DMA_TCD2_DADDR = &GPIOD_PDOR;

  579.          DMA_TCD2_DOFF = 0;

  580.          DMA_TCD2_CITER_ELINKNO = bufsize;

  581.          DMA_TCD2_DLASTSGA = 0;

  582.          DMA_TCD2_CSR = DMA_TCD_CSR_DREQ;

  583.          DMA_TCD2_BITER_ELINKNO = bufsize;

  584. 	dma2.source(frameBuffer, sizeof(frameBuffer));

  585. 	dma2.destination(GPIOD_PDOR);

  586. 	dma2.size(1);

  587. 	dma2.count(bufsize);

  588. 	dma2.disableOnCompletion();

  589. 

  590.         // DMA channel #3 clear all the pins low at 48% of the cycle

  591.         DMA_TCD3_SADDR = &ones;

  592.         DMA_TCD3_SOFF = 0;

  593.         DMA_TCD3_ATTR = DMA_TCD_ATTR_SSIZE(0) | DMA_TCD_ATTR_DSIZE(0);

  594.         DMA_TCD3_NBYTES_MLNO = 1;

  595.         DMA_TCD3_SLAST = 0;

  596.         DMA_TCD3_DADDR = &GPIOD_PCOR;

  597.         DMA_TCD3_DOFF = 0;

  598.         DMA_TCD3_CITER_ELINKNO = bufsize;

  599.         DMA_TCD3_DLASTSGA = 0;

  600.         DMA_TCD3_CSR = DMA_TCD_CSR_DREQ | DMA_TCD_CSR_INTMAJOR;

  601.         DMA_TCD3_BITER_ELINKNO = bufsize;

  602. 	dma3.source(ones);

  603. 	dma3.destination(GPIOD_PCOR);

  604. 	dma3.size(1);

  605. 	dma3.count(bufsize);

  606. 	dma3.disableOnCompletion();

  607. 

  608. ************************

  609. Audio, DAC

  610. ************************

  611. 

  612.         DMA_CR = 0;

  613.         DMA_TCD4_SADDR = dac_buffer;

  614.         DMA_TCD4_SOFF = 2;

  615.         DMA_TCD4_ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);

  616.         DMA_TCD4_NBYTES_MLNO = 2;

  617.         DMA_TCD4_SLAST = -sizeof(dac_buffer);

  618.         DMA_TCD4_DADDR = &DAC0_DAT0L;

  619.         DMA_TCD4_DOFF = 0;

  620.         DMA_TCD4_CITER_ELINKNO = sizeof(dac_buffer) / 2;

  621.         DMA_TCD4_DLASTSGA = 0;

  622.         DMA_TCD4_BITER_ELINKNO = sizeof(dac_buffer) / 2;

  623.         DMA_TCD4_CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;

  624.         DMAMUX0_CHCFG4 = DMAMUX_DISABLE;

  625.         DMAMUX0_CHCFG4 = DMAMUX_SOURCE_PDB | DMAMUX_ENABLE;

  626. 

  627. ************************

  628. Audio, I2S

  629. ************************

  630. 

  631.         DMA_CR = 0;

  632.         DMA_TCD0_SADDR = i2s_tx_buffer;

  633.         DMA_TCD0_SOFF = 2;

  634.         DMA_TCD0_ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);

  635.         DMA_TCD0_NBYTES_MLNO = 2;

  636.         DMA_TCD0_SLAST = -sizeof(i2s_tx_buffer);

  637.         DMA_TCD0_DADDR = &I2S0_TDR0;

  638.         DMA_TCD0_DOFF = 0;

  639.         DMA_TCD0_CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;

  640.         DMA_TCD0_DLASTSGA = 0;

  641.         DMA_TCD0_BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;

  642.         DMA_TCD0_CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;

  643. 

  644.         DMAMUX0_CHCFG0 = DMAMUX_DISABLE;

  645.         DMAMUX0_CHCFG0 = DMAMUX_SOURCE_I2S0_TX | DMAMUX_ENABLE;

  646. 

  647. ************************

  648. ADC lib, Pedro Villanueva

  649. ************************

  650. 

  651.     DMA_CR = 0; // normal mode of operation

  652. 

  653.     *DMAMUX0_CHCFG = DMAMUX_DISABLE; // disable before changing

  654. 

  655.     *DMA_TCD_ATTR = DMA_TCD_ATTR_SSIZE(DMA_TCD_ATTR_SIZE_16BIT) |

  656.                   DMA_TCD_ATTR_DSIZE(DMA_TCD_ATTR_SIZE_16BIT) |

  657.                   DMA_TCD_ATTR_DMOD(4); // src and dst data is 16 bit (2 bytes), buffer size 2^^4 bytes = 8 values

  658.     *DMA_TCD_NBYTES_MLNO = 2; // Minor Byte Transfer Count 2 bytes = 16 bits (we transfer 2 bytes each minor loop)

  659. 

  660.     *DMA_TCD_SADDR = ADC_RA; // source address

  661.     *DMA_TCD_SOFF = 0; // don't change the address when minor loop finishes

  662.     *DMA_TCD_SLAST = 0; // don't change src address after major loop completes

  663. 

  664.     *DMA_TCD_DADDR = elems; // destination address

  665.     *DMA_TCD_DOFF = 2; // increment 2 bytes each minor loop

  666.     *DMA_TCD_DLASTSGA = 0; // modulus feature takes care of going back to first element

  667. 

  668.     *DMA_TCD_CITER_ELINKNO = 1; // Current Major Iteration Count with channel linking disabled

  669.     *DMA_TCD_BITER_ELINKNO = 1; // Starting Major Iteration Count with channel linking disabled

  670. 

  671.     *DMA_TCD_CSR = DMA_TCD_CSR_INTMAJOR; // Control and status: interrupt when major counter is complete

  672. 

  673.     DMA_CERQ = DMA_CERQ_CERQ(DMA_channel); // clear all past request

  674.     DMA_CINT = DMA_channel; // clear interrupts

  675. 

  676.     uint8_t DMAMUX_SOURCE_ADC = DMAMUX_SOURCE_ADC0;

  677.     if(ADC_number==1){

  678.         DMAMUX_SOURCE_ADC = DMAMUX_SOURCE_ADC1;

  679.     }

  680.     *DMAMUX0_CHCFG = DMAMUX_SOURCE_ADC | DMAMUX_ENABLE; // enable mux and set channel DMA_channel to ADC0

  681. 

  682.     DMA_SERQ = DMA_SERQ_SERQ(DMA_channel); // enable DMA request

  683.     NVIC_ENABLE_IRQ(IRQ_DMA_CH); // enable interrupts

  684. 

  685. ************************

  686. SmartMatrix

  687. ************************

  688. 

  689.     // enable minor loop mapping so addresses can get reset after minor loops

  690.     DMA_CR = 1 << 7;

  691. 

  692.     // DMA channel #0 - on latch rising edge, read address from fixed address temporary buffer, and output address on GPIO

  693.     // using combo of writes to set+clear registers, to only modify the address pins and not other GPIO pins

  694.     // address temporary buffer is refreshed before each DMA trigger (by DMA channel #2)

  695.     // only use single major loop, never disable channel

  696. #define ADDRESS_ARRAY_REGISTERS_TO_UPDATE   2

  697.     DMA_TCD0_SADDR = &gpiosync.gpio_pcor;

  698.     DMA_TCD0_SOFF = (int)&gpiosync.gpio_psor - (int)&gpiosync.gpio_pcor;

  699.     DMA_TCD0_SLAST = (ADDRESS_ARRAY_REGISTERS_TO_UPDATE * ((int)&ADDX_GPIO_CLEAR_REGISTER - (int)&ADDX_GPIO_SET_REGISTER));

  700.     DMA_TCD0_ATTR = DMA_TCD_ATTR_SSIZE(2) | DMA_TCD_ATTR_DSIZE(2);

  701.     // Destination Minor Loop Offset Enabled - transfer appropriate number of bytes per minor loop, and put DADDR back to original value when minor loop is complete

  702.     // Source Minor Loop Offset Enabled - source buffer is same size and offset as destination so values reset after each minor loop

  703.     DMA_TCD0_NBYTES_MLOFFYES = DMA_TCD_NBYTES_SMLOE | DMA_TCD_NBYTES_DMLOE |

  704.                                ((ADDRESS_ARRAY_REGISTERS_TO_UPDATE * ((int)&ADDX_GPIO_CLEAR_REGISTER - (int)&ADDX_GPIO_SET_REGISTER)) << 10) |

  705.                                (ADDRESS_ARRAY_REGISTERS_TO_UPDATE * sizeof(gpiosync.gpio_psor));

  706.     // start on higher value of two registers, and make offset decrement to avoid negative number in NBYTES_MLOFFYES (TODO: can switch order by masking negative offset)

  707.     DMA_TCD0_DADDR = &ADDX_GPIO_CLEAR_REGISTER;

  708.     // update destination address so the second update per minor loop is ADDX_GPIO_SET_REGISTER

  709.     DMA_TCD0_DOFF = (int)&ADDX_GPIO_SET_REGISTER - (int)&ADDX_GPIO_CLEAR_REGISTER;

  710.     DMA_TCD0_DLASTSGA = (ADDRESS_ARRAY_REGISTERS_TO_UPDATE * ((int)&ADDX_GPIO_CLEAR_REGISTER - (int)&ADDX_GPIO_SET_REGISTER));

  711.     // single major loop

  712.     DMA_TCD0_CITER_ELINKNO = 1;

  713.     DMA_TCD0_BITER_ELINKNO = 1;

  714.     // link channel 1, enable major channel-to-channel linking, don't clear enable on major loop complete

  715.     DMA_TCD0_CSR = (1 << 8) | (1 << 5);

  716.     DMAMUX0_CHCFG0 = DMAMUX_SOURCE_LATCH_RISING_EDGE | DMAMUX_ENABLE;

  717. 

  718.     // DMA channel #1 - copy address values from current position in array to buffer to temporarily hold row values for the next timer cycle

  719.     // only use single major loop, never disable channel

  720.     DMA_TCD1_SADDR = &matrixUpdateBlocks[0][0].addressValues;

  721.     DMA_TCD1_SOFF = sizeof(uint16_t);

  722.     DMA_TCD1_SLAST = sizeof(matrixUpdateBlock) - (ADDRESS_ARRAY_REGISTERS_TO_UPDATE * sizeof(uint16_t));

  723.     DMA_TCD1_ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);

  724.     // 16-bit = 2 bytes transferred

  725.     // transfer two 16-bit values, reset destination address back after each minor loop

  726.     DMA_TCD1_NBYTES_MLOFFNO = (ADDRESS_ARRAY_REGISTERS_TO_UPDATE * sizeof(uint16_t));

  727.     // start with the register that's the highest location in memory and make offset decrement to avoid negative number in NBYTES_MLOFFYES register (TODO: can switch order by masking negative offset)

  728.     DMA_TCD1_DADDR = &gpiosync.gpio_pcor;

  729.     DMA_TCD1_DOFF = (int)&gpiosync.gpio_psor - (int)&gpiosync.gpio_pcor;

  730.     DMA_TCD1_DLASTSGA = (ADDRESS_ARRAY_REGISTERS_TO_UPDATE * ((int)&gpiosync.gpio_pcor - (int)&gpiosync.gpio_psor));

  731.     // no minor loop linking, single major loop, single minor loop, don't clear enable after major loop complete

  732.     DMA_TCD1_CITER_ELINKNO = 1;

  733.     DMA_TCD1_BITER_ELINKNO = 1;

  734.     DMA_TCD1_CSR = 0;

  735. 

  736.     // DMA channel #2 - on latch falling edge, load FTM1_CV1 and FTM1_MOD with with next values from current block

  737.     // only use single major loop, never disable channel

  738.     // link to channel 3 when complete

  739. #define TIMER_REGISTERS_TO_UPDATE   2

  740.     DMA_TCD2_SADDR = &matrixUpdateBlocks[0][0].timerValues.timer_oe;

  741.     DMA_TCD2_SOFF = sizeof(uint16_t);

  742.     DMA_TCD2_SLAST = sizeof(matrixUpdateBlock) - (TIMER_REGISTERS_TO_UPDATE * sizeof(uint16_t));

  743.     DMA_TCD2_ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);

  744.     // 16-bit = 2 bytes transferred

  745.     DMA_TCD2_NBYTES_MLOFFNO = TIMER_REGISTERS_TO_UPDATE * sizeof(uint16_t);

  746.     DMA_TCD2_DADDR = &FTM1_C1V;

  747.     DMA_TCD2_DOFF = (int)&FTM1_MOD - (int)&FTM1_C1V;

  748.     DMA_TCD2_DLASTSGA = TIMER_REGISTERS_TO_UPDATE * ((int)&FTM1_C1V - (int)&FTM1_MOD);

  749.     // no minor loop linking, single major loop

  750.     DMA_TCD2_CITER_ELINKNO = 1;

  751.     DMA_TCD2_BITER_ELINKNO = 1;

  752.     // link channel 3, enable major channel-to-channel linking, don't clear enable after major loop complete

  753.     DMA_TCD2_CSR = (3 << 8) | (1 << 5);

  754.     DMAMUX0_CHCFG2 = DMAMUX_SOURCE_LATCH_FALLING_EDGE | DMAMUX_ENABLE;

  755. 

  756. #define DMA_TCD_MLOFF_MASK  (0x3FFFFC00)

  757. 

  758.     // DMA channel #3 - repeatedly load gpio_array into GPIOD_PDOR, stop and int on major loop complete

  759.     DMA_TCD3_SADDR = matrixUpdateData[0][0];

  760.     DMA_TCD3_SOFF = sizeof(matrixUpdateData[0][0]) / 2;

  761.     // SADDR will get updated by ISR, no need to set SLAST

  762.     DMA_TCD3_SLAST = 0;

  763.     DMA_TCD3_ATTR = DMA_TCD_ATTR_SSIZE(0) | DMA_TCD_ATTR_DSIZE(0);

  764.     // after each minor loop, set source to point back to the beginning of this set of data,

  765.     // but advance by 1 byte to get the next significant bits data

  766.     DMA_TCD3_NBYTES_MLOFFYES = DMA_TCD_NBYTES_SMLOE |

  767.                                (((1 - sizeof(matrixUpdateData[0])) << 10) & DMA_TCD_MLOFF_MASK) |

  768.                                (MATRIX_WIDTH * DMA_UPDATES_PER_CLOCK);

  769.     DMA_TCD3_DADDR = &GPIOD_PDOR;

  770.     DMA_TCD3_DOFF = 0;

  771.     DMA_TCD3_DLASTSGA = 0;

  772.     DMA_TCD3_CITER_ELINKNO = LATCHES_PER_ROW;

  773.     DMA_TCD3_BITER_ELINKNO = LATCHES_PER_ROW;

  774.     // int after major loop is complete

  775.     DMA_TCD3_CSR = DMA_TCD_CSR_INTMAJOR;

  776.     // for debugging - enable bandwidth control (space out GPIO updates so they can be seen easier on a low-bandwidth logic analyzer)

  777.     //DMA_TCD3_CSR |= (0x02 << 14);

  778. 

  779.     // enable a done interrupt when all DMA operations are complete

  780.     NVIC_ENABLE_IRQ(IRQ_DMA_CH3);

  781. 

  782.     // enable additional dma interrupt used as software interrupt

  783.     NVIC_SET_PRIORITY(IRQ_DMA_CH1, 0xFF); // 0xFF = lowest priority

  784.     NVIC_ENABLE_IRQ(IRQ_DMA_CH1);

  785. 

  786.     // enable channels 0, 1, 2, 3

  787.     DMA_ERQ = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3);

  788. 

  789.     // at the end after everything is set up: enable timer from system clock, with appropriate prescale

  790.     FTM1_SC = FTM_SC_CLKS(1) | FTM_SC_PS(LATCH_TIMER_PRESCALE);

  791. 

  792. 

  793. */

  794. 

  795. 

  796. };

  797. 

  798. // arrange the relative priority of 2 or more DMA channels

  799. void DMAPriorityOrder(DMAChannel &ch1, DMAChannel &ch2);

  800. void DMAPriorityOrder(DMAChannel &ch1, DMAChannel &ch2, DMAChannel &ch3);

  801. void DMAPriorityOrder(DMAChannel &ch1, DMAChannel &ch2, DMAChannel &ch3, DMAChannel &ch4);

  802. 

  803. 

  804. 

  805. extern "C" {

  806. #endif

  807. extern uint16_t dma_channel_allocated_mask;

  808. #ifdef __cplusplus

  809. }

  810. #endif

  811. 

  812. 

  813. 

  814. #endif