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serial4.c 11KB

7 vuotta sitten
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  1. /* Teensyduino Core Library
  2. * http://www.pjrc.com/teensy/
  3. * Copyright (c) 2017 PJRC.COM, LLC.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining
  6. * a copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sublicense, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * 1. The above copyright notice and this permission notice shall be
  14. * included in all copies or substantial portions of the Software.
  15. *
  16. * 2. If the Software is incorporated into a build system that allows
  17. * selection among a list of target devices, then similar target
  18. * devices manufactured by PJRC.COM must be included in the list of
  19. * target devices and selectable in the same manner.
  20. *
  21. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  24. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  25. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  26. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  27. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  28. * SOFTWARE.
  29. */
  30. #include "kinetis.h"
  31. #include "core_pins.h"
  32. #include "HardwareSerial.h"
  33. #ifdef HAS_KINETISK_UART3
  34. ////////////////////////////////////////////////////////////////
  35. // Tunable parameters (relatively safe to edit these numbers)
  36. ////////////////////////////////////////////////////////////////
  37. #ifndef SERIAL4_TX_BUFFER_SIZE
  38. #define SERIAL4_TX_BUFFER_SIZE 40 // number of outgoing bytes to buffer
  39. #endif
  40. #ifndef SERIAL4_RX_BUFFER_SIZE
  41. #define SERIAL4_RX_BUFFER_SIZE 64 // number of incoming bytes to buffer
  42. #endif
  43. #define RTS_HIGH_WATERMARK (SERIAL4_RX_BUFFER_SIZE-24) // RTS requests sender to pause
  44. #define RTS_LOW_WATERMARK (SERIAL4_RX_BUFFER_SIZE-38) // RTS allows sender to resume
  45. #define IRQ_PRIORITY 64 // 0 = highest priority, 255 = lowest
  46. ////////////////////////////////////////////////////////////////
  47. // changes not recommended below this point....
  48. ////////////////////////////////////////////////////////////////
  49. #ifdef SERIAL_9BIT_SUPPORT
  50. static uint8_t use9Bits = 0;
  51. #define BUFTYPE uint16_t
  52. #else
  53. #define BUFTYPE uint8_t
  54. #define use9Bits 0
  55. #endif
  56. static volatile BUFTYPE tx_buffer[SERIAL4_TX_BUFFER_SIZE];
  57. static volatile BUFTYPE rx_buffer[SERIAL4_RX_BUFFER_SIZE];
  58. static volatile uint8_t transmitting = 0;
  59. static volatile uint8_t *transmit_pin=NULL;
  60. #define transmit_assert() *transmit_pin = 1
  61. #define transmit_deassert() *transmit_pin = 0
  62. static volatile uint8_t *rts_pin=NULL;
  63. #define rts_assert() *rts_pin = 0
  64. #define rts_deassert() *rts_pin = 1
  65. #if SERIAL4_TX_BUFFER_SIZE > 255
  66. static volatile uint16_t tx_buffer_head = 0;
  67. static volatile uint16_t tx_buffer_tail = 0;
  68. #else
  69. static volatile uint8_t tx_buffer_head = 0;
  70. static volatile uint8_t tx_buffer_tail = 0;
  71. #endif
  72. #if SERIAL4_RX_BUFFER_SIZE > 255
  73. static volatile uint16_t rx_buffer_head = 0;
  74. static volatile uint16_t rx_buffer_tail = 0;
  75. #else
  76. static volatile uint8_t rx_buffer_head = 0;
  77. static volatile uint8_t rx_buffer_tail = 0;
  78. #endif
  79. static uint8_t rx_pin_num = 31;
  80. static uint8_t tx_pin_num = 32;
  81. // UART0 and UART1 are clocked by F_CPU, UART2 is clocked by F_BUS
  82. // UART0 has 8 byte fifo, UART1 and UART2 have 1 byte buffer
  83. #define C2_ENABLE UART_C2_TE | UART_C2_RE | UART_C2_RIE
  84. #define C2_TX_ACTIVE C2_ENABLE | UART_C2_TIE
  85. #define C2_TX_COMPLETING C2_ENABLE | UART_C2_TCIE
  86. #define C2_TX_INACTIVE C2_ENABLE
  87. void serial4_begin(uint32_t divisor)
  88. {
  89. SIM_SCGC4 |= SIM_SCGC4_UART3; // turn on clock, TODO: use bitband
  90. rx_buffer_head = 0;
  91. rx_buffer_tail = 0;
  92. tx_buffer_head = 0;
  93. tx_buffer_tail = 0;
  94. transmitting = 0;
  95. switch (rx_pin_num) {
  96. case 31: CORE_PIN31_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
  97. case 63: CORE_PIN63_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
  98. }
  99. switch (tx_pin_num) {
  100. case 32: CORE_PIN32_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
  101. case 62: CORE_PIN62_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
  102. }
  103. if (divisor < 32) divisor = 32;
  104. UART3_BDH = (divisor >> 13) & 0x1F;
  105. UART3_BDL = (divisor >> 5) & 0xFF;
  106. UART3_C4 = divisor & 0x1F;
  107. UART3_C1 = 0;
  108. UART3_PFIFO = 0;
  109. UART3_C2 = C2_TX_INACTIVE;
  110. NVIC_SET_PRIORITY(IRQ_UART3_STATUS, IRQ_PRIORITY);
  111. NVIC_ENABLE_IRQ(IRQ_UART3_STATUS);
  112. }
  113. void serial4_format(uint32_t format)
  114. {
  115. uint8_t c;
  116. c = UART3_C1;
  117. c = (c & ~0x13) | (format & 0x03); // configure parity
  118. if (format & 0x04) c |= 0x10; // 9 bits (might include parity)
  119. UART3_C1 = c;
  120. if ((format & 0x0F) == 0x04) UART3_C3 |= 0x40; // 8N2 is 9 bit with 9th bit always 1
  121. c = UART3_S2 & ~0x10;
  122. if (format & 0x10) c |= 0x10; // rx invert
  123. UART3_S2 = c;
  124. c = UART3_C3 & ~0x10;
  125. if (format & 0x20) c |= 0x10; // tx invert
  126. UART3_C3 = c;
  127. #ifdef SERIAL_9BIT_SUPPORT
  128. c = UART3_C4 & 0x1F;
  129. if (format & 0x08) c |= 0x20; // 9 bit mode with parity (requires 10 bits)
  130. UART3_C4 = c;
  131. use9Bits = format & 0x80;
  132. #endif
  133. #if defined(__MK64FX512__) || defined(__MK66FX1M0__) || defined(KINETISL)
  134. // For T3.5/T3.6/TLC See about turning on 2 stop bit mode
  135. if ( format & 0x100) {
  136. uint8_t bdl = UART3_BDL;
  137. UART3_BDH |= UART_BDH_SBNS; // Turn on 2 stop bits - was turned off by set baud
  138. UART3_BDL = bdl; // Says BDH not acted on until BDL is written
  139. }
  140. #endif
  141. }
  142. void serial4_end(void)
  143. {
  144. if (!(SIM_SCGC4 & SIM_SCGC4_UART3)) return;
  145. while (transmitting) yield(); // wait for buffered data to send
  146. NVIC_DISABLE_IRQ(IRQ_UART3_STATUS);
  147. UART3_C2 = 0;
  148. switch (rx_pin_num) {
  149. case 31: CORE_PIN31_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); break; // PTC3
  150. case 63: CORE_PIN63_CONFIG = 0; break;
  151. }
  152. switch (tx_pin_num & 127) {
  153. case 32: CORE_PIN32_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); break; // PTC4
  154. case 62: CORE_PIN62_CONFIG = 0; break;
  155. }
  156. rx_buffer_head = 0;
  157. rx_buffer_tail = 0;
  158. if (rts_pin) rts_deassert();
  159. }
  160. void serial4_set_transmit_pin(uint8_t pin)
  161. {
  162. while (transmitting) ;
  163. pinMode(pin, OUTPUT);
  164. digitalWrite(pin, LOW);
  165. transmit_pin = portOutputRegister(pin);
  166. }
  167. void serial4_set_tx(uint8_t pin, uint8_t opendrain)
  168. {
  169. uint32_t cfg;
  170. if (opendrain) pin |= 128;
  171. if (pin == tx_pin_num) return;
  172. if ((SIM_SCGC4 & SIM_SCGC4_UART3)) {
  173. switch (tx_pin_num & 127) {
  174. case 32: CORE_PIN32_CONFIG = 0; break; // PTB11
  175. case 62: CORE_PIN62_CONFIG = 0; break;
  176. }
  177. if (opendrain) {
  178. cfg = PORT_PCR_DSE | PORT_PCR_ODE;
  179. } else {
  180. cfg = PORT_PCR_DSE | PORT_PCR_SRE;
  181. }
  182. switch (pin & 127) {
  183. case 32: CORE_PIN32_CONFIG = cfg | PORT_PCR_MUX(3); break;
  184. case 62: CORE_PIN62_CONFIG = cfg | PORT_PCR_MUX(3); break;
  185. }
  186. }
  187. tx_pin_num = pin;
  188. }
  189. void serial4_set_rx(uint8_t pin)
  190. {
  191. if (pin == rx_pin_num) return;
  192. if ((SIM_SCGC4 & SIM_SCGC4_UART3)) {
  193. switch (rx_pin_num) {
  194. case 31: CORE_PIN31_CONFIG = 0; break; // PTC3
  195. case 63: CORE_PIN63_CONFIG = 0; break;
  196. }
  197. switch (pin) {
  198. case 31: CORE_PIN31_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
  199. case 63: CORE_PIN63_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
  200. }
  201. }
  202. rx_pin_num = pin;
  203. }
  204. int serial4_set_rts(uint8_t pin)
  205. {
  206. if (!(SIM_SCGC4 & SIM_SCGC4_UART3)) return 0;
  207. if (pin < CORE_NUM_DIGITAL) {
  208. rts_pin = portOutputRegister(pin);
  209. pinMode(pin, OUTPUT);
  210. rts_assert();
  211. } else {
  212. rts_pin = NULL;
  213. return 0;
  214. }
  215. return 1;
  216. }
  217. int serial4_set_cts(uint8_t pin)
  218. {
  219. return 0;
  220. }
  221. void serial4_putchar(uint32_t c)
  222. {
  223. uint32_t head, n;
  224. if (!(SIM_SCGC4 & SIM_SCGC4_UART3)) return;
  225. if (transmit_pin) transmit_assert();
  226. head = tx_buffer_head;
  227. if (++head >= SERIAL4_TX_BUFFER_SIZE) head = 0;
  228. while (tx_buffer_tail == head) {
  229. int priority = nvic_execution_priority();
  230. if (priority <= IRQ_PRIORITY) {
  231. if ((UART3_S1 & UART_S1_TDRE)) {
  232. uint32_t tail = tx_buffer_tail;
  233. if (++tail >= SERIAL4_TX_BUFFER_SIZE) tail = 0;
  234. n = tx_buffer[tail];
  235. if (use9Bits) UART3_C3 = (UART3_C3 & ~0x40) | ((n & 0x100) >> 2);
  236. UART3_D = n;
  237. tx_buffer_tail = tail;
  238. }
  239. } else if (priority >= 256) {
  240. yield(); // wait
  241. }
  242. }
  243. tx_buffer[head] = c;
  244. transmitting = 1;
  245. tx_buffer_head = head;
  246. UART3_C2 = C2_TX_ACTIVE;
  247. }
  248. void serial4_write(const void *buf, unsigned int count)
  249. {
  250. const uint8_t *p = (const uint8_t *)buf;
  251. while (count-- > 0) serial4_putchar(*p++);
  252. }
  253. void serial4_flush(void)
  254. {
  255. while (transmitting) yield(); // wait
  256. }
  257. int serial4_write_buffer_free(void)
  258. {
  259. uint32_t head, tail;
  260. head = tx_buffer_head;
  261. tail = tx_buffer_tail;
  262. if (head >= tail) return SERIAL4_TX_BUFFER_SIZE - 1 - head + tail;
  263. return tail - head - 1;
  264. }
  265. int serial4_available(void)
  266. {
  267. uint32_t head, tail;
  268. head = rx_buffer_head;
  269. tail = rx_buffer_tail;
  270. if (head >= tail) return head - tail;
  271. return SERIAL4_RX_BUFFER_SIZE + head - tail;
  272. }
  273. int serial4_getchar(void)
  274. {
  275. uint32_t head, tail;
  276. int c;
  277. head = rx_buffer_head;
  278. tail = rx_buffer_tail;
  279. if (head == tail) return -1;
  280. if (++tail >= SERIAL4_RX_BUFFER_SIZE) tail = 0;
  281. c = rx_buffer[tail];
  282. rx_buffer_tail = tail;
  283. if (rts_pin) {
  284. int avail;
  285. if (head >= tail) avail = head - tail;
  286. else avail = SERIAL4_RX_BUFFER_SIZE + head - tail;
  287. if (avail <= RTS_LOW_WATERMARK) rts_assert();
  288. }
  289. return c;
  290. }
  291. int serial4_peek(void)
  292. {
  293. uint32_t head, tail;
  294. head = rx_buffer_head;
  295. tail = rx_buffer_tail;
  296. if (head == tail) return -1;
  297. if (++tail >= SERIAL4_RX_BUFFER_SIZE) tail = 0;
  298. return rx_buffer[tail];
  299. }
  300. void serial4_clear(void)
  301. {
  302. rx_buffer_head = rx_buffer_tail;
  303. if (rts_pin) rts_assert();
  304. }
  305. // status interrupt combines
  306. // Transmit data below watermark UART_S1_TDRE
  307. // Transmit complete UART_S1_TC
  308. // Idle line UART_S1_IDLE
  309. // Receive data above watermark UART_S1_RDRF
  310. // LIN break detect UART_S2_LBKDIF
  311. // RxD pin active edge UART_S2_RXEDGIF
  312. void uart3_status_isr(void)
  313. {
  314. uint32_t head, tail, n;
  315. uint8_t c;
  316. if (UART3_S1 & UART_S1_RDRF) {
  317. if (use9Bits && (UART3_C3 & 0x80)) {
  318. n = UART3_D | 0x100;
  319. } else {
  320. n = UART3_D;
  321. }
  322. head = rx_buffer_head + 1;
  323. if (head >= SERIAL4_RX_BUFFER_SIZE) head = 0;
  324. if (head != rx_buffer_tail) {
  325. rx_buffer[head] = n;
  326. rx_buffer_head = head;
  327. }
  328. if (rts_pin) {
  329. int avail;
  330. tail = tx_buffer_tail;
  331. if (head >= tail) avail = head - tail;
  332. else avail = SERIAL4_RX_BUFFER_SIZE + head - tail;
  333. if (avail >= RTS_HIGH_WATERMARK) rts_deassert();
  334. }
  335. }
  336. c = UART3_C2;
  337. if ((c & UART_C2_TIE) && (UART3_S1 & UART_S1_TDRE)) {
  338. head = tx_buffer_head;
  339. tail = tx_buffer_tail;
  340. if (head == tail) {
  341. UART3_C2 = C2_TX_COMPLETING;
  342. } else {
  343. if (++tail >= SERIAL4_TX_BUFFER_SIZE) tail = 0;
  344. n = tx_buffer[tail];
  345. if (use9Bits) UART3_C3 = (UART3_C3 & ~0x40) | ((n & 0x100) >> 2);
  346. UART3_D = n;
  347. tx_buffer_tail = tail;
  348. }
  349. }
  350. if ((c & UART_C2_TCIE) && (UART3_S1 & UART_S1_TC)) {
  351. transmitting = 0;
  352. if (transmit_pin) transmit_deassert();
  353. UART3_C2 = C2_TX_INACTIVE;
  354. }
  355. }
  356. #endif // HAS_KINETISK_UART3