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serial1.c 17KB

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  1. /* Teensyduino Core Library
  2. * http://www.pjrc.com/teensy/
  3. * Copyright (c) 2013 PJRC.COM, LLC.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining
  6. * a copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sublicense, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * 1. The above copyright notice and this permission notice shall be
  14. * included in all copies or substantial portions of the Software.
  15. *
  16. * 2. If the Software is incorporated into a build system that allows
  17. * selection among a list of target devices, then similar target
  18. * devices manufactured by PJRC.COM must be included in the list of
  19. * target devices and selectable in the same manner.
  20. *
  21. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  24. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  25. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  26. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  27. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  28. * SOFTWARE.
  29. */
  30. #include "kinetis.h"
  31. #include "core_pins.h"
  32. #include "HardwareSerial.h"
  33. ////////////////////////////////////////////////////////////////
  34. // Tunable parameters (relatively safe to edit these numbers)
  35. ////////////////////////////////////////////////////////////////
  36. #define TX_BUFFER_SIZE 64 // number of outgoing bytes to buffer
  37. #define RX_BUFFER_SIZE 64 // number of incoming bytes to buffer
  38. #define RTS_HIGH_WATERMARK 40 // RTS requests sender to pause
  39. #define RTS_LOW_WATERMARK 26 // RTS allows sender to resume
  40. #define IRQ_PRIORITY 64 // 0 = highest priority, 255 = lowest
  41. ////////////////////////////////////////////////////////////////
  42. // changes not recommended below this point....
  43. ////////////////////////////////////////////////////////////////
  44. #ifdef SERIAL_9BIT_SUPPORT
  45. static uint8_t use9Bits = 0;
  46. #define BUFTYPE uint16_t
  47. #else
  48. #define BUFTYPE uint8_t
  49. #define use9Bits 0
  50. #endif
  51. static volatile BUFTYPE tx_buffer[TX_BUFFER_SIZE];
  52. static volatile BUFTYPE rx_buffer[RX_BUFFER_SIZE];
  53. static volatile uint8_t transmitting = 0;
  54. #if defined(KINETISK)
  55. static volatile uint8_t *transmit_pin=NULL;
  56. #define transmit_assert() *transmit_pin = 1
  57. #define transmit_deassert() *transmit_pin = 0
  58. static volatile uint8_t *rts_pin=NULL;
  59. #define rts_assert() *rts_pin = 0
  60. #define rts_deassert() *rts_pin = 1
  61. #elif defined(KINETISL)
  62. static volatile uint8_t *transmit_pin=NULL;
  63. static uint8_t transmit_mask=0;
  64. #define transmit_assert() *(transmit_pin+4) = transmit_mask;
  65. #define transmit_deassert() *(transmit_pin+8) = transmit_mask;
  66. static volatile uint8_t *rts_pin=NULL;
  67. static uint8_t rts_mask=0;
  68. #define rts_assert() *(rts_pin+8) = rts_mask;
  69. #define rts_deassert() *(rts_pin+4) = rts_mask;
  70. #endif
  71. #if TX_BUFFER_SIZE > 255
  72. static volatile uint16_t tx_buffer_head = 0;
  73. static volatile uint16_t tx_buffer_tail = 0;
  74. #else
  75. static volatile uint8_t tx_buffer_head = 0;
  76. static volatile uint8_t tx_buffer_tail = 0;
  77. #endif
  78. #if RX_BUFFER_SIZE > 255
  79. static volatile uint16_t rx_buffer_head = 0;
  80. static volatile uint16_t rx_buffer_tail = 0;
  81. #else
  82. static volatile uint8_t rx_buffer_head = 0;
  83. static volatile uint8_t rx_buffer_tail = 0;
  84. #endif
  85. static uint8_t rx_pin_num = 0;
  86. static uint8_t tx_pin_num = 1;
  87. // UART0 and UART1 are clocked by F_CPU, UART2 is clocked by F_BUS
  88. // UART0 has 8 byte fifo, UART1 and UART2 have 1 byte buffer
  89. #ifdef HAS_KINETISK_UART0_FIFO
  90. #define C2_ENABLE UART_C2_TE | UART_C2_RE | UART_C2_RIE | UART_C2_ILIE
  91. #else
  92. #define C2_ENABLE UART_C2_TE | UART_C2_RE | UART_C2_RIE
  93. #endif
  94. #define C2_TX_ACTIVE C2_ENABLE | UART_C2_TIE
  95. #define C2_TX_COMPLETING C2_ENABLE | UART_C2_TCIE
  96. #define C2_TX_INACTIVE C2_ENABLE
  97. void serial_begin(uint32_t divisor)
  98. {
  99. SIM_SCGC4 |= SIM_SCGC4_UART0; // turn on clock, TODO: use bitband
  100. rx_buffer_head = 0;
  101. rx_buffer_tail = 0;
  102. tx_buffer_head = 0;
  103. tx_buffer_tail = 0;
  104. transmitting = 0;
  105. switch (rx_pin_num) {
  106. case 0: CORE_PIN0_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
  107. case 21: CORE_PIN21_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
  108. #if defined(KINETISL)
  109. case 3: CORE_PIN3_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(2); break;
  110. #endif
  111. #if defined(__MK64FX512__) || defined(__MK66FX1M0__)
  112. case 27: CORE_PIN27_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
  113. #endif
  114. }
  115. switch (tx_pin_num) {
  116. case 1: CORE_PIN1_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
  117. case 5: CORE_PIN5_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
  118. #if defined(KINETISL)
  119. case 4: CORE_PIN4_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(2); break;
  120. #endif
  121. #if defined(__MK64FX512__) || defined(__MK66FX1M0__)
  122. case 26: CORE_PIN26_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
  123. #endif
  124. }
  125. #if defined(HAS_KINETISK_UART0)
  126. UART0_BDH = (divisor >> 13) & 0x1F;
  127. UART0_BDL = (divisor >> 5) & 0xFF;
  128. UART0_C4 = divisor & 0x1F;
  129. #ifdef HAS_KINETISK_UART0_FIFO
  130. UART0_C1 = UART_C1_ILT;
  131. UART0_TWFIFO = 2; // tx watermark, causes S1_TDRE to set
  132. UART0_RWFIFO = 4; // rx watermark, causes S1_RDRF to set
  133. UART0_PFIFO = UART_PFIFO_TXFE | UART_PFIFO_RXFE;
  134. #else
  135. UART0_C1 = 0;
  136. UART0_PFIFO = 0;
  137. #endif
  138. #elif defined(HAS_KINETISL_UART0)
  139. UART0_BDH = (divisor >> 8) & 0x1F;
  140. UART0_BDL = divisor & 0xFF;
  141. UART0_C1 = 0;
  142. #endif
  143. UART0_C2 = C2_TX_INACTIVE;
  144. NVIC_SET_PRIORITY(IRQ_UART0_STATUS, IRQ_PRIORITY);
  145. NVIC_ENABLE_IRQ(IRQ_UART0_STATUS);
  146. }
  147. void serial_format(uint32_t format)
  148. {
  149. uint8_t c;
  150. c = UART0_C1;
  151. c = (c & ~0x13) | (format & 0x03); // configure parity
  152. if (format & 0x04) c |= 0x10; // 9 bits (might include parity)
  153. UART0_C1 = c;
  154. if ((format & 0x0F) == 0x04) UART0_C3 |= 0x40; // 8N2 is 9 bit with 9th bit always 1
  155. c = UART0_S2 & ~0x10;
  156. if (format & 0x10) c |= 0x10; // rx invert
  157. UART0_S2 = c;
  158. c = UART0_C3 & ~0x10;
  159. if (format & 0x20) c |= 0x10; // tx invert
  160. UART0_C3 = c;
  161. #ifdef SERIAL_9BIT_SUPPORT
  162. c = UART0_C4 & 0x1F;
  163. if (format & 0x08) c |= 0x20; // 9 bit mode with parity (requires 10 bits)
  164. UART0_C4 = c;
  165. use9Bits = format & 0x80;
  166. #endif
  167. #if defined(__MK64FX512__) || defined(__MK66FX1M0__) || defined(KINETISL)
  168. // For T3.5/T3.6/TLC See about turning on 2 stop bit mode
  169. if ( format & 0x100) {
  170. uint8_t bdl = UART0_BDL;
  171. UART0_BDH |= UART_BDH_SBNS; // Turn on 2 stop bits - was turned off by set baud
  172. UART0_BDL = bdl; // Says BDH not acted on until BDL is written
  173. }
  174. #endif
  175. }
  176. void serial_end(void)
  177. {
  178. if (!(SIM_SCGC4 & SIM_SCGC4_UART0)) return;
  179. while (transmitting) yield(); // wait for buffered data to send
  180. NVIC_DISABLE_IRQ(IRQ_UART0_STATUS);
  181. UART0_C2 = 0;
  182. CORE_PIN0_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1);
  183. CORE_PIN1_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1);
  184. rx_buffer_head = 0;
  185. rx_buffer_tail = 0;
  186. if (rts_pin) rts_deassert();
  187. }
  188. void serial_set_transmit_pin(uint8_t pin)
  189. {
  190. while (transmitting) ;
  191. pinMode(pin, OUTPUT);
  192. digitalWrite(pin, LOW);
  193. transmit_pin = portOutputRegister(pin);
  194. #if defined(KINETISL)
  195. transmit_mask = digitalPinToBitMask(pin);
  196. #endif
  197. }
  198. void serial_set_tx(uint8_t pin, uint8_t opendrain)
  199. {
  200. uint32_t cfg;
  201. if (opendrain) pin |= 128;
  202. if (pin == tx_pin_num) return;
  203. if ((SIM_SCGC4 & SIM_SCGC4_UART0)) {
  204. switch (tx_pin_num & 127) {
  205. case 1: CORE_PIN1_CONFIG = 0; break; // PTB17
  206. case 5: CORE_PIN5_CONFIG = 0; break; // PTD7
  207. #if defined(KINETISL)
  208. case 4: CORE_PIN4_CONFIG = 0; break; // PTA2
  209. case 24: CORE_PIN24_CONFIG = 0; break; // PTE20
  210. #endif
  211. #if defined(__MK64FX512__) || defined(__MK66FX1M0__)
  212. case 26: CORE_PIN26_CONFIG = 0; break; //PTA14
  213. #endif
  214. }
  215. if (opendrain) {
  216. cfg = PORT_PCR_DSE | PORT_PCR_ODE;
  217. } else {
  218. cfg = PORT_PCR_DSE | PORT_PCR_SRE;
  219. }
  220. switch (pin & 127) {
  221. case 1: CORE_PIN1_CONFIG = cfg | PORT_PCR_MUX(3); break;
  222. case 5: CORE_PIN5_CONFIG = cfg | PORT_PCR_MUX(3); break;
  223. #if defined(KINETISL)
  224. case 4: CORE_PIN4_CONFIG = cfg | PORT_PCR_MUX(2); break;
  225. case 24: CORE_PIN24_CONFIG = cfg | PORT_PCR_MUX(4); break;
  226. #endif
  227. #if defined(__MK64FX512__) || defined(__MK66FX1M0__)
  228. case 26: CORE_PIN26_CONFIG = cfg | PORT_PCR_MUX(3); break;
  229. #endif
  230. }
  231. }
  232. tx_pin_num = pin;
  233. }
  234. void serial_set_rx(uint8_t pin)
  235. {
  236. if (pin == rx_pin_num) return;
  237. if ((SIM_SCGC4 & SIM_SCGC4_UART0)) {
  238. switch (rx_pin_num) {
  239. case 0: CORE_PIN0_CONFIG = 0; break; // PTB16
  240. case 21: CORE_PIN21_CONFIG = 0; break; // PTD6
  241. #if defined(KINETISL)
  242. case 3: CORE_PIN3_CONFIG = 0; break; // PTA1
  243. case 25: CORE_PIN25_CONFIG = 0; break; // PTE21
  244. #endif
  245. #if defined(__MK64FX512__) || defined(__MK66FX1M0__)
  246. case 27: CORE_PIN27_CONFIG = 0; break; // PTA15
  247. #endif
  248. }
  249. switch (pin) {
  250. case 0: CORE_PIN0_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
  251. case 21: CORE_PIN21_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
  252. #if defined(KINETISL)
  253. case 3: CORE_PIN3_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(2); break;
  254. case 25: CORE_PIN25_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(4); break;
  255. #endif
  256. #if defined(__MK64FX512__) || defined(__MK66FX1M0__)
  257. case 27: CORE_PIN27_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
  258. #endif
  259. }
  260. }
  261. rx_pin_num = pin;
  262. }
  263. int serial_set_rts(uint8_t pin)
  264. {
  265. if (!(SIM_SCGC4 & SIM_SCGC4_UART0)) return 0;
  266. if (pin < CORE_NUM_DIGITAL) {
  267. rts_pin = portOutputRegister(pin);
  268. #if defined(KINETISL)
  269. rts_mask = digitalPinToBitMask(pin);
  270. #endif
  271. pinMode(pin, OUTPUT);
  272. rts_assert();
  273. } else {
  274. rts_pin = NULL;
  275. return 0;
  276. }
  277. /*
  278. if (pin == 6) {
  279. CORE_PIN6_CONFIG = PORT_PCR_MUX(3);
  280. } else if (pin == 19) {
  281. CORE_PIN19_CONFIG = PORT_PCR_MUX(3);
  282. } else {
  283. UART0_MODEM &= ~UART_MODEM_RXRTSE;
  284. return 0;
  285. }
  286. UART0_MODEM |= UART_MODEM_RXRTSE;
  287. */
  288. return 1;
  289. }
  290. int serial_set_cts(uint8_t pin)
  291. {
  292. #if defined(KINETISK)
  293. if (!(SIM_SCGC4 & SIM_SCGC4_UART0)) return 0;
  294. if (pin == 18) {
  295. CORE_PIN18_CONFIG = PORT_PCR_MUX(3) | PORT_PCR_PE; // weak pulldown
  296. } else if (pin == 20) {
  297. CORE_PIN20_CONFIG = PORT_PCR_MUX(3) | PORT_PCR_PE; // weak pulldown
  298. } else {
  299. UART0_MODEM &= ~UART_MODEM_TXCTSE;
  300. return 0;
  301. }
  302. UART0_MODEM |= UART_MODEM_TXCTSE;
  303. return 1;
  304. #else
  305. return 0;
  306. #endif
  307. }
  308. void serial_putchar(uint32_t c)
  309. {
  310. uint32_t head, n;
  311. if (!(SIM_SCGC4 & SIM_SCGC4_UART0)) return;
  312. if (transmit_pin) transmit_assert();
  313. head = tx_buffer_head;
  314. if (++head >= TX_BUFFER_SIZE) head = 0;
  315. while (tx_buffer_tail == head) {
  316. int priority = nvic_execution_priority();
  317. if (priority <= IRQ_PRIORITY) {
  318. if ((UART0_S1 & UART_S1_TDRE)) {
  319. uint32_t tail = tx_buffer_tail;
  320. if (++tail >= TX_BUFFER_SIZE) tail = 0;
  321. n = tx_buffer[tail];
  322. if (use9Bits) UART0_C3 = (UART0_C3 & ~0x40) | ((n & 0x100) >> 2);
  323. UART0_D = n;
  324. tx_buffer_tail = tail;
  325. }
  326. } else if (priority >= 256) {
  327. yield();
  328. }
  329. }
  330. tx_buffer[head] = c;
  331. transmitting = 1;
  332. tx_buffer_head = head;
  333. UART0_C2 = C2_TX_ACTIVE;
  334. }
  335. #ifdef HAS_KINETISK_UART0_FIFO
  336. void serial_write(const void *buf, unsigned int count)
  337. {
  338. const uint8_t *p = (const uint8_t *)buf;
  339. const uint8_t *end = p + count;
  340. uint32_t head, n;
  341. if (!(SIM_SCGC4 & SIM_SCGC4_UART0)) return;
  342. if (transmit_pin) transmit_assert();
  343. while (p < end) {
  344. head = tx_buffer_head;
  345. if (++head >= TX_BUFFER_SIZE) head = 0;
  346. if (tx_buffer_tail == head) {
  347. UART0_C2 = C2_TX_ACTIVE;
  348. do {
  349. int priority = nvic_execution_priority();
  350. if (priority <= IRQ_PRIORITY) {
  351. if ((UART0_S1 & UART_S1_TDRE)) {
  352. uint32_t tail = tx_buffer_tail;
  353. if (++tail >= TX_BUFFER_SIZE) tail = 0;
  354. n = tx_buffer[tail];
  355. if (use9Bits) UART0_C3 = (UART0_C3 & ~0x40) | ((n & 0x100) >> 2);
  356. UART0_D = n;
  357. tx_buffer_tail = tail;
  358. }
  359. } else if (priority >= 256) {
  360. yield();
  361. }
  362. } while (tx_buffer_tail == head);
  363. }
  364. tx_buffer[head] = *p++;
  365. transmitting = 1;
  366. tx_buffer_head = head;
  367. }
  368. UART0_C2 = C2_TX_ACTIVE;
  369. }
  370. #else
  371. void serial_write(const void *buf, unsigned int count)
  372. {
  373. const uint8_t *p = (const uint8_t *)buf;
  374. while (count-- > 0) serial_putchar(*p++);
  375. }
  376. #endif
  377. void serial_flush(void)
  378. {
  379. while (transmitting) yield(); // wait
  380. }
  381. int serial_write_buffer_free(void)
  382. {
  383. uint32_t head, tail;
  384. head = tx_buffer_head;
  385. tail = tx_buffer_tail;
  386. if (head >= tail) return TX_BUFFER_SIZE - 1 - head + tail;
  387. return tail - head - 1;
  388. }
  389. int serial_available(void)
  390. {
  391. uint32_t head, tail;
  392. head = rx_buffer_head;
  393. tail = rx_buffer_tail;
  394. if (head >= tail) return head - tail;
  395. return RX_BUFFER_SIZE + head - tail;
  396. }
  397. int serial_getchar(void)
  398. {
  399. uint32_t head, tail;
  400. int c;
  401. head = rx_buffer_head;
  402. tail = rx_buffer_tail;
  403. if (head == tail) return -1;
  404. if (++tail >= RX_BUFFER_SIZE) tail = 0;
  405. c = rx_buffer[tail];
  406. rx_buffer_tail = tail;
  407. if (rts_pin) {
  408. int avail;
  409. if (head >= tail) avail = head - tail;
  410. else avail = RX_BUFFER_SIZE + head - tail;
  411. if (avail <= RTS_LOW_WATERMARK) rts_assert();
  412. }
  413. return c;
  414. }
  415. int serial_peek(void)
  416. {
  417. uint32_t head, tail;
  418. head = rx_buffer_head;
  419. tail = rx_buffer_tail;
  420. if (head == tail) return -1;
  421. if (++tail >= RX_BUFFER_SIZE) tail = 0;
  422. return rx_buffer[tail];
  423. }
  424. void serial_clear(void)
  425. {
  426. #ifdef HAS_KINETISK_UART0_FIFO
  427. if (!(SIM_SCGC4 & SIM_SCGC4_UART0)) return;
  428. UART0_C2 &= ~(UART_C2_RE | UART_C2_RIE | UART_C2_ILIE);
  429. UART0_CFIFO = UART_CFIFO_RXFLUSH;
  430. UART0_C2 |= (UART_C2_RE | UART_C2_RIE | UART_C2_ILIE);
  431. #endif
  432. rx_buffer_head = rx_buffer_tail;
  433. if (rts_pin) rts_assert();
  434. }
  435. // status interrupt combines
  436. // Transmit data below watermark UART_S1_TDRE
  437. // Transmit complete UART_S1_TC
  438. // Idle line UART_S1_IDLE
  439. // Receive data above watermark UART_S1_RDRF
  440. // LIN break detect UART_S2_LBKDIF
  441. // RxD pin active edge UART_S2_RXEDGIF
  442. void uart0_status_isr(void)
  443. {
  444. uint32_t head, tail, n;
  445. uint8_t c;
  446. #ifdef HAS_KINETISK_UART0_FIFO
  447. uint32_t newhead;
  448. uint8_t avail;
  449. if (UART0_S1 & (UART_S1_RDRF | UART_S1_IDLE)) {
  450. __disable_irq();
  451. avail = UART0_RCFIFO;
  452. if (avail == 0) {
  453. // The only way to clear the IDLE interrupt flag is
  454. // to read the data register. But reading with no
  455. // data causes a FIFO underrun, which causes the
  456. // FIFO to return corrupted data. If anyone from
  457. // Freescale reads this, what a poor design! There
  458. // write should be a write-1-to-clear for IDLE.
  459. c = UART0_D;
  460. // flushing the fifo recovers from the underrun,
  461. // but there's a possible race condition where a
  462. // new character could be received between reading
  463. // RCFIFO == 0 and flushing the FIFO. To minimize
  464. // the chance, interrupts are disabled so a higher
  465. // priority interrupt (hopefully) doesn't delay.
  466. // TODO: change this to disabling the IDLE interrupt
  467. // which won't be simple, since we already manage
  468. // which transmit interrupts are enabled.
  469. UART0_CFIFO = UART_CFIFO_RXFLUSH;
  470. __enable_irq();
  471. } else {
  472. __enable_irq();
  473. head = rx_buffer_head;
  474. tail = rx_buffer_tail;
  475. do {
  476. if (use9Bits && (UART0_C3 & 0x80)) {
  477. n = UART0_D | 0x100;
  478. } else {
  479. n = UART0_D;
  480. }
  481. newhead = head + 1;
  482. if (newhead >= RX_BUFFER_SIZE) newhead = 0;
  483. if (newhead != tail) {
  484. head = newhead;
  485. rx_buffer[head] = n;
  486. }
  487. } while (--avail > 0);
  488. rx_buffer_head = head;
  489. if (rts_pin) {
  490. int avail;
  491. if (head >= tail) avail = head - tail;
  492. else avail = RX_BUFFER_SIZE + head - tail;
  493. if (avail >= RTS_HIGH_WATERMARK) rts_deassert();
  494. }
  495. }
  496. }
  497. c = UART0_C2;
  498. if ((c & UART_C2_TIE) && (UART0_S1 & UART_S1_TDRE)) {
  499. head = tx_buffer_head;
  500. tail = tx_buffer_tail;
  501. do {
  502. if (tail == head) break;
  503. if (++tail >= TX_BUFFER_SIZE) tail = 0;
  504. avail = UART0_S1;
  505. n = tx_buffer[tail];
  506. if (use9Bits) UART0_C3 = (UART0_C3 & ~0x40) | ((n & 0x100) >> 2);
  507. UART0_D = n;
  508. } while (UART0_TCFIFO < 8);
  509. tx_buffer_tail = tail;
  510. if (UART0_S1 & UART_S1_TDRE) UART0_C2 = C2_TX_COMPLETING;
  511. }
  512. #else
  513. if (UART0_S1 & UART_S1_RDRF) {
  514. n = UART0_D;
  515. if (use9Bits && (UART0_C3 & 0x80)) n |= 0x100;
  516. head = rx_buffer_head + 1;
  517. if (head >= RX_BUFFER_SIZE) head = 0;
  518. if (head != rx_buffer_tail) {
  519. rx_buffer[head] = n;
  520. rx_buffer_head = head;
  521. }
  522. }
  523. c = UART0_C2;
  524. if ((c & UART_C2_TIE) && (UART0_S1 & UART_S1_TDRE)) {
  525. head = tx_buffer_head;
  526. tail = tx_buffer_tail;
  527. if (head == tail) {
  528. UART0_C2 = C2_TX_COMPLETING;
  529. } else {
  530. if (++tail >= TX_BUFFER_SIZE) tail = 0;
  531. n = tx_buffer[tail];
  532. if (use9Bits) UART0_C3 = (UART0_C3 & ~0x40) | ((n & 0x100) >> 2);
  533. UART0_D = n;
  534. tx_buffer_tail = tail;
  535. }
  536. }
  537. #endif
  538. if ((c & UART_C2_TCIE) && (UART0_S1 & UART_S1_TC)) {
  539. transmitting = 0;
  540. if (transmit_pin) transmit_deassert();
  541. UART0_C2 = C2_TX_INACTIVE;
  542. }
  543. }
  544. void serial_print(const char *p)
  545. {
  546. while (*p) {
  547. char c = *p++;
  548. if (c == '\n') serial_putchar('\r');
  549. serial_putchar(c);
  550. }
  551. }
  552. static void serial_phex1(uint32_t n)
  553. {
  554. n &= 15;
  555. if (n < 10) {
  556. serial_putchar('0' + n);
  557. } else {
  558. serial_putchar('A' - 10 + n);
  559. }
  560. }
  561. void serial_phex(uint32_t n)
  562. {
  563. serial_phex1(n >> 4);
  564. serial_phex1(n);
  565. }
  566. void serial_phex16(uint32_t n)
  567. {
  568. serial_phex(n >> 8);
  569. serial_phex(n);
  570. }
  571. void serial_phex32(uint32_t n)
  572. {
  573. serial_phex(n >> 24);
  574. serial_phex(n >> 16);
  575. serial_phex(n >> 8);
  576. serial_phex(n);
  577. }