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  1. /* Teensyduino Core Library
  2. * http://www.pjrc.com/teensy/
  3. * Copyright (c) 2013 PJRC.COM, LLC.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining
  6. * a copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sublicense, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * 1. The above copyright notice and this permission notice shall be
  14. * included in all copies or substantial portions of the Software.
  15. *
  16. * 2. If the Software is incorporated into a build system that allows
  17. * selection among a list of target devices, then similar target
  18. * devices manufactured by PJRC.COM must be included in the list of
  19. * target devices and selectable in the same manner.
  20. *
  21. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  24. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  25. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  26. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  27. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  28. * SOFTWARE.
  29. */
  30. #ifndef _mk20dx128_h_
  31. #define _mk20dx128_h_
  32. //#define F_CPU 96000000
  33. //#define F_CPU 48000000
  34. //#define F_CPU 24000000
  35. //#define F_BUS 48000000
  36. //#define F_BUS 24000000
  37. //#define F_MEM 24000000
  38. #if (F_CPU == 96000000)
  39. #define F_BUS 48000000
  40. #define F_MEM 24000000
  41. #elif (F_CPU == 48000000)
  42. #define F_BUS 48000000
  43. #define F_MEM 24000000
  44. #elif (F_CPU == 24000000)
  45. #define F_BUS 24000000
  46. #define F_MEM 24000000
  47. #endif
  48. #ifndef NULL
  49. #define NULL ((void *)0)
  50. #endif
  51. #include <stdint.h>
  52. #ifdef __cplusplus
  53. extern "C" {
  54. #endif
  55. // chapter 11: Port control and interrupts (PORT)
  56. #define PORTA_PCR0 *(volatile uint32_t *)0x40049000 // Pin Control Register n
  57. #define PORT_PCR_ISF (uint32_t)0x01000000 // Interrupt Status Flag
  58. #define PORT_PCR_IRQC(n) (uint32_t)(((n) & 15) << 16) // Interrupt Configuration
  59. #define PORT_PCR_IRQC_MASK (uint32_t)0x000F0000
  60. #define PORT_PCR_LK (uint32_t)0x00008000 // Lock Register
  61. #define PORT_PCR_MUX(n) (uint32_t)(((n) & 7) << 8) // Pin Mux Control
  62. #define PORT_PCR_MUX_MASK (uint32_t)0x00000700
  63. #define PORT_PCR_DSE (uint32_t)0x00000040 // Drive Strength Enable
  64. #define PORT_PCR_ODE (uint32_t)0x00000020 // Open Drain Enable
  65. #define PORT_PCR_PFE (uint32_t)0x00000010 // Passive Filter Enable
  66. #define PORT_PCR_SRE (uint32_t)0x00000004 // Slew Rate Enable
  67. #define PORT_PCR_PE (uint32_t)0x00000002 // Pull Enable
  68. #define PORT_PCR_PS (uint32_t)0x00000001 // Pull Select
  69. #define PORTA_PCR1 *(volatile uint32_t *)0x40049004 // Pin Control Register n
  70. #define PORTA_PCR2 *(volatile uint32_t *)0x40049008 // Pin Control Register n
  71. #define PORTA_PCR3 *(volatile uint32_t *)0x4004900C // Pin Control Register n
  72. #define PORTA_PCR4 *(volatile uint32_t *)0x40049010 // Pin Control Register n
  73. #define PORTA_PCR5 *(volatile uint32_t *)0x40049014 // Pin Control Register n
  74. #define PORTA_PCR6 *(volatile uint32_t *)0x40049018 // Pin Control Register n
  75. #define PORTA_PCR7 *(volatile uint32_t *)0x4004901C // Pin Control Register n
  76. #define PORTA_PCR8 *(volatile uint32_t *)0x40049020 // Pin Control Register n
  77. #define PORTA_PCR9 *(volatile uint32_t *)0x40049024 // Pin Control Register n
  78. #define PORTA_PCR10 *(volatile uint32_t *)0x40049028 // Pin Control Register n
  79. #define PORTA_PCR11 *(volatile uint32_t *)0x4004902C // Pin Control Register n
  80. #define PORTA_PCR12 *(volatile uint32_t *)0x40049030 // Pin Control Register n
  81. #define PORTA_PCR13 *(volatile uint32_t *)0x40049034 // Pin Control Register n
  82. #define PORTA_PCR14 *(volatile uint32_t *)0x40049038 // Pin Control Register n
  83. #define PORTA_PCR15 *(volatile uint32_t *)0x4004903C // Pin Control Register n
  84. #define PORTA_PCR16 *(volatile uint32_t *)0x40049040 // Pin Control Register n
  85. #define PORTA_PCR17 *(volatile uint32_t *)0x40049044 // Pin Control Register n
  86. #define PORTA_PCR18 *(volatile uint32_t *)0x40049048 // Pin Control Register n
  87. #define PORTA_PCR19 *(volatile uint32_t *)0x4004904C // Pin Control Register n
  88. #define PORTA_PCR20 *(volatile uint32_t *)0x40049050 // Pin Control Register n
  89. #define PORTA_PCR21 *(volatile uint32_t *)0x40049054 // Pin Control Register n
  90. #define PORTA_PCR22 *(volatile uint32_t *)0x40049058 // Pin Control Register n
  91. #define PORTA_PCR23 *(volatile uint32_t *)0x4004905C // Pin Control Register n
  92. #define PORTA_PCR24 *(volatile uint32_t *)0x40049060 // Pin Control Register n
  93. #define PORTA_PCR25 *(volatile uint32_t *)0x40049064 // Pin Control Register n
  94. #define PORTA_PCR26 *(volatile uint32_t *)0x40049068 // Pin Control Register n
  95. #define PORTA_PCR27 *(volatile uint32_t *)0x4004906C // Pin Control Register n
  96. #define PORTA_PCR28 *(volatile uint32_t *)0x40049070 // Pin Control Register n
  97. #define PORTA_PCR29 *(volatile uint32_t *)0x40049074 // Pin Control Register n
  98. #define PORTA_PCR30 *(volatile uint32_t *)0x40049078 // Pin Control Register n
  99. #define PORTA_PCR31 *(volatile uint32_t *)0x4004907C // Pin Control Register n
  100. #define PORTA_GPCLR *(volatile uint32_t *)0x40049080 // Global Pin Control Low Register
  101. #define PORTA_GPCHR *(volatile uint32_t *)0x40049084 // Global Pin Control High Register
  102. #define PORTA_ISFR *(volatile uint32_t *)0x400490A0 // Interrupt Status Flag Register
  103. #define PORTB_PCR0 *(volatile uint32_t *)0x4004A000 // Pin Control Register n
  104. #define PORTB_PCR1 *(volatile uint32_t *)0x4004A004 // Pin Control Register n
  105. #define PORTB_PCR2 *(volatile uint32_t *)0x4004A008 // Pin Control Register n
  106. #define PORTB_PCR3 *(volatile uint32_t *)0x4004A00C // Pin Control Register n
  107. #define PORTB_PCR4 *(volatile uint32_t *)0x4004A010 // Pin Control Register n
  108. #define PORTB_PCR5 *(volatile uint32_t *)0x4004A014 // Pin Control Register n
  109. #define PORTB_PCR6 *(volatile uint32_t *)0x4004A018 // Pin Control Register n
  110. #define PORTB_PCR7 *(volatile uint32_t *)0x4004A01C // Pin Control Register n
  111. #define PORTB_PCR8 *(volatile uint32_t *)0x4004A020 // Pin Control Register n
  112. #define PORTB_PCR9 *(volatile uint32_t *)0x4004A024 // Pin Control Register n
  113. #define PORTB_PCR10 *(volatile uint32_t *)0x4004A028 // Pin Control Register n
  114. #define PORTB_PCR11 *(volatile uint32_t *)0x4004A02C // Pin Control Register n
  115. #define PORTB_PCR12 *(volatile uint32_t *)0x4004A030 // Pin Control Register n
  116. #define PORTB_PCR13 *(volatile uint32_t *)0x4004A034 // Pin Control Register n
  117. #define PORTB_PCR14 *(volatile uint32_t *)0x4004A038 // Pin Control Register n
  118. #define PORTB_PCR15 *(volatile uint32_t *)0x4004A03C // Pin Control Register n
  119. #define PORTB_PCR16 *(volatile uint32_t *)0x4004A040 // Pin Control Register n
  120. #define PORTB_PCR17 *(volatile uint32_t *)0x4004A044 // Pin Control Register n
  121. #define PORTB_PCR18 *(volatile uint32_t *)0x4004A048 // Pin Control Register n
  122. #define PORTB_PCR19 *(volatile uint32_t *)0x4004A04C // Pin Control Register n
  123. #define PORTB_PCR20 *(volatile uint32_t *)0x4004A050 // Pin Control Register n
  124. #define PORTB_PCR21 *(volatile uint32_t *)0x4004A054 // Pin Control Register n
  125. #define PORTB_PCR22 *(volatile uint32_t *)0x4004A058 // Pin Control Register n
  126. #define PORTB_PCR23 *(volatile uint32_t *)0x4004A05C // Pin Control Register n
  127. #define PORTB_PCR24 *(volatile uint32_t *)0x4004A060 // Pin Control Register n
  128. #define PORTB_PCR25 *(volatile uint32_t *)0x4004A064 // Pin Control Register n
  129. #define PORTB_PCR26 *(volatile uint32_t *)0x4004A068 // Pin Control Register n
  130. #define PORTB_PCR27 *(volatile uint32_t *)0x4004A06C // Pin Control Register n
  131. #define PORTB_PCR28 *(volatile uint32_t *)0x4004A070 // Pin Control Register n
  132. #define PORTB_PCR29 *(volatile uint32_t *)0x4004A074 // Pin Control Register n
  133. #define PORTB_PCR30 *(volatile uint32_t *)0x4004A078 // Pin Control Register n
  134. #define PORTB_PCR31 *(volatile uint32_t *)0x4004A07C // Pin Control Register n
  135. #define PORTB_GPCLR *(volatile uint32_t *)0x4004A080 // Global Pin Control Low Register
  136. #define PORTB_GPCHR *(volatile uint32_t *)0x4004A084 // Global Pin Control High Register
  137. #define PORTB_ISFR *(volatile uint32_t *)0x4004A0A0 // Interrupt Status Flag Register
  138. #define PORTC_PCR0 *(volatile uint32_t *)0x4004B000 // Pin Control Register n
  139. #define PORTC_PCR1 *(volatile uint32_t *)0x4004B004 // Pin Control Register n
  140. #define PORTC_PCR2 *(volatile uint32_t *)0x4004B008 // Pin Control Register n
  141. #define PORTC_PCR3 *(volatile uint32_t *)0x4004B00C // Pin Control Register n
  142. #define PORTC_PCR4 *(volatile uint32_t *)0x4004B010 // Pin Control Register n
  143. #define PORTC_PCR5 *(volatile uint32_t *)0x4004B014 // Pin Control Register n
  144. #define PORTC_PCR6 *(volatile uint32_t *)0x4004B018 // Pin Control Register n
  145. #define PORTC_PCR7 *(volatile uint32_t *)0x4004B01C // Pin Control Register n
  146. #define PORTC_PCR8 *(volatile uint32_t *)0x4004B020 // Pin Control Register n
  147. #define PORTC_PCR9 *(volatile uint32_t *)0x4004B024 // Pin Control Register n
  148. #define PORTC_PCR10 *(volatile uint32_t *)0x4004B028 // Pin Control Register n
  149. #define PORTC_PCR11 *(volatile uint32_t *)0x4004B02C // Pin Control Register n
  150. #define PORTC_PCR12 *(volatile uint32_t *)0x4004B030 // Pin Control Register n
  151. #define PORTC_PCR13 *(volatile uint32_t *)0x4004B034 // Pin Control Register n
  152. #define PORTC_PCR14 *(volatile uint32_t *)0x4004B038 // Pin Control Register n
  153. #define PORTC_PCR15 *(volatile uint32_t *)0x4004B03C // Pin Control Register n
  154. #define PORTC_PCR16 *(volatile uint32_t *)0x4004B040 // Pin Control Register n
  155. #define PORTC_PCR17 *(volatile uint32_t *)0x4004B044 // Pin Control Register n
  156. #define PORTC_PCR18 *(volatile uint32_t *)0x4004B048 // Pin Control Register n
  157. #define PORTC_PCR19 *(volatile uint32_t *)0x4004B04C // Pin Control Register n
  158. #define PORTC_PCR20 *(volatile uint32_t *)0x4004B050 // Pin Control Register n
  159. #define PORTC_PCR21 *(volatile uint32_t *)0x4004B054 // Pin Control Register n
  160. #define PORTC_PCR22 *(volatile uint32_t *)0x4004B058 // Pin Control Register n
  161. #define PORTC_PCR23 *(volatile uint32_t *)0x4004B05C // Pin Control Register n
  162. #define PORTC_PCR24 *(volatile uint32_t *)0x4004B060 // Pin Control Register n
  163. #define PORTC_PCR25 *(volatile uint32_t *)0x4004B064 // Pin Control Register n
  164. #define PORTC_PCR26 *(volatile uint32_t *)0x4004B068 // Pin Control Register n
  165. #define PORTC_PCR27 *(volatile uint32_t *)0x4004B06C // Pin Control Register n
  166. #define PORTC_PCR28 *(volatile uint32_t *)0x4004B070 // Pin Control Register n
  167. #define PORTC_PCR29 *(volatile uint32_t *)0x4004B074 // Pin Control Register n
  168. #define PORTC_PCR30 *(volatile uint32_t *)0x4004B078 // Pin Control Register n
  169. #define PORTC_PCR31 *(volatile uint32_t *)0x4004B07C // Pin Control Register n
  170. #define PORTC_GPCLR *(volatile uint32_t *)0x4004B080 // Global Pin Control Low Register
  171. #define PORTC_GPCHR *(volatile uint32_t *)0x4004B084 // Global Pin Control High Register
  172. #define PORTC_ISFR *(volatile uint32_t *)0x4004B0A0 // Interrupt Status Flag Register
  173. #define PORTD_PCR0 *(volatile uint32_t *)0x4004C000 // Pin Control Register n
  174. #define PORTD_PCR1 *(volatile uint32_t *)0x4004C004 // Pin Control Register n
  175. #define PORTD_PCR2 *(volatile uint32_t *)0x4004C008 // Pin Control Register n
  176. #define PORTD_PCR3 *(volatile uint32_t *)0x4004C00C // Pin Control Register n
  177. #define PORTD_PCR4 *(volatile uint32_t *)0x4004C010 // Pin Control Register n
  178. #define PORTD_PCR5 *(volatile uint32_t *)0x4004C014 // Pin Control Register n
  179. #define PORTD_PCR6 *(volatile uint32_t *)0x4004C018 // Pin Control Register n
  180. #define PORTD_PCR7 *(volatile uint32_t *)0x4004C01C // Pin Control Register n
  181. #define PORTD_PCR8 *(volatile uint32_t *)0x4004C020 // Pin Control Register n
  182. #define PORTD_PCR9 *(volatile uint32_t *)0x4004C024 // Pin Control Register n
  183. #define PORTD_PCR10 *(volatile uint32_t *)0x4004C028 // Pin Control Register n
  184. #define PORTD_PCR11 *(volatile uint32_t *)0x4004C02C // Pin Control Register n
  185. #define PORTD_PCR12 *(volatile uint32_t *)0x4004C030 // Pin Control Register n
  186. #define PORTD_PCR13 *(volatile uint32_t *)0x4004C034 // Pin Control Register n
  187. #define PORTD_PCR14 *(volatile uint32_t *)0x4004C038 // Pin Control Register n
  188. #define PORTD_PCR15 *(volatile uint32_t *)0x4004C03C // Pin Control Register n
  189. #define PORTD_PCR16 *(volatile uint32_t *)0x4004C040 // Pin Control Register n
  190. #define PORTD_PCR17 *(volatile uint32_t *)0x4004C044 // Pin Control Register n
  191. #define PORTD_PCR18 *(volatile uint32_t *)0x4004C048 // Pin Control Register n
  192. #define PORTD_PCR19 *(volatile uint32_t *)0x4004C04C // Pin Control Register n
  193. #define PORTD_PCR20 *(volatile uint32_t *)0x4004C050 // Pin Control Register n
  194. #define PORTD_PCR21 *(volatile uint32_t *)0x4004C054 // Pin Control Register n
  195. #define PORTD_PCR22 *(volatile uint32_t *)0x4004C058 // Pin Control Register n
  196. #define PORTD_PCR23 *(volatile uint32_t *)0x4004C05C // Pin Control Register n
  197. #define PORTD_PCR24 *(volatile uint32_t *)0x4004C060 // Pin Control Register n
  198. #define PORTD_PCR25 *(volatile uint32_t *)0x4004C064 // Pin Control Register n
  199. #define PORTD_PCR26 *(volatile uint32_t *)0x4004C068 // Pin Control Register n
  200. #define PORTD_PCR27 *(volatile uint32_t *)0x4004C06C // Pin Control Register n
  201. #define PORTD_PCR28 *(volatile uint32_t *)0x4004C070 // Pin Control Register n
  202. #define PORTD_PCR29 *(volatile uint32_t *)0x4004C074 // Pin Control Register n
  203. #define PORTD_PCR30 *(volatile uint32_t *)0x4004C078 // Pin Control Register n
  204. #define PORTD_PCR31 *(volatile uint32_t *)0x4004C07C // Pin Control Register n
  205. #define PORTD_GPCLR *(volatile uint32_t *)0x4004C080 // Global Pin Control Low Register
  206. #define PORTD_GPCHR *(volatile uint32_t *)0x4004C084 // Global Pin Control High Register
  207. #define PORTD_ISFR *(volatile uint32_t *)0x4004C0A0 // Interrupt Status Flag Register
  208. #define PORTE_PCR0 *(volatile uint32_t *)0x4004D000 // Pin Control Register n
  209. #define PORTE_PCR1 *(volatile uint32_t *)0x4004D004 // Pin Control Register n
  210. #define PORTE_PCR2 *(volatile uint32_t *)0x4004D008 // Pin Control Register n
  211. #define PORTE_PCR3 *(volatile uint32_t *)0x4004D00C // Pin Control Register n
  212. #define PORTE_PCR4 *(volatile uint32_t *)0x4004D010 // Pin Control Register n
  213. #define PORTE_PCR5 *(volatile uint32_t *)0x4004D014 // Pin Control Register n
  214. #define PORTE_PCR6 *(volatile uint32_t *)0x4004D018 // Pin Control Register n
  215. #define PORTE_PCR7 *(volatile uint32_t *)0x4004D01C // Pin Control Register n
  216. #define PORTE_PCR8 *(volatile uint32_t *)0x4004D020 // Pin Control Register n
  217. #define PORTE_PCR9 *(volatile uint32_t *)0x4004D024 // Pin Control Register n
  218. #define PORTE_PCR10 *(volatile uint32_t *)0x4004D028 // Pin Control Register n
  219. #define PORTE_PCR11 *(volatile uint32_t *)0x4004D02C // Pin Control Register n
  220. #define PORTE_PCR12 *(volatile uint32_t *)0x4004D030 // Pin Control Register n
  221. #define PORTE_PCR13 *(volatile uint32_t *)0x4004D034 // Pin Control Register n
  222. #define PORTE_PCR14 *(volatile uint32_t *)0x4004D038 // Pin Control Register n
  223. #define PORTE_PCR15 *(volatile uint32_t *)0x4004D03C // Pin Control Register n
  224. #define PORTE_PCR16 *(volatile uint32_t *)0x4004D040 // Pin Control Register n
  225. #define PORTE_PCR17 *(volatile uint32_t *)0x4004D044 // Pin Control Register n
  226. #define PORTE_PCR18 *(volatile uint32_t *)0x4004D048 // Pin Control Register n
  227. #define PORTE_PCR19 *(volatile uint32_t *)0x4004D04C // Pin Control Register n
  228. #define PORTE_PCR20 *(volatile uint32_t *)0x4004D050 // Pin Control Register n
  229. #define PORTE_PCR21 *(volatile uint32_t *)0x4004D054 // Pin Control Register n
  230. #define PORTE_PCR22 *(volatile uint32_t *)0x4004D058 // Pin Control Register n
  231. #define PORTE_PCR23 *(volatile uint32_t *)0x4004D05C // Pin Control Register n
  232. #define PORTE_PCR24 *(volatile uint32_t *)0x4004D060 // Pin Control Register n
  233. #define PORTE_PCR25 *(volatile uint32_t *)0x4004D064 // Pin Control Register n
  234. #define PORTE_PCR26 *(volatile uint32_t *)0x4004D068 // Pin Control Register n
  235. #define PORTE_PCR27 *(volatile uint32_t *)0x4004D06C // Pin Control Register n
  236. #define PORTE_PCR28 *(volatile uint32_t *)0x4004D070 // Pin Control Register n
  237. #define PORTE_PCR29 *(volatile uint32_t *)0x4004D074 // Pin Control Register n
  238. #define PORTE_PCR30 *(volatile uint32_t *)0x4004D078 // Pin Control Register n
  239. #define PORTE_PCR31 *(volatile uint32_t *)0x4004D07C // Pin Control Register n
  240. #define PORTE_GPCLR *(volatile uint32_t *)0x4004D080 // Global Pin Control Low Register
  241. #define PORTE_GPCHR *(volatile uint32_t *)0x4004D084 // Global Pin Control High Register
  242. #define PORTE_ISFR *(volatile uint32_t *)0x4004D0A0 // Interrupt Status Flag Register
  243. // Chapter 12: System Integration Module (SIM)
  244. #define SIM_SOPT1 *(volatile uint32_t *)0x40047000 // System Options Register 1
  245. #define SIM_SOPT1CFG *(volatile uint32_t *)0x40047004 // SOPT1 Configuration Register
  246. #define SIM_SOPT2 *(volatile uint32_t *)0x40048004 // System Options Register 2
  247. #define SIM_SOPT2_USBSRC (uint32_t)0x00040000 // 0=USB_CLKIN, 1=FFL/PLL
  248. #define SIM_SOPT2_PLLFLLSEL (uint32_t)0x00010000 // 0=FLL, 1=PLL
  249. #define SIM_SOPT2_TRACECLKSEL (uint32_t)0x00001000 // 0=MCGOUTCLK, 1=CPU
  250. #define SIM_SOPT2_PTD7PAD (uint32_t)0x00000800 // 0=normal, 1=double drive PTD7
  251. #define SIM_SOPT2_CLKOUTSEL(n) (uint32_t)(((n) & 7) << 5) // Selects the clock to output on the CLKOUT pin.
  252. #define SIM_SOPT2_RTCCLKOUTSEL (uint32_t)0x00000010 // RTC clock out select
  253. #define SIM_SOPT4 *(volatile uint32_t *)0x4004800C // System Options Register 4
  254. #define SIM_SOPT5 *(volatile uint32_t *)0x40048010 // System Options Register 5
  255. #define SIM_SOPT7 *(volatile uint32_t *)0x40048018 // System Options Register 7
  256. #define SIM_SDID *(const uint32_t *)0x40048024 // System Device Identification Register
  257. #define SIM_SCGC2 *(volatile uint32_t *)0x4004802C // System Clock Gating Control Register 2
  258. #define SIM_SCGC2_DAC0 (uint32_t)0x00001000 // DAC0 Clock Gate Control
  259. #define SIM_SCGC3 *(volatile uint32_t *)0x40048030 // System Clock Gating Control Register 3
  260. #define SIM_SCGC3_ADC1 (uint32_t)0x08000000 // ADC1 Clock Gate Control
  261. #define SIM_SCGC3_FTM2 (uint32_t)0x01000000 // FTM2 Clock Gate Control
  262. #define SIM_SCGC4 *(volatile uint32_t *)0x40048034 // System Clock Gating Control Register 4
  263. #define SIM_SCGC4_VREF (uint32_t)0x00100000 // VREF Clock Gate Control
  264. #define SIM_SCGC4_CMP (uint32_t)0x00080000 // Comparator Clock Gate Control
  265. #define SIM_SCGC4_USBOTG (uint32_t)0x00040000 // USB Clock Gate Control
  266. #define SIM_SCGC4_UART2 (uint32_t)0x00001000 // UART2 Clock Gate Control
  267. #define SIM_SCGC4_UART1 (uint32_t)0x00000800 // UART1 Clock Gate Control
  268. #define SIM_SCGC4_UART0 (uint32_t)0x00000400 // UART0 Clock Gate Control
  269. #define SIM_SCGC4_I2C1 (uint32_t)0x00000080 // I2C1 Clock Gate Control
  270. #define SIM_SCGC4_I2C0 (uint32_t)0x00000040 // I2C0 Clock Gate Control
  271. #define SIM_SCGC4_CMT (uint32_t)0x00000004 // CMT Clock Gate Control
  272. #define SIM_SCGC4_EWM (uint32_t)0x00000002 // EWM Clock Gate Control
  273. #define SIM_SCGC5 *(volatile uint32_t *)0x40048038 // System Clock Gating Control Register 5
  274. #define SIM_SCGC5_PORTE (uint32_t)0x00002000 // Port E Clock Gate Control
  275. #define SIM_SCGC5_PORTD (uint32_t)0x00001000 // Port D Clock Gate Control
  276. #define SIM_SCGC5_PORTC (uint32_t)0x00000800 // Port C Clock Gate Control
  277. #define SIM_SCGC5_PORTB (uint32_t)0x00000400 // Port B Clock Gate Control
  278. #define SIM_SCGC5_PORTA (uint32_t)0x00000200 // Port A Clock Gate Control
  279. #define SIM_SCGC5_TSI (uint32_t)0x00000020 // Touch Sense Input TSI Clock Gate Control
  280. #define SIM_SCGC5_LPTIMER (uint32_t)0x00000001 // Low Power Timer Access Control
  281. #define SIM_SCGC6 *(volatile uint32_t *)0x4004803C // System Clock Gating Control Register 6
  282. #define SIM_SCGC6_RTC (uint32_t)0x20000000 // RTC Access
  283. #define SIM_SCGC6_ADC0 (uint32_t)0x08000000 // ADC0 Clock Gate Control
  284. #define SIM_SCGC6_FTM1 (uint32_t)0x02000000 // FTM1 Clock Gate Control
  285. #define SIM_SCGC6_FTM0 (uint32_t)0x01000000 // FTM0 Clock Gate Control
  286. #define SIM_SCGC6_PIT (uint32_t)0x00800000 // PIT Clock Gate Control
  287. #define SIM_SCGC6_PDB (uint32_t)0x00400000 // PDB Clock Gate Control
  288. #define SIM_SCGC6_USBDCD (uint32_t)0x00200000 // USB DCD Clock Gate Control
  289. #define SIM_SCGC6_CRC (uint32_t)0x00040000 // CRC Clock Gate Control
  290. #define SIM_SCGC6_I2S (uint32_t)0x00008000 // I2S Clock Gate Control
  291. #define SIM_SCGC6_SPI1 (uint32_t)0x00002000 // SPI1 Clock Gate Control
  292. #define SIM_SCGC6_SPI0 (uint32_t)0x00001000 // SPI0 Clock Gate Control
  293. #define SIM_SCGC6_FLEXCAN0 (uint32_t)0x00000010 // FlexCAN0 Clock Gate Control
  294. #define SIM_SCGC6_DMAMUX (uint32_t)0x00000002 // DMA Mux Clock Gate Control
  295. #define SIM_SCGC6_FTFL (uint32_t)0x00000001 // Flash Memory Clock Gate Control
  296. #define SIM_SCGC7 *(volatile uint32_t *)0x40048040 // System Clock Gating Control Register 7
  297. #define SIM_SCGC7_DMA (uint32_t)0x00000002 // DMA Clock Gate Control
  298. #define SIM_CLKDIV1 *(volatile uint32_t *)0x40048044 // System Clock Divider Register 1
  299. #define SIM_CLKDIV1_OUTDIV1(n) (uint32_t)(((n) & 0x0F) << 28) // divide value for the core/system clock
  300. #define SIM_CLKDIV1_OUTDIV2(n) (uint32_t)(((n) & 0x0F) << 24) // divide value for the peripheral clock
  301. #define SIM_CLKDIV1_OUTDIV4(n) (uint32_t)(((n) & 0x0F) << 16) // divide value for the flash clock
  302. #define SIM_CLKDIV2 *(volatile uint32_t *)0x40048048 // System Clock Divider Register 2
  303. #define SIM_CLKDIV2_USBDIV(n) (uint32_t)(((n) & 0x07) << 1)
  304. #define SIM_CLKDIV2_USBFRAC (uint32_t)0x01
  305. #define SIM_FCFG1 *(const uint32_t *)0x4004804C // Flash Configuration Register 1
  306. #define SIM_FCFG2 *(const uint32_t *)0x40048050 // Flash Configuration Register 2
  307. #define SIM_UIDH *(const uint32_t *)0x40048054 // Unique Identification Register High
  308. #define SIM_UIDMH *(const uint32_t *)0x40048058 // Unique Identification Register Mid-High
  309. #define SIM_UIDML *(const uint32_t *)0x4004805C // Unique Identification Register Mid Low
  310. #define SIM_UIDL *(const uint32_t *)0x40048060 // Unique Identification Register Low
  311. // Chapter 13: Reset Control Module (RCM)
  312. #define RCM_SRS0 *(volatile uint8_t *)0x4007F000 // System Reset Status Register 0
  313. #define RCM_SRS1 *(volatile uint8_t *)0x4007F001 // System Reset Status Register 1
  314. #define RCM_RPFC *(volatile uint8_t *)0x4007F004 // Reset Pin Filter Control Register
  315. #define RCM_RPFW *(volatile uint8_t *)0x4007F005 // Reset Pin Filter Width Register
  316. #define RCM_MR *(volatile uint8_t *)0x4007F007 // Mode Register
  317. // Chapter 14: System Mode Controller
  318. #define SMC_PMPROT *(volatile uint8_t *)0x4007E000 // Power Mode Protection Register
  319. #define SMC_PMPROT_AVLP (uint8_t)0x20 // Allow very low power modes
  320. #define SMC_PMPROT_ALLS (uint8_t)0x08 // Allow low leakage stop mode
  321. #define SMC_PMPROT_AVLLS (uint8_t)0x02 // Allow very low leakage stop mode
  322. #define SMC_PMCTRL *(volatile uint8_t *)0x4007E001 // Power Mode Control Register
  323. #define SMC_PMCTRL_LPWUI (uint8_t)0x80 // Low Power Wake Up on Interrupt
  324. #define SMC_PMCTRL_RUNM(n) (uint8_t)(((n) & 0x03) << 5) // Run Mode Control
  325. #define SMC_PMCTRL_STOPA (uint8_t)0x08 // Stop Aborted
  326. #define SMC_PMCTRL_STOPM(n) (uint8_t)((n) & 0x07) // Stop Mode Control
  327. #define SMC_VLLSCTRL *(volatile uint8_t *)0x4007E002 // VLLS Control Register
  328. #define SMC_VLLSCTRL_PORPO (uint8_t)0x20 // POR Power Option
  329. #define SMC_VLLSCTRL_VLLSM(n) (uint8_t)((n) & 0x07) // VLLS Mode Control
  330. #define SMC_PMSTAT *(volatile uint8_t *)0x4007E003 // Power Mode Status Register
  331. #define SMC_PMSTAT_RUN (uint8_t)0x01 // Current power mode is RUN
  332. #define SMC_PMSTAT_STOP (uint8_t)0x02 // Current power mode is STOP
  333. #define SMC_PMSTAT_VLPR (uint8_t)0x04 // Current power mode is VLPR
  334. #define SMC_PMSTAT_VLPW (uint8_t)0x08 // Current power mode is VLPW
  335. #define SMC_PMSTAT_VLPS (uint8_t)0x10 // Current power mode is VLPS
  336. #define SMC_PMSTAT_LLS (uint8_t)0x20 // Current power mode is LLS
  337. #define SMC_PMSTAT_VLLS (uint8_t)0x40 // Current power mode is VLLS
  338. // Chapter 15: Power Management Controller
  339. #define PMC_LVDSC1 *(volatile uint8_t *)0x4007D000 // Low Voltage Detect Status And Control 1 register
  340. #define PMC_LVDSC1_LVDF (uint8_t)0x80 // Low-Voltage Detect Flag
  341. #define PMC_LVDSC1_LVDACK (uint8_t)0x40 // Low-Voltage Detect Acknowledge
  342. #define PMC_LVDSC1_LVDIE (uint8_t)0x20 // Low-Voltage Detect Interrupt Enable
  343. #define PMC_LVDSC1_LVDRE (uint8_t)0x10 // Low-Voltage Detect Reset Enable
  344. #define PMC_LVDSC1_LVDV(n) (uint8_t)((n) & 0x03) // Low-Voltage Detect Voltage Select
  345. #define PMC_LVDSC2 *(volatile uint8_t *)0x4007D001 // Low Voltage Detect Status And Control 2 register
  346. #define PMC_LVDSC2_LVWF (uint8_t)0x80 // Low-Voltage Warning Flag
  347. #define PMC_LVDSC2_LVWACK (uint8_t)0x40 // Low-Voltage Warning Acknowledge
  348. #define PMC_LVDSC2_LVWIE (uint8_t)0x20 // Low-Voltage Warning Interrupt Enable
  349. #define PMC_LVDSC2_LVWV(n) (uint8_t)((n) & 0x03) // Low-Voltage Warning Voltage Select
  350. #define PMC_REGSC *(volatile uint8_t *)0x4007D002 // Regulator Status And Control register
  351. #define PMC_REGSC_BGEN (uint8_t)0x10 // Bandgap Enable In VLPx Operation
  352. #define PMC_REGSC_ACKISO (uint8_t)0x08 // Acknowledge Isolation
  353. #define PMC_REGSC_REGONS (uint8_t)0x04 // Regulator In Run Regulation Status
  354. #define PMC_REGSC_BGBE (uint8_t)0x01 // Bandgap Buffer Enable
  355. // Chapter 16: Low-Leakage Wakeup Unit (LLWU)
  356. #define LLWU_PE1 *(volatile uint8_t *)0x4007C000 // LLWU Pin Enable 1 register
  357. #define LLWU_PE2 *(volatile uint8_t *)0x4007C001 // LLWU Pin Enable 2 register
  358. #define LLWU_PE3 *(volatile uint8_t *)0x4007C002 // LLWU Pin Enable 3 register
  359. #define LLWU_PE4 *(volatile uint8_t *)0x4007C003 // LLWU Pin Enable 4 register
  360. #define LLWU_ME *(volatile uint8_t *)0x4007C004 // LLWU Module Enable register
  361. #define LLWU_F1 *(volatile uint8_t *)0x4007C005 // LLWU Flag 1 register
  362. #define LLWU_F2 *(volatile uint8_t *)0x4007C006 // LLWU Flag 2 register
  363. #define LLWU_F3 *(volatile uint8_t *)0x4007C007 // LLWU Flag 3 register
  364. #define LLWU_FILT1 *(volatile uint8_t *)0x4007C008 // LLWU Pin Filter 1 register
  365. #define LLWU_FILT2 *(volatile uint8_t *)0x4007C009 // LLWU Pin Filter 2 register
  366. #define LLWU_RST *(volatile uint8_t *)0x4007C00A // LLWU Reset Enable register
  367. // Chapter 17: Miscellaneous Control Module (MCM)
  368. #define MCM_PLASC *(volatile uint16_t *)0xE0080008 // Crossbar Switch (AXBS) Slave Configuration
  369. #define MCM_PLAMC *(volatile uint16_t *)0xE008000A // Crossbar Switch (AXBS) Master Configuration
  370. #define MCM_PLACR *(volatile uint32_t *)0xE008000C // Crossbar Switch (AXBS) Control Register (MK20DX128)
  371. #define MCM_PLACR_ARG (uint32_t)0x00000200 // Arbitration select, 0=fixed, 1=round-robin
  372. #define MCM_CR *(volatile uint32_t *)0xE008000C // RAM arbitration control register (MK20DX256)
  373. #define MCM_CR_SRAMLWP (uint32_t)0x40000000 // SRAM_L write protect
  374. #define MCM_CR_SRAMLAP(n) (uint32_t)(((n) & 0x03) << 28) // SRAM_L priority, 0=RR, 1=favor DMA, 2=CPU, 3=DMA
  375. #define MCM_CR_SRAMUWP (uint32_t)0x04000000 // SRAM_U write protect
  376. #define MCM_CR_SRAMUAP(n) (uint32_t)(((n) & 0x03) << 24) // SRAM_U priority, 0=RR, 1=favor DMA, 2=CPU, 3=DMA
  377. // Crossbar Switch (AXBS) - only programmable on MK20DX256
  378. #define AXBS_PRS0 *(volatile uint32_t *)0x40004000 // Priority Registers Slave 0
  379. #define AXBS_CRS0 *(volatile uint32_t *)0x40004010 // Control Register 0
  380. #define AXBS_PRS1 *(volatile uint32_t *)0x40004100 // Priority Registers Slave 1
  381. #define AXBS_CRS1 *(volatile uint32_t *)0x40004110 // Control Register 1
  382. #define AXBS_PRS2 *(volatile uint32_t *)0x40004200 // Priority Registers Slave 2
  383. #define AXBS_CRS2 *(volatile uint32_t *)0x40004210 // Control Register 2
  384. #define AXBS_PRS3 *(volatile uint32_t *)0x40004300 // Priority Registers Slave 3
  385. #define AXBS_CRS3 *(volatile uint32_t *)0x40004310 // Control Register 3
  386. #define AXBS_PRS4 *(volatile uint32_t *)0x40004400 // Priority Registers Slave 4
  387. #define AXBS_CRS4 *(volatile uint32_t *)0x40004410 // Control Register 4
  388. #define AXBS_PRS5 *(volatile uint32_t *)0x40004500 // Priority Registers Slave 5
  389. #define AXBS_CRS5 *(volatile uint32_t *)0x40004510 // Control Register 5
  390. #define AXBS_PRS6 *(volatile uint32_t *)0x40004600 // Priority Registers Slave 6
  391. #define AXBS_CRS6 *(volatile uint32_t *)0x40004610 // Control Register 6
  392. #define AXBS_PRS7 *(volatile uint32_t *)0x40004700 // Priority Registers Slave 7
  393. #define AXBS_CRS7 *(volatile uint32_t *)0x40004710 // Control Register 7
  394. #define AXBS_MGPCR0 *(volatile uint32_t *)0x40004800 // Master 0 General Purpose Control Register
  395. #define AXBS_MGPCR1 *(volatile uint32_t *)0x40004900 // Master 1 General Purpose Control Register
  396. #define AXBS_MGPCR2 *(volatile uint32_t *)0x40004A00 // Master 2 General Purpose Control Register
  397. #define AXBS_MGPCR3 *(volatile uint32_t *)0x40004B00 // Master 3 General Purpose Control Register
  398. #define AXBS_MGPCR4 *(volatile uint32_t *)0x40004C00 // Master 4 General Purpose Control Register
  399. #define AXBS_MGPCR5 *(volatile uint32_t *)0x40004D00 // Master 5 General Purpose Control Register
  400. #define AXBS_MGPCR6 *(volatile uint32_t *)0x40004E00 // Master 6 General Purpose Control Register
  401. #define AXBS_MGPCR7 *(volatile uint32_t *)0x40004F00 // Master 7 General Purpose Control Register
  402. #define AXBS_CRS_READONLY (uint32_t)0x80000000
  403. #define AXBS_CRS_HALTLOWPRIORITY (uint32_t)0x40000000
  404. #define AXBS_CRS_ARB_FIXED (uint32_t)0x00000000
  405. #define AXBS_CRS_ARB_ROUNDROBIN (uint32_t)0x00010000
  406. #define AXBS_CRS_PARK_FIXED (uint32_t)0x00000000
  407. #define AXBS_CRS_PARK_PREVIOUS (uint32_t)0x00000010
  408. #define AXBS_CRS_PARK_NONE (uint32_t)0x00000020
  409. #define AXBS_CRS_PARK(n) (uint32_t)(((n) & 7) << 0)
  410. // Chapter 20: Direct Memory Access Multiplexer (DMAMUX)
  411. #define DMAMUX0_CHCFG0 *(volatile uint8_t *)0x40021000 // Channel Configuration register
  412. #define DMAMUX0_CHCFG1 *(volatile uint8_t *)0x40021001 // Channel Configuration register
  413. #define DMAMUX0_CHCFG2 *(volatile uint8_t *)0x40021002 // Channel Configuration register
  414. #define DMAMUX0_CHCFG3 *(volatile uint8_t *)0x40021003 // Channel Configuration register
  415. #define DMAMUX0_CHCFG4 *(volatile uint8_t *)0x40021004 // Channel Configuration register
  416. #define DMAMUX0_CHCFG5 *(volatile uint8_t *)0x40021005 // Channel Configuration register
  417. #define DMAMUX0_CHCFG6 *(volatile uint8_t *)0x40021006 // Channel Configuration register
  418. #define DMAMUX0_CHCFG7 *(volatile uint8_t *)0x40021007 // Channel Configuration register
  419. #define DMAMUX0_CHCFG8 *(volatile uint8_t *)0x40021008 // Channel Configuration register
  420. #define DMAMUX0_CHCFG9 *(volatile uint8_t *)0x40021009 // Channel Configuration register
  421. #define DMAMUX0_CHCFG10 *(volatile uint8_t *)0x4002100A // Channel Configuration register
  422. #define DMAMUX0_CHCFG11 *(volatile uint8_t *)0x4002100B // Channel Configuration register
  423. #define DMAMUX0_CHCFG12 *(volatile uint8_t *)0x4002100C // Channel Configuration register
  424. #define DMAMUX0_CHCFG13 *(volatile uint8_t *)0x4002100D // Channel Configuration register
  425. #define DMAMUX0_CHCFG14 *(volatile uint8_t *)0x4002100E // Channel Configuration register
  426. #define DMAMUX0_CHCFG15 *(volatile uint8_t *)0x4002100F // Channel Configuration register
  427. #define DMAMUX_DISABLE 0
  428. #define DMAMUX_TRIG 64
  429. #define DMAMUX_ENABLE 128
  430. #define DMAMUX_SOURCE_UART0_RX 2
  431. #define DMAMUX_SOURCE_UART0_TX 3
  432. #define DMAMUX_SOURCE_UART1_RX 4
  433. #define DMAMUX_SOURCE_UART1_TX 5
  434. #define DMAMUX_SOURCE_UART2_RX 6
  435. #define DMAMUX_SOURCE_UART2_TX 7
  436. #define DMAMUX_SOURCE_I2S0_RX 14
  437. #define DMAMUX_SOURCE_I2S0_TX 15
  438. #define DMAMUX_SOURCE_SPI0_RX 16
  439. #define DMAMUX_SOURCE_SPI0_TX 17
  440. #define DMAMUX_SOURCE_I2C0 22
  441. #define DMAMUX_SOURCE_I2C1 23
  442. #define DMAMUX_SOURCE_FTM0_CH0 24
  443. #define DMAMUX_SOURCE_FTM0_CH1 25
  444. #define DMAMUX_SOURCE_FTM0_CH2 26
  445. #define DMAMUX_SOURCE_FTM0_CH3 27
  446. #define DMAMUX_SOURCE_FTM0_CH4 28
  447. #define DMAMUX_SOURCE_FTM0_CH5 29
  448. #define DMAMUX_SOURCE_FTM0_CH6 30
  449. #define DMAMUX_SOURCE_FTM0_CH7 31
  450. #define DMAMUX_SOURCE_FTM1_CH0 32
  451. #define DMAMUX_SOURCE_FTM1_CH1 33
  452. #define DMAMUX_SOURCE_FTM2_CH0 34
  453. #define DMAMUX_SOURCE_FTM2_CH1 35
  454. #define DMAMUX_SOURCE_ADC0 40
  455. #define DMAMUX_SOURCE_ADC1 41
  456. #define DMAMUX_SOURCE_CMP0 42
  457. #define DMAMUX_SOURCE_CMP1 43
  458. #define DMAMUX_SOURCE_CMP2 44
  459. #define DMAMUX_SOURCE_DAC0 45
  460. #define DMAMUX_SOURCE_CMT 47
  461. #define DMAMUX_SOURCE_PDB 48
  462. #define DMAMUX_SOURCE_PORTA 49
  463. #define DMAMUX_SOURCE_PORTB 50
  464. #define DMAMUX_SOURCE_PORTC 51
  465. #define DMAMUX_SOURCE_PORTD 52
  466. #define DMAMUX_SOURCE_PORTE 53
  467. #define DMAMUX_SOURCE_ALWAYS0 54
  468. #define DMAMUX_SOURCE_ALWAYS1 55
  469. #define DMAMUX_SOURCE_ALWAYS2 56
  470. #define DMAMUX_SOURCE_ALWAYS3 57
  471. #define DMAMUX_SOURCE_ALWAYS4 58
  472. #define DMAMUX_SOURCE_ALWAYS5 59
  473. #define DMAMUX_SOURCE_ALWAYS6 60
  474. #define DMAMUX_SOURCE_ALWAYS7 61
  475. #define DMAMUX_SOURCE_ALWAYS8 62
  476. #define DMAMUX_SOURCE_ALWAYS9 63
  477. // Chapter 21: Direct Memory Access Controller (eDMA)
  478. #define DMA_CR *(volatile uint32_t *)0x40008000 // Control Register
  479. #define DMA_CR_CX ((uint32_t)(1<<17)) // Cancel Transfer
  480. #define DMA_CR_ECX ((uint32_t)(1<<16)) // Error Cancel Transfer
  481. #define DMA_CR_EMLM ((uint32_t)0x80) // Enable Minor Loop Mapping
  482. #define DMA_CR_CLM ((uint32_t)0x40) // Continuous Link Mode
  483. #define DMA_CR_HALT ((uint32_t)0x20) // Halt DMA Operations
  484. #define DMA_CR_HOE ((uint32_t)0x10) // Halt On Error
  485. #define DMA_CR_ERCA ((uint32_t)0x04) // Enable Round Robin Channel Arbitration
  486. #define DMA_CR_EDBG ((uint32_t)0x02) // Enable Debug
  487. #define DMA_ES *(volatile uint32_t *)0x40008004 // Error Status Register
  488. #define DMA_ERQ *(volatile uint32_t *)0x4000800C // Enable Request Register
  489. #define DMA_ERQ_ERQ0 ((uint32_t)1<<0) // Enable DMA Request 0
  490. #define DMA_ERQ_ERQ1 ((uint32_t)1<<1) // Enable DMA Request 1
  491. #define DMA_ERQ_ERQ2 ((uint32_t)1<<2) // Enable DMA Request 2
  492. #define DMA_ERQ_ERQ3 ((uint32_t)1<<3) // Enable DMA Request 3
  493. #define DMA_EEI *(volatile uint32_t *)0x40008014 // Enable Error Interrupt Register
  494. #define DMA_EEI_EEI0 ((uint32_t)1<<0) // Enable Error Interrupt 0
  495. #define DMA_EEI_EEI1 ((uint32_t)1<<1) // Enable Error Interrupt 1
  496. #define DMA_EEI_EEI2 ((uint32_t)1<<2) // Enable Error Interrupt 2
  497. #define DMA_EEI_EEI3 ((uint32_t)1<<3) // Enable Error Interrupt 3
  498. #define DMA_CEEI *(volatile uint8_t *)0x40008018 // Clear Enable Error Interrupt Register
  499. #define DMA_CEEI_CEEI(n) ((uint8_t)(n & 3)<<0) // Clear Enable Error Interrupt
  500. #define DMA_CEEI_CAEE ((uint8_t)1<<6) // Clear All Enable Error Interrupts
  501. #define DMA_CEEI_NOP ((uint8_t)1<<7) // NOP
  502. #define DMA_SEEI *(volatile uint8_t *)0x40008019 // Set Enable Error Interrupt Register
  503. #define DMA_SEEI_SEEI(n) ((uint8_t)(n & 3)<<0) // Set Enable Error Interrupt
  504. #define DMA_SEEI_SAEE ((uint8_t)1<<6) // Set All Enable Error Interrupts
  505. #define DMA_SEEI_NOP ((uint8_t)1<<7) // NOP
  506. #define DMA_CERQ *(volatile uint8_t *)0x4000801A // Clear Enable Request Register
  507. #define DMA_CERQ_CERQ(n) ((uint8_t)(n & 3)<<0) // Clear Enable Request
  508. #define DMA_CERQ_CAER ((uint8_t)1<<6) // Clear All Enable Requests
  509. #define DMA_CERQ_NOP ((uint8_t)1<<7) // NOP
  510. #define DMA_SERQ *(volatile uint8_t *)0x4000801B // Set Enable Request Register
  511. #define DMA_SERQ_SERQ(n) ((uint8_t)(n & 3)<<0) // Set Enable Request
  512. #define DMA_SERQ_SAER ((uint8_t)1<<6) // Set All Enable Requests
  513. #define DMA_SERQ_NOP ((uint8_t)1<<7) // NOP
  514. #define DMA_CDNE *(volatile uint8_t *)0x4000801C // Clear DONE Status Bit Register
  515. #define DMA_CDNE_CDNE(n) ((uint8_t)(n & 3)<<0) // Clear Done Bit
  516. #define DMA_CDNE_CADN ((uint8_t)1<<6) // Clear All Done Bits
  517. #define DMA_CDNE_NOP ((uint8_t)1<<7) // NOP
  518. #define DMA_SSRT *(volatile uint8_t *)0x4000801D // Set START Bit Register
  519. #define DMA_SSRT_SSRT(n) ((uint8_t)(n & 3)<<0) // Set Start Bit
  520. #define DMA_SSRT_SAST ((uint8_t)1<<6) // Set All Start Bits
  521. #define DMA_SSRT_NOP ((uint8_t)1<<7) // NOP
  522. #define DMA_CERR *(volatile uint8_t *)0x4000801E // Clear Error Register
  523. #define DMA_CERR_CERR(n) ((uint8_t)(n & 3)<<0) // Clear Error Indicator
  524. #define DMA_CERR_CAEI ((uint8_t)1<<6) // Clear All Error Indicators
  525. #define DMA_CERR_NOP ((uint8_t)1<<7) // NOP
  526. #define DMA_CINT *(volatile uint8_t *)0x4000801F // Clear Interrupt Request Register
  527. #define DMA_CINT_CINT(n) ((uint8_t)(n & 3)<<0) // Clear Interrupt Request
  528. #define DMA_CINT_CAIR ((uint8_t)1<<6) // Clear All Interrupt Requests
  529. #define DMA_CINT_NOP ((uint8_t)1<<7) // NOP
  530. #define DMA_INT *(volatile uint32_t *)0x40008024 // Interrupt Request Register
  531. #define DMA_INT_INT0 ((uint32_t)1<<0) // Interrupt Request 0
  532. #define DMA_INT_INT1 ((uint32_t)1<<1) // Interrupt Request 1
  533. #define DMA_INT_INT2 ((uint32_t)1<<2) // Interrupt Request 2
  534. #define DMA_INT_INT3 ((uint32_t)1<<3) // Interrupt Request 3
  535. #define DMA_ERR *(volatile uint32_t *)0x4000802C // Error Register
  536. #define DMA_ERR_ERR0 ((uint32_t)1<<0) // Error in Channel 0
  537. #define DMA_ERR_ERR1 ((uint32_t)1<<1) // Error in Channel 1
  538. #define DMA_ERR_ERR2 ((uint32_t)1<<2) // Error in Channel 2
  539. #define DMA_ERR_ERR3 ((uint32_t)1<<3) // Error in Channel 3
  540. #define DMA_HRS *(volatile uint32_t *)0x40008034 // Hardware Request Status Register
  541. #define DMA_HRS_HRS0 ((uint32_t)1<<0) // Hardware Request Status Channel 0
  542. #define DMA_HRS_HRS1 ((uint32_t)1<<1) // Hardware Request Status Channel 1
  543. #define DMA_HRS_HRS2 ((uint32_t)1<<2) // Hardware Request Status Channel 2
  544. #define DMA_HRS_HRS3 ((uint32_t)1<<3) // Hardware Request Status Channel 3
  545. #define DMA_DCHPRI3 *(volatile uint8_t *)0x40008100 // Channel n Priority Register
  546. #define DMA_DCHPRI2 *(volatile uint8_t *)0x40008101 // Channel n Priority Register
  547. #define DMA_DCHPRI1 *(volatile uint8_t *)0x40008102 // Channel n Priority Register
  548. #define DMA_DCHPRI0 *(volatile uint8_t *)0x40008103 // Channel n Priority Register
  549. #define DMA_DCHPRI_CHPRI(n) ((uint8_t)(n & 3)<<0) // Channel Arbitration Priority
  550. #define DMA_DCHPRI_DPA ((uint8_t)1<<6) // Disable PreEmpt Ability
  551. #define DMA_DCHPRI_ECP ((uint8_t)1<<7) // Enable PreEmption
  552. #define DMA_TCD_ATTR_SMOD(n) (((n) & 0x1F) << 11)
  553. #define DMA_TCD_ATTR_SSIZE(n) (((n) & 0x7) << 8)
  554. #define DMA_TCD_ATTR_DMOD(n) (((n) & 0x1F) << 3)
  555. #define DMA_TCD_ATTR_DSIZE(n) (((n) & 0x7) << 0)
  556. #define DMA_TCD_ATTR_SIZE_8BIT 0
  557. #define DMA_TCD_ATTR_SIZE_16BIT 1
  558. #define DMA_TCD_ATTR_SIZE_32BIT 2
  559. #define DMA_TCD_ATTR_SIZE_16BYTE 4
  560. #define DMA_TCD_ATTR_SIZE_32BYTE 5
  561. #define DMA_TCD_CSR_BWC(n) (((n) & 0x3) << 14)
  562. #define DMA_TCD_CSR_MAJORLINKCH(n) (((n) & 0x3) << 8)
  563. #define DMA_TCD_CSR_DONE 0x0080
  564. #define DMA_TCD_CSR_ACTIVE 0x0040
  565. #define DMA_TCD_CSR_MAJORELINK 0x0020
  566. #define DMA_TCD_CSR_ESG 0x0010
  567. #define DMA_TCD_CSR_DREQ 0x0008
  568. #define DMA_TCD_CSR_INTHALF 0x0004
  569. #define DMA_TCD_CSR_INTMAJOR 0x0002
  570. #define DMA_TCD_CSR_START 0x0001
  571. #define DMA_TCD_CITER_MASK ((uint16_t)0x7FFF) // Loop count mask
  572. #define DMA_TCD_CITER_ELINK ((uint16_t)1<<15) // Enable channel linking on minor-loop complete
  573. #define DMA_TCD_BITER_MASK ((uint16_t)0x7FFF) // Loop count mask
  574. #define DMA_TCD_BITER_ELINK ((uint16_t)1<<15) // Enable channel linking on minor-loop complete
  575. #define DMA_TCD_NBYTES_SMLOE ((uint32_t)1<<31) // Source Minor Loop Offset Enable
  576. #define DMA_TCD_NBYTES_DMLOE ((uint32_t)1<<30) // Destination Minor Loop Offset Enable
  577. #define DMA_TCD_NBYTES_MLOFFNO_NBYTES(n) ((uint32_t)(n)) // NBytes transfer count when minor loop disabled
  578. #define DMA_TCD_NBYTES_MLOFFYES_NBYTES(n) ((uint32_t)(n & 0x1F)) // NBytes transfer count when minor loop enabled
  579. #define DMA_TCD_NBYTES_MLOFFYES_MLOFF(n) ((uint32_t)(n & 0xFFFFF)<<10) // Offset
  580. #define DMA_TCD0_SADDR *(volatile const void * volatile *)0x40009000 // TCD Source Address
  581. #define DMA_TCD0_SOFF *(volatile int16_t *)0x40009004 // TCD Signed Source Address Offset
  582. #define DMA_TCD0_ATTR *(volatile uint16_t *)0x40009006 // TCD Transfer Attributes
  583. #define DMA_TCD0_NBYTES_MLNO *(volatile uint32_t *)0x40009008 // TCD Minor Byte Count (Minor Loop Disabled)
  584. #define DMA_TCD0_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009008 // TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
  585. #define DMA_TCD0_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009008 // TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
  586. #define DMA_TCD0_SLAST *(volatile int32_t *)0x4000900C // TCD Last Source Address Adjustment
  587. #define DMA_TCD0_DADDR *(volatile void * volatile *)0x40009010 // TCD Destination Address
  588. #define DMA_TCD0_DOFF *(volatile int16_t *)0x40009014 // TCD Signed Destination Address Offset
  589. #define DMA_TCD0_CITER_ELINKYES *(volatile uint16_t *)0x40009016 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled
  590. #define DMA_TCD0_CITER_ELINKNO *(volatile uint16_t *)0x40009016 // ??
  591. #define DMA_TCD0_DLASTSGA *(volatile int32_t *)0x40009018 // TCD Last Destination Address Adjustment/Scatter Gather Address
  592. #define DMA_TCD0_CSR *(volatile uint16_t *)0x4000901C // TCD Control and Status
  593. #define DMA_TCD0_BITER_ELINKYES *(volatile uint16_t *)0x4000901E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Enabled
  594. #define DMA_TCD0_BITER_ELINKNO *(volatile uint16_t *)0x4000901E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled
  595. #define DMA_TCD1_SADDR *(volatile const void * volatile *)0x40009020 // TCD Source Address
  596. #define DMA_TCD1_SOFF *(volatile int16_t *)0x40009024 // TCD Signed Source Address Offset
  597. #define DMA_TCD1_ATTR *(volatile uint16_t *)0x40009026 // TCD Transfer Attributes
  598. #define DMA_TCD1_NBYTES_MLNO *(volatile uint32_t *)0x40009028 // TCD Minor Byte Count, Minor Loop Disabled
  599. #define DMA_TCD1_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009028 // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled
  600. #define DMA_TCD1_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009028 // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled
  601. #define DMA_TCD1_SLAST *(volatile int32_t *)0x4000902C // TCD Last Source Address Adjustment
  602. #define DMA_TCD1_DADDR *(volatile void * volatile *)0x40009030 // TCD Destination Address
  603. #define DMA_TCD1_DOFF *(volatile int16_t *)0x40009034 // TCD Signed Destination Address Offset
  604. #define DMA_TCD1_CITER_ELINKYES *(volatile uint16_t *)0x40009036 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled
  605. #define DMA_TCD1_CITER_ELINKNO *(volatile uint16_t *)0x40009036 // ??
  606. #define DMA_TCD1_DLASTSGA *(volatile int32_t *)0x40009038 // TCD Last Destination Address Adjustment/Scatter Gather Address
  607. #define DMA_TCD1_CSR *(volatile uint16_t *)0x4000903C // TCD Control and Status
  608. #define DMA_TCD1_BITER_ELINKYES *(volatile uint16_t *)0x4000903E // TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled
  609. #define DMA_TCD1_BITER_ELINKNO *(volatile uint16_t *)0x4000903E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled
  610. #define DMA_TCD2_SADDR *(volatile const void * volatile *)0x40009040 // TCD Source Address
  611. #define DMA_TCD2_SOFF *(volatile int16_t *)0x40009044 // TCD Signed Source Address Offset
  612. #define DMA_TCD2_ATTR *(volatile uint16_t *)0x40009046 // TCD Transfer Attributes
  613. #define DMA_TCD2_NBYTES_MLNO *(volatile uint32_t *)0x40009048 // TCD Minor Byte Count, Minor Loop Disabled
  614. #define DMA_TCD2_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009048 // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled
  615. #define DMA_TCD2_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009048 // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled
  616. #define DMA_TCD2_SLAST *(volatile int32_t *)0x4000904C // TCD Last Source Address Adjustment
  617. #define DMA_TCD2_DADDR *(volatile void * volatile *)0x40009050 // TCD Destination Address
  618. #define DMA_TCD2_DOFF *(volatile int16_t *)0x40009054 // TCD Signed Destination Address Offset
  619. #define DMA_TCD2_CITER_ELINKYES *(volatile uint16_t *)0x40009056 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled
  620. #define DMA_TCD2_CITER_ELINKNO *(volatile uint16_t *)0x40009056 // ??
  621. #define DMA_TCD2_DLASTSGA *(volatile int32_t *)0x40009058 // TCD Last Destination Address Adjustment/Scatter Gather Address
  622. #define DMA_TCD2_CSR *(volatile uint16_t *)0x4000905C // TCD Control and Status
  623. #define DMA_TCD2_BITER_ELINKYES *(volatile uint16_t *)0x4000905E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Enabled
  624. #define DMA_TCD2_BITER_ELINKNO *(volatile uint16_t *)0x4000905E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled
  625. #define DMA_TCD3_SADDR *(volatile const void * volatile *)0x40009060 // TCD Source Address
  626. #define DMA_TCD3_SOFF *(volatile int16_t *)0x40009064 // TCD Signed Source Address Offset
  627. #define DMA_TCD3_ATTR *(volatile uint16_t *)0x40009066 // TCD Transfer Attributes
  628. #define DMA_TCD3_NBYTES_MLNO *(volatile uint32_t *)0x40009068 // TCD Minor Byte Count, Minor Loop Disabled
  629. #define DMA_TCD3_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009068 // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled
  630. #define DMA_TCD3_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009068 // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled
  631. #define DMA_TCD3_SLAST *(volatile int32_t *)0x4000906C // TCD Last Source Address Adjustment
  632. #define DMA_TCD3_DADDR *(volatile void * volatile *)0x40009070 // TCD Destination Address
  633. #define DMA_TCD3_DOFF *(volatile int16_t *)0x40009074 // TCD Signed Destination Address Offset
  634. #define DMA_TCD3_CITER_ELINKYES *(volatile uint16_t *)0x40009076 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled
  635. #define DMA_TCD3_CITER_ELINKNO *(volatile uint16_t *)0x40009076 // ??
  636. #define DMA_TCD3_DLASTSGA *(volatile int32_t *)0x40009078 // TCD Last Destination Address Adjustment/Scatter Gather Address
  637. #define DMA_TCD3_CSR *(volatile uint16_t *)0x4000907C // TCD Control and Status
  638. #define DMA_TCD3_BITER_ELINKYES *(volatile uint16_t *)0x4000907E // TCD Beginning Minor Loop Link, Major Loop Count ,Channel Linking Enabled
  639. #define DMA_TCD3_BITER_ELINKNO *(volatile uint16_t *)0x4000907E // TCD Beginning Minor Loop Link, Major Loop Count ,Channel Linking Disabled
  640. // Chapter 22: External Watchdog Monitor (EWM)
  641. #define EWM_CTRL *(volatile uint8_t *)0x40061000 // Control Register
  642. #define EWM_SERV *(volatile uint8_t *)0x40061001 // Service Register
  643. #define EWM_CMPL *(volatile uint8_t *)0x40061002 // Compare Low Register
  644. #define EWM_CMPH *(volatile uint8_t *)0x40061003 // Compare High Register
  645. // Chapter 23: Watchdog Timer (WDOG)
  646. #define WDOG_STCTRLH *(volatile uint16_t *)0x40052000 // Watchdog Status and Control Register High
  647. #define WDOG_STCTRLH_DISTESTWDOG (uint16_t)0x4000 // Allows the WDOG's functional test mode to be disabled permanently.
  648. #define WDOG_STCTRLH_BYTESEL(n) (uint16_t)(((n) & 3) << 12) // selects the byte to be tested when the watchdog is in the byte test mode.
  649. #define WDOG_STCTRLH_TESTSEL (uint16_t)0x0800
  650. #define WDOG_STCTRLH_TESTWDOG (uint16_t)0x0400
  651. #define WDOG_STCTRLH_WAITEN (uint16_t)0x0080
  652. #define WDOG_STCTRLH_STOPEN (uint16_t)0x0040
  653. #define WDOG_STCTRLH_DBGEN (uint16_t)0x0020
  654. #define WDOG_STCTRLH_ALLOWUPDATE (uint16_t)0x0010
  655. #define WDOG_STCTRLH_WINEN (uint16_t)0x0008
  656. #define WDOG_STCTRLH_IRQRSTEN (uint16_t)0x0004
  657. #define WDOG_STCTRLH_CLKSRC (uint16_t)0x0002
  658. #define WDOG_STCTRLH_WDOGEN (uint16_t)0x0001
  659. #define WDOG_STCTRLL *(volatile uint16_t *)0x40052002 // Watchdog Status and Control Register Low
  660. #define WDOG_TOVALH *(volatile uint16_t *)0x40052004 // Watchdog Time-out Value Register High
  661. #define WDOG_TOVALL *(volatile uint16_t *)0x40052006 // Watchdog Time-out Value Register Low
  662. #define WDOG_WINH *(volatile uint16_t *)0x40052008 // Watchdog Window Register High
  663. #define WDOG_WINL *(volatile uint16_t *)0x4005200A // Watchdog Window Register Low
  664. #define WDOG_REFRESH *(volatile uint16_t *)0x4005200C // Watchdog Refresh register
  665. #define WDOG_UNLOCK *(volatile uint16_t *)0x4005200E // Watchdog Unlock register
  666. #define WDOG_UNLOCK_SEQ1 (uint16_t)0xC520
  667. #define WDOG_UNLOCK_SEQ2 (uint16_t)0xD928
  668. #define WDOG_TMROUTH *(volatile uint16_t *)0x40052010 // Watchdog Timer Output Register High
  669. #define WDOG_TMROUTL *(volatile uint16_t *)0x40052012 // Watchdog Timer Output Register Low
  670. #define WDOG_RSTCNT *(volatile uint16_t *)0x40052014 // Watchdog Reset Count register
  671. #define WDOG_PRESC *(volatile uint16_t *)0x40052016 // Watchdog Prescaler register
  672. // Chapter 24: Multipurpose Clock Generator (MCG)
  673. #define MCG_C1 *(volatile uint8_t *)0x40064000 // MCG Control 1 Register
  674. #define MCG_C1_IREFSTEN (uint8_t)0x01 // Internal Reference Stop Enable, Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode.
  675. #define MCG_C1_IRCLKEN (uint8_t)0x02 // Internal Reference Clock Enable, Enables the internal reference clock for use as MCGIRCLK.
  676. #define MCG_C1_IREFS (uint8_t)0x04 // Internal Reference Select, Selects the reference clock source for the FLL.
  677. #define MCG_C1_FRDIV(n) (uint8_t)(((n) & 0x07) << 3) // FLL External Reference Divider, Selects the amount to divide down the external reference clock for the FLL
  678. #define MCG_C1_CLKS(n) (uint8_t)(((n) & 0x03) << 6) // Clock Source Select, Selects the clock source for MCGOUTCLK
  679. #define MCG_C2 *(volatile uint8_t *)0x40064001 // MCG Control 2 Register
  680. #define MCG_C2_IRCS (uint8_t)0x01 // Internal Reference Clock Select, Selects between the fast or slow internal reference clock source.
  681. #define MCG_C2_LP (uint8_t)0x02 // Low Power Select, Controls whether the FLL or PLL is disabled in BLPI and BLPE modes.
  682. #define MCG_C2_EREFS (uint8_t)0x04 // External Reference Select, Selects the source for the external reference clock.
  683. #define MCG_C2_HGO0 (uint8_t)0x08 // High Gain Oscillator Select, Controls the crystal oscillator mode of operation
  684. #define MCG_C2_RANGE0(n) (uint8_t)(((n) & 0x03) << 4) // Frequency Range Select, Selects the frequency range for the crystal oscillator
  685. #define MCG_C2_LOCRE0 (uint8_t)0x80 // Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0
  686. #define MCG_C3 *(volatile uint8_t *)0x40064002 // MCG Control 3 Register
  687. #define MCG_C3_SCTRIM(n) (uint8_t)(n) // Slow Internal Reference Clock Trim Setting
  688. #define MCG_C4 *(volatile uint8_t *)0x40064003 // MCG Control 4 Register
  689. #define MCG_C4_SCFTRIM (uint8_t)0x01 // Slow Internal Reference Clock Fine Trim
  690. #define MCG_C4_FCTRIM(n) (uint8_t)(((n) & 0x0F) << 1) // Fast Internal Reference Clock Trim Setting
  691. #define MCG_C4_DRST_DRS(n) (uint8_t)(((n) & 0x03) << 5) // DCO Range Select
  692. #define MCG_C4_DMX32 (uint8_t)0x80 // DCO Maximum Frequency with 32.768 kHz Reference, controls whether the DCO frequency range is narrowed
  693. #define MCG_C5 *(volatile uint8_t *)0x40064004 // MCG Control 5 Register
  694. #define MCG_C5_PRDIV0(n) (uint8_t)((n) & 0x1F) // PLL External Reference Divider
  695. #define MCG_C5_PLLSTEN0 (uint8_t)0x20 // PLL Stop Enable
  696. #define MCG_C5_PLLCLKEN0 (uint8_t)0x40 // PLL Clock Enable
  697. #define MCG_C6 *(volatile uint8_t *)0x40064005 // MCG Control 6 Register
  698. #define MCG_C6_VDIV0(n) (uint8_t)((n) & 0x1F) // VCO 0 Divider
  699. #define MCG_C6_CME0 (uint8_t)0x20 // Clock Monitor Enable
  700. #define MCG_C6_PLLS (uint8_t)0x40 // PLL Select, Controls whether the PLL or FLL output is selected as the MCG source when CLKS[1:0]=00.
  701. #define MCG_C6_LOLIE0 (uint8_t)0x80 // Loss of Lock Interrrupt Enable
  702. #define MCG_S *(volatile uint8_t *)0x40064006 // MCG Status Register
  703. #define MCG_S_IRCST (uint8_t)0x01 // Internal Reference Clock Status
  704. #define MCG_S_OSCINIT0 (uint8_t)0x02 // OSC Initialization, resets to 0, is set to 1 after the initialization cycles of the crystal oscillator
  705. #define MCG_S_CLKST(n) (uint8_t)(((n) & 0x03) << 2) // Clock Mode Status, 0=FLL is selected, 1= Internal ref, 2=External ref, 3=PLL
  706. #define MCG_S_CLKST_MASK (uint8_t)0x0C
  707. #define MCG_S_IREFST (uint8_t)0x10 // Internal Reference Status
  708. #define MCG_S_PLLST (uint8_t)0x20 // PLL Select Status
  709. #define MCG_S_LOCK0 (uint8_t)0x40 // Lock Status, 0=PLL Unlocked, 1=PLL Locked
  710. #define MCG_S_LOLS0 (uint8_t)0x80 // Loss of Lock Status
  711. #define MCG_SC *(volatile uint8_t *)0x40064008 // MCG Status and Control Register
  712. #define MCG_SC_LOCS0 (uint8_t)0x01 // OSC0 Loss of Clock Status
  713. #define MCG_SC_FCRDIV(n) (uint8_t)(((n) & 0x07) << 1) // Fast Clock Internal Reference Divider
  714. #define MCG_SC_FLTPRSRV (uint8_t)0x10 // FLL Filter Preserve Enable
  715. #define MCG_SC_ATMF (uint8_t)0x20 // Automatic Trim Machine Fail Flag
  716. #define MCG_SC_ATMS (uint8_t)0x40 // Automatic Trim Machine Select
  717. #define MCG_SC_ATME (uint8_t)0x80 // Automatic Trim Machine Enable
  718. #define MCG_ATCVH *(volatile uint8_t *)0x4006400A // MCG Auto Trim Compare Value High Register
  719. #define MCG_ATCVL *(volatile uint8_t *)0x4006400B // MCG Auto Trim Compare Value Low Register
  720. #define MCG_C7 *(volatile uint8_t *)0x4006400C // MCG Control 7 Register
  721. #define MCG_C8 *(volatile uint8_t *)0x4006400D // MCG Control 8 Register
  722. // Chapter 25: Oscillator (OSC)
  723. #define OSC0_CR *(volatile uint8_t *)0x40065000 // OSC Control Register
  724. #define OSC_SC16P (uint8_t)0x01 // Oscillator 16 pF Capacitor Load Configure
  725. #define OSC_SC8P (uint8_t)0x02 // Oscillator 8 pF Capacitor Load Configure
  726. #define OSC_SC4P (uint8_t)0x04 // Oscillator 4 pF Capacitor Load Configure
  727. #define OSC_SC2P (uint8_t)0x08 // Oscillator 2 pF Capacitor Load Configure
  728. #define OSC_EREFSTEN (uint8_t)0x20 // External Reference Stop Enable, Controls whether or not the external reference clock (OSCERCLK) remains enabled when MCU enters Stop mode.
  729. #define OSC_ERCLKEN (uint8_t)0x80 // External Reference Enable, Enables external reference clock (OSCERCLK).
  730. // Chapter 27: Flash Memory Controller (FMC)
  731. #define FMC_PFAPR *(volatile uint32_t *)0x4001F000 // Flash Access Protection
  732. #define FMC_PFB0CR *(volatile uint32_t *)0x4001F004 // Flash Control
  733. #define FMC_TAGVDW0S0 *(volatile uint32_t *)0x4001F100 // Cache Tag Storage
  734. #define FMC_TAGVDW0S1 *(volatile uint32_t *)0x4001F104 // Cache Tag Storage
  735. #define FMC_TAGVDW1S0 *(volatile uint32_t *)0x4001F108 // Cache Tag Storage
  736. #define FMC_TAGVDW1S1 *(volatile uint32_t *)0x4001F10C // Cache Tag Storage
  737. #define FMC_TAGVDW2S0 *(volatile uint32_t *)0x4001F110 // Cache Tag Storage
  738. #define FMC_TAGVDW2S1 *(volatile uint32_t *)0x4001F114 // Cache Tag Storage
  739. #define FMC_TAGVDW3S0 *(volatile uint32_t *)0x4001F118 // Cache Tag Storage
  740. #define FMC_TAGVDW3S1 *(volatile uint32_t *)0x4001F11C // Cache Tag Storage
  741. #define FMC_DATAW0S0 *(volatile uint32_t *)0x4001F200 // Cache Data Storage
  742. #define FMC_DATAW0S1 *(volatile uint32_t *)0x4001F204 // Cache Data Storage
  743. #define FMC_DATAW1S0 *(volatile uint32_t *)0x4001F208 // Cache Data Storage
  744. #define FMC_DATAW1S1 *(volatile uint32_t *)0x4001F20C // Cache Data Storage
  745. #define FMC_DATAW2S0 *(volatile uint32_t *)0x4001F210 // Cache Data Storage
  746. #define FMC_DATAW2S1 *(volatile uint32_t *)0x4001F214 // Cache Data Storage
  747. #define FMC_DATAW3S0 *(volatile uint32_t *)0x4001F218 // Cache Data Storage
  748. #define FMC_DATAW3S1 *(volatile uint32_t *)0x4001F21C // Cache Data Storage
  749. // Chapter 28: Flash Memory Module (FTFL)
  750. #define FTFL_FSTAT *(volatile uint8_t *)0x40020000 // Flash Status Register
  751. #define FTFL_FSTAT_CCIF (uint8_t)0x80 // Command Complete Interrupt Flag
  752. #define FTFL_FSTAT_RDCOLERR (uint8_t)0x40 // Flash Read Collision Error Flag
  753. #define FTFL_FSTAT_ACCERR (uint8_t)0x20 // Flash Access Error Flag
  754. #define FTFL_FSTAT_FPVIOL (uint8_t)0x10 // Flash Protection Violation Flag
  755. #define FTFL_FSTAT_MGSTAT0 (uint8_t)0x01 // Memory Controller Command Completion Status Flag
  756. #define FTFL_FCNFG *(volatile uint8_t *)0x40020001 // Flash Configuration Register
  757. #define FTFL_FCNFG_CCIE (uint8_t)0x80 // Command Complete Interrupt Enable
  758. #define FTFL_FCNFG_RDCOLLIE (uint8_t)0x40 // Read Collision Error Interrupt Enable
  759. #define FTFL_FCNFG_ERSAREQ (uint8_t)0x20 // Erase All Request
  760. #define FTFL_FCNFG_ERSSUSP (uint8_t)0x10 // Erase Suspend
  761. #define FTFL_FCNFG_PFLSH (uint8_t)0x04 // Flash memory configuration
  762. #define FTFL_FCNFG_RAMRDY (uint8_t)0x02 // RAM Ready
  763. #define FTFL_FCNFG_EEERDY (uint8_t)0x01 // EEPROM Ready
  764. #define FTFL_FSEC *(const uint8_t *)0x40020002 // Flash Security Register
  765. #define FTFL_FOPT *(const uint8_t *)0x40020003 // Flash Option Register
  766. #define FTFL_FCCOB3 *(volatile uint8_t *)0x40020004 // Flash Common Command Object Registers
  767. #define FTFL_FCCOB2 *(volatile uint8_t *)0x40020005
  768. #define FTFL_FCCOB1 *(volatile uint8_t *)0x40020006
  769. #define FTFL_FCCOB0 *(volatile uint8_t *)0x40020007
  770. #define FTFL_FCCOB7 *(volatile uint8_t *)0x40020008
  771. #define FTFL_FCCOB6 *(volatile uint8_t *)0x40020009
  772. #define FTFL_FCCOB5 *(volatile uint8_t *)0x4002000A
  773. #define FTFL_FCCOB4 *(volatile uint8_t *)0x4002000B
  774. #define FTFL_FCCOBB *(volatile uint8_t *)0x4002000C
  775. #define FTFL_FCCOBA *(volatile uint8_t *)0x4002000D
  776. #define FTFL_FCCOB9 *(volatile uint8_t *)0x4002000E
  777. #define FTFL_FCCOB8 *(volatile uint8_t *)0x4002000F
  778. #define FTFL_FPROT3 *(volatile uint8_t *)0x40020010 // Program Flash Protection Registers
  779. #define FTFL_FPROT2 *(volatile uint8_t *)0x40020011 // Program Flash Protection Registers
  780. #define FTFL_FPROT1 *(volatile uint8_t *)0x40020012 // Program Flash Protection Registers
  781. #define FTFL_FPROT0 *(volatile uint8_t *)0x40020013 // Program Flash Protection Registers
  782. #define FTFL_FEPROT *(volatile uint8_t *)0x40020016 // EEPROM Protection Register
  783. #define FTFL_FDPROT *(volatile uint8_t *)0x40020017 // Data Flash Protection Register
  784. // Chapter 30: Cyclic Redundancy Check (CRC)
  785. #define CRC_CRC *(volatile uint32_t *)0x40032000 // CRC Data register
  786. #define CRC_GPOLY *(volatile uint32_t *)0x40032004 // CRC Polynomial register
  787. #define CRC_CTRL *(volatile uint32_t *)0x40032008 // CRC Control register
  788. // Chapter 31: Analog-to-Digital Converter (ADC)
  789. #define ADC0_SC1A *(volatile uint32_t *)0x4003B000 // ADC status and control registers 1
  790. #define ADC0_SC1B *(volatile uint32_t *)0x4003B004 // ADC status and control registers 1
  791. #define ADC_SC1_COCO (uint32_t)0x80 // Conversion complete flag
  792. #define ADC_SC1_AIEN (uint32_t)0x40 // Interrupt enable
  793. #define ADC_SC1_DIFF (uint32_t)0x20 // Differential mode enable
  794. #define ADC_SC1_ADCH(n) (uint32_t)((n) & 0x1F) // Input channel select
  795. #define ADC0_CFG1 *(volatile uint32_t *)0x4003B008 // ADC configuration register 1
  796. #define ADC_CFG1_ADLPC (uint32_t)0x80 // Low-power configuration
  797. #define ADC_CFG1_ADIV(n) (uint32_t)(((n) & 3) << 5) // Clock divide select, 0=direct, 1=div2, 2=div4, 3=div8
  798. #define ADC_CFG1_ADLSMP (uint32_t)0x10 // Sample time configuration, 0=Short, 1=Long
  799. #define ADC_CFG1_MODE(n) (uint32_t)(((n) & 3) << 2) // Conversion mode, 0=8 bit, 1=12 bit, 2=10 bit, 3=16 bit
  800. #define ADC_CFG1_ADICLK(n) (uint32_t)(((n) & 3) << 0) // Input clock, 0=bus, 1=bus/2, 2=OSCERCLK, 3=async
  801. #define ADC0_CFG2 *(volatile uint32_t *)0x4003B00C // Configuration register 2
  802. #define ADC_CFG2_MUXSEL (uint32_t)0x10 // 0=a channels, 1=b channels
  803. #define ADC_CFG2_ADACKEN (uint32_t)0x08 // async clock enable
  804. #define ADC_CFG2_ADHSC (uint32_t)0x04 // High speed configuration
  805. #define ADC_CFG2_ADLSTS(n) (uint32_t)(((n) & 3) << 0) // Sample time, 0=24 cycles, 1=12 cycles, 2=6 cycles, 3=2 cycles
  806. #define ADC0_RA *(volatile uint32_t *)0x4003B010 // ADC data result register
  807. #define ADC0_RB *(volatile uint32_t *)0x4003B014 // ADC data result register
  808. #define ADC0_CV1 *(volatile uint32_t *)0x4003B018 // Compare value registers
  809. #define ADC0_CV2 *(volatile uint32_t *)0x4003B01C // Compare value registers
  810. #define ADC0_SC2 *(volatile uint32_t *)0x4003B020 // Status and control register 2
  811. #define ADC_SC2_ADACT (uint32_t)0x80 // Conversion active
  812. #define ADC_SC2_ADTRG (uint32_t)0x40 // Conversion trigger select, 0=software, 1=hardware
  813. #define ADC_SC2_ACFE (uint32_t)0x20 // Compare function enable
  814. #define ADC_SC2_ACFGT (uint32_t)0x10 // Compare function greater than enable
  815. #define ADC_SC2_ACREN (uint32_t)0x08 // Compare function range enable
  816. #define ADC_SC2_DMAEN (uint32_t)0x04 // DMA enable
  817. #define ADC_SC2_REFSEL(n) (uint32_t)(((n) & 3) << 0) // Voltage reference, 0=vcc/external, 1=1.2 volts
  818. #define ADC0_SC3 *(volatile uint32_t *)0x4003B024 // Status and control register 3
  819. #define ADC_SC3_CAL (uint32_t)0x80 // Calibration, 1=begin, stays set while cal in progress
  820. #define ADC_SC3_CALF (uint32_t)0x40 // Calibration failed flag
  821. #define ADC_SC3_ADCO (uint32_t)0x08 // Continuous conversion enable
  822. #define ADC_SC3_AVGE (uint32_t)0x04 // Hardware average enable
  823. #define ADC_SC3_AVGS(n) (uint32_t)(((n) & 3) << 0) // avg select, 0=4 samples, 1=8 samples, 2=16 samples, 3=32 samples
  824. #define ADC0_OFS *(volatile uint32_t *)0x4003B028 // ADC offset correction register
  825. #define ADC0_PG *(volatile uint32_t *)0x4003B02C // ADC plus-side gain register
  826. #define ADC0_MG *(volatile uint32_t *)0x4003B030 // ADC minus-side gain register
  827. #define ADC0_CLPD *(volatile uint32_t *)0x4003B034 // ADC plus-side general calibration value register
  828. #define ADC0_CLPS *(volatile uint32_t *)0x4003B038 // ADC plus-side general calibration value register
  829. #define ADC0_CLP4 *(volatile uint32_t *)0x4003B03C // ADC plus-side general calibration value register
  830. #define ADC0_CLP3 *(volatile uint32_t *)0x4003B040 // ADC plus-side general calibration value register
  831. #define ADC0_CLP2 *(volatile uint32_t *)0x4003B044 // ADC plus-side general calibration value register
  832. #define ADC0_CLP1 *(volatile uint32_t *)0x4003B048 // ADC plus-side general calibration value register
  833. #define ADC0_CLP0 *(volatile uint32_t *)0x4003B04C // ADC plus-side general calibration value register
  834. #define ADC0_CLMD *(volatile uint32_t *)0x4003B054 // ADC minus-side general calibration value register
  835. #define ADC0_CLMS *(volatile uint32_t *)0x4003B058 // ADC minus-side general calibration value register
  836. #define ADC0_CLM4 *(volatile uint32_t *)0x4003B05C // ADC minus-side general calibration value register
  837. #define ADC0_CLM3 *(volatile uint32_t *)0x4003B060 // ADC minus-side general calibration value register
  838. #define ADC0_CLM2 *(volatile uint32_t *)0x4003B064 // ADC minus-side general calibration value register
  839. #define ADC0_CLM1 *(volatile uint32_t *)0x4003B068 // ADC minus-side general calibration value register
  840. #define ADC0_CLM0 *(volatile uint32_t *)0x4003B06C // ADC minus-side general calibration value register
  841. #define ADC1_SC1A *(volatile uint32_t *)0x400BB000 // ADC status and control registers 1
  842. #define ADC1_SC1B *(volatile uint32_t *)0x400BB004 // ADC status and control registers 1
  843. #define ADC1_CFG1 *(volatile uint32_t *)0x400BB008 // ADC configuration register 1
  844. #define ADC1_CFG2 *(volatile uint32_t *)0x400BB00C // Configuration register 2
  845. #define ADC1_RA *(volatile uint32_t *)0x400BB010 // ADC data result register
  846. #define ADC1_RB *(volatile uint32_t *)0x400BB014 // ADC data result register
  847. #define ADC1_CV1 *(volatile uint32_t *)0x400BB018 // Compare value registers
  848. #define ADC1_CV2 *(volatile uint32_t *)0x400BB01C // Compare value registers
  849. #define ADC1_SC2 *(volatile uint32_t *)0x400BB020 // Status and control register 2
  850. #define ADC1_SC3 *(volatile uint32_t *)0x400BB024 // Status and control register 3
  851. #define ADC1_OFS *(volatile uint32_t *)0x400BB028 // ADC offset correction register
  852. #define ADC1_PG *(volatile uint32_t *)0x400BB02C // ADC plus-side gain register
  853. #define ADC1_MG *(volatile uint32_t *)0x400BB030 // ADC minus-side gain register
  854. #define ADC1_CLPD *(volatile uint32_t *)0x400BB034 // ADC plus-side general calibration value register
  855. #define ADC1_CLPS *(volatile uint32_t *)0x400BB038 // ADC plus-side general calibration value register
  856. #define ADC1_CLP4 *(volatile uint32_t *)0x400BB03C // ADC plus-side general calibration value register
  857. #define ADC1_CLP3 *(volatile uint32_t *)0x400BB040 // ADC plus-side general calibration value register
  858. #define ADC1_CLP2 *(volatile uint32_t *)0x400BB044 // ADC plus-side general calibration value register
  859. #define ADC1_CLP1 *(volatile uint32_t *)0x400BB048 // ADC plus-side general calibration value register
  860. #define ADC1_CLP0 *(volatile uint32_t *)0x400BB04C // ADC plus-side general calibration value register
  861. #define ADC1_CLMD *(volatile uint32_t *)0x400BB054 // ADC minus-side general calibration value register
  862. #define ADC1_CLMS *(volatile uint32_t *)0x400BB058 // ADC minus-side general calibration value register
  863. #define ADC1_CLM4 *(volatile uint32_t *)0x400BB05C // ADC minus-side general calibration value register
  864. #define ADC1_CLM3 *(volatile uint32_t *)0x400BB060 // ADC minus-side general calibration value register
  865. #define ADC1_CLM2 *(volatile uint32_t *)0x400BB064 // ADC minus-side general calibration value register
  866. #define ADC1_CLM1 *(volatile uint32_t *)0x400BB068 // ADC minus-side general calibration value register
  867. #define ADC1_CLM0 *(volatile uint32_t *)0x400BB06C // ADC minus-side general calibration value register
  868. #define DAC0_DAT0L *(volatile uint8_t *)0x400CC000 // DAC Data Low Register
  869. #define DAC0_DATH *(volatile uint8_t *)0x400CC001 // DAC Data High Register
  870. #define DAC0_DAT1L *(volatile uint8_t *)0x400CC002 // DAC Data Low Register
  871. #define DAC0_DAT2L *(volatile uint8_t *)0x400CC004 // DAC Data Low Register
  872. #define DAC0_DAT3L *(volatile uint8_t *)0x400CC006 // DAC Data Low Register
  873. #define DAC0_DAT4L *(volatile uint8_t *)0x400CC008 // DAC Data Low Register
  874. #define DAC0_DAT5L *(volatile uint8_t *)0x400CC00A // DAC Data Low Register
  875. #define DAC0_DAT6L *(volatile uint8_t *)0x400CC00C // DAC Data Low Register
  876. #define DAC0_DAT7L *(volatile uint8_t *)0x400CC00E // DAC Data Low Register
  877. #define DAC0_DAT8L *(volatile uint8_t *)0x400CC010 // DAC Data Low Register
  878. #define DAC0_DAT9L *(volatile uint8_t *)0x400CC012 // DAC Data Low Register
  879. #define DAC0_DAT10L *(volatile uint8_t *)0x400CC014 // DAC Data Low Register
  880. #define DAC0_DAT11L *(volatile uint8_t *)0x400CC016 // DAC Data Low Register
  881. #define DAC0_DAT12L *(volatile uint8_t *)0x400CC018 // DAC Data Low Register
  882. #define DAC0_DAT13L *(volatile uint8_t *)0x400CC01A // DAC Data Low Register
  883. #define DAC0_DAT14L *(volatile uint8_t *)0x400CC01C // DAC Data Low Register
  884. #define DAC0_DAT15L *(volatile uint8_t *)0x400CC01E // DAC Data Low Register
  885. #define DAC0_SR *(volatile uint8_t *)0x400CC020 // DAC Status Register
  886. #define DAC0_C0 *(volatile uint8_t *)0x400CC021 // DAC Control Register
  887. #define DAC_C0_DACEN 0x80 // DAC Enable
  888. #define DAC_C0_DACRFS 0x40 // DAC Reference Select
  889. #define DAC_C0_DACTRGSEL 0x20 // DAC Trigger Select
  890. #define DAC_C0_DACSWTRG 0x10 // DAC Software Trigger
  891. #define DAC_C0_LPEN 0x08 // DAC Low Power Control
  892. #define DAC_C0_DACBWIEN 0x04 // DAC Buffer Watermark Interrupt Enable
  893. #define DAC_C0_DACBTIEN 0x02 // DAC Buffer Read Pointer Top Flag Interrupt Enable
  894. #define DAC_C0_DACBBIEN 0x01 // DAC Buffer Read Pointer Bottom Flag Interrupt Enable
  895. #define DAC0_C1 *(volatile uint8_t *)0x400CC022 // DAC Control Register 1
  896. #define DAC_C1_DMAEN 0x80 // DMA Enable Select
  897. #define DAC_C1_DACBFWM(n) (((n) & 3) << 3) // DAC Buffer Watermark Select
  898. #define DAC_C1_DACBFMD(n) (((n) & 3) << 0) // DAC Buffer Work Mode Select
  899. #define DAC_C1_DACBFEN 0x00 // DAC Buffer Enable
  900. #define DAC0_C2 *(volatile uint8_t *)0x400CC023 // DAC Control Register 2
  901. #define DAC_C2_DACBFRP(n) (((n) & 15) << 4) // DAC Buffer Read Pointer
  902. #define DAC_C2_DACBFUP(n) (((n) & 15) << 0) // DAC Buffer Upper Limit
  903. //#define MCG_C2_RANGE0(n) (uint8_t)(((n) & 0x03) << 4) // Frequency Range Select, Selects the frequency range for the crystal oscillator
  904. //#define MCG_C2_LOCRE0 (uint8_t)0x80 // Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0
  905. // Chapter 32: Comparator (CMP)
  906. #define CMP0_CR0 *(volatile uint8_t *)0x40073000 // CMP Control Register 0
  907. #define CMP0_CR1 *(volatile uint8_t *)0x40073001 // CMP Control Register 1
  908. #define CMP0_FPR *(volatile uint8_t *)0x40073002 // CMP Filter Period Register
  909. #define CMP0_SCR *(volatile uint8_t *)0x40073003 // CMP Status and Control Register
  910. #define CMP0_DACCR *(volatile uint8_t *)0x40073004 // DAC Control Register
  911. #define CMP0_MUXCR *(volatile uint8_t *)0x40073005 // MUX Control Register
  912. #define CMP1_CR0 *(volatile uint8_t *)0x40073008 // CMP Control Register 0
  913. #define CMP1_CR1 *(volatile uint8_t *)0x40073009 // CMP Control Register 1
  914. #define CMP1_FPR *(volatile uint8_t *)0x4007300A // CMP Filter Period Register
  915. #define CMP1_SCR *(volatile uint8_t *)0x4007300B // CMP Status and Control Register
  916. #define CMP1_DACCR *(volatile uint8_t *)0x4007300C // DAC Control Register
  917. #define CMP1_MUXCR *(volatile uint8_t *)0x4007300D // MUX Control Register
  918. // Chapter 33: Voltage Reference (VREFV1)
  919. #define VREF_TRM *(volatile uint8_t *)0x40074000 // VREF Trim Register
  920. #define VREF_SC *(volatile uint8_t *)0x40074001 // VREF Status and Control Register
  921. // Chapter 34: Programmable Delay Block (PDB)
  922. #define PDB0_SC *(volatile uint32_t *)0x40036000 // Status and Control Register
  923. #define PDB_SC_LDMOD(n) (((n) & 3) << 18) // Load Mode Select
  924. #define PDB_SC_PDBEIE 0x00020000 // Sequence Error Interrupt Enable
  925. #define PDB_SC_SWTRIG 0x00010000 // Software Trigger
  926. #define PDB_SC_DMAEN 0x00008000 // DMA Enable
  927. #define PDB_SC_PRESCALER(n) (((n) & 7) << 12) // Prescaler Divider Select
  928. #define PDB_SC_TRGSEL(n) (((n) & 15) << 8) // Trigger Input Source Select
  929. #define PDB_SC_PDBEN 0x00000080 // PDB Enable
  930. #define PDB_SC_PDBIF 0x00000040 // PDB Interrupt Flag
  931. #define PDB_SC_PDBIE 0x00000020 // PDB Interrupt Enable.
  932. #define PDB_SC_MULT(n) (((n) & 3) << 2) // Multiplication Factor
  933. #define PDB_SC_CONT 0x00000002 // Continuous Mode Enable
  934. #define PDB_SC_LDOK 0x00000001 // Load OK
  935. #define PDB0_MOD *(volatile uint32_t *)0x40036004 // Modulus Register
  936. #define PDB0_CNT *(volatile uint32_t *)0x40036008 // Counter Register
  937. #define PDB0_IDLY *(volatile uint32_t *)0x4003600C // Interrupt Delay Register
  938. #define PDB0_CH0C1 *(volatile uint32_t *)0x40036010 // Channel n Control Register 1
  939. #define PDB0_CH0S *(volatile uint32_t *)0x40036014 // Channel n Status Register
  940. #define PDB0_CH0DLY0 *(volatile uint32_t *)0x40036018 // Channel n Delay 0 Register
  941. #define PDB0_CH0DLY1 *(volatile uint32_t *)0x4003601C // Channel n Delay 1 Register
  942. #define PDB0_POEN *(volatile uint32_t *)0x40036190 // Pulse-Out n Enable Register
  943. #define PDB0_PO0DLY *(volatile uint32_t *)0x40036194 // Pulse-Out n Delay Register
  944. #define PDB0_PO1DLY *(volatile uint32_t *)0x40036198 // Pulse-Out n Delay Register
  945. // Chapter 35: FlexTimer Module (FTM)
  946. #define FTM0_SC *(volatile uint32_t *)0x40038000 // Status And Control
  947. #define FTM_SC_TOF 0x80 // Timer Overflow Flag
  948. #define FTM_SC_TOIE 0x40 // Timer Overflow Interrupt Enable
  949. #define FTM_SC_CPWMS 0x20 // Center-Aligned PWM Select
  950. #define FTM_SC_CLKS(n) (((n) & 3) << 3) // Clock Source Selection
  951. #define FTM_SC_PS(n) (((n) & 7) << 0) // Prescale Factor Selection
  952. #define FTM0_CNT *(volatile uint32_t *)0x40038004 // Counter
  953. #define FTM0_MOD *(volatile uint32_t *)0x40038008 // Modulo
  954. #define FTM0_C0SC *(volatile uint32_t *)0x4003800C // Channel 0 Status And Control
  955. #define FTM0_C0V *(volatile uint32_t *)0x40038010 // Channel 0 Value
  956. #define FTM0_C1SC *(volatile uint32_t *)0x40038014 // Channel 1 Status And Control
  957. #define FTM0_C1V *(volatile uint32_t *)0x40038018 // Channel 1 Value
  958. #define FTM0_C2SC *(volatile uint32_t *)0x4003801C // Channel 2 Status And Control
  959. #define FTM0_C2V *(volatile uint32_t *)0x40038020 // Channel 2 Value
  960. #define FTM0_C3SC *(volatile uint32_t *)0x40038024 // Channel 3 Status And Control
  961. #define FTM0_C3V *(volatile uint32_t *)0x40038028 // Channel 3 Value
  962. #define FTM0_C4SC *(volatile uint32_t *)0x4003802C // Channel 4 Status And Control
  963. #define FTM0_C4V *(volatile uint32_t *)0x40038030 // Channel 4 Value
  964. #define FTM0_C5SC *(volatile uint32_t *)0x40038034 // Channel 5 Status And Control
  965. #define FTM0_C5V *(volatile uint32_t *)0x40038038 // Channel 5 Value
  966. #define FTM0_C6SC *(volatile uint32_t *)0x4003803C // Channel 6 Status And Control
  967. #define FTM0_C6V *(volatile uint32_t *)0x40038040 // Channel 6 Value
  968. #define FTM0_C7SC *(volatile uint32_t *)0x40038044 // Channel 7 Status And Control
  969. #define FTM0_C7V *(volatile uint32_t *)0x40038048 // Channel 7 Value
  970. #define FTM0_CNTIN *(volatile uint32_t *)0x4003804C // Counter Initial Value
  971. #define FTM0_STATUS *(volatile uint32_t *)0x40038050 // Capture And Compare Status
  972. #define FTM0_MODE *(volatile uint32_t *)0x40038054 // Features Mode Selection
  973. #define FTM_MODE_FAULTIE 0x80 // Fault Interrupt Enable
  974. #define FTM_MODE_FAULTM(n) (((n) & 3) << 5) // Fault Control Mode
  975. #define FTM_MODE_CAPTEST 0x10 // Capture Test Mode Enable
  976. #define FTM_MODE_PWMSYNC 0x08 // PWM Synchronization Mode
  977. #define FTM_MODE_WPDIS 0x04 // Write Protection Disable
  978. #define FTM_MODE_INIT 0x02 // Initialize The Channels Output
  979. #define FTM_MODE_FTMEN 0x01 // FTM Enable
  980. #define FTM0_SYNC *(volatile uint32_t *)0x40038058 // Synchronization
  981. #define FTM_SYNC_SWSYNC 0x80 //
  982. #define FTM_SYNC_TRIG2 0x40 //
  983. #define FTM_SYNC_TRIG1 0x20 //
  984. #define FTM_SYNC_TRIG0 0x10 //
  985. #define FTM_SYNC_SYNCHOM 0x08 //
  986. #define FTM_SYNC_REINIT 0x04 //
  987. #define FTM_SYNC_CNTMAX 0x02 //
  988. #define FTM_SYNC_CNTMIN 0x01 //
  989. #define FTM0_OUTINIT *(volatile uint32_t *)0x4003805C // Initial State For Channels Output
  990. #define FTM0_OUTMASK *(volatile uint32_t *)0x40038060 // Output Mask
  991. #define FTM0_COMBINE *(volatile uint32_t *)0x40038064 // Function For Linked Channels
  992. #define FTM0_DEADTIME *(volatile uint32_t *)0x40038068 // Deadtime Insertion Control
  993. #define FTM0_EXTTRIG *(volatile uint32_t *)0x4003806C // FTM External Trigger
  994. #define FTM0_POL *(volatile uint32_t *)0x40038070 // Channels Polarity
  995. #define FTM0_FMS *(volatile uint32_t *)0x40038074 // Fault Mode Status
  996. #define FTM0_FILTER *(volatile uint32_t *)0x40038078 // Input Capture Filter Control
  997. #define FTM0_FLTCTRL *(volatile uint32_t *)0x4003807C // Fault Control
  998. #define FTM0_QDCTRL *(volatile uint32_t *)0x40038080 // Quadrature Decoder Control And Status
  999. #define FTM0_CONF *(volatile uint32_t *)0x40038084 // Configuration
  1000. #define FTM0_FLTPOL *(volatile uint32_t *)0x40038088 // FTM Fault Input Polarity
  1001. #define FTM0_SYNCONF *(volatile uint32_t *)0x4003808C // Synchronization Configuration
  1002. #define FTM0_INVCTRL *(volatile uint32_t *)0x40038090 // FTM Inverting Control
  1003. #define FTM0_SWOCTRL *(volatile uint32_t *)0x40038094 // FTM Software Output Control
  1004. #define FTM0_PWMLOAD *(volatile uint32_t *)0x40038098 // FTM PWM Load
  1005. #define FTM1_SC *(volatile uint32_t *)0x40039000 // Status And Control
  1006. #define FTM1_CNT *(volatile uint32_t *)0x40039004 // Counter
  1007. #define FTM1_MOD *(volatile uint32_t *)0x40039008 // Modulo
  1008. #define FTM1_C0SC *(volatile uint32_t *)0x4003900C // Channel 0 Status And Control
  1009. #define FTM1_C0V *(volatile uint32_t *)0x40039010 // Channel 0 Value
  1010. #define FTM1_C1SC *(volatile uint32_t *)0x40039014 // Channel 1 Status And Control
  1011. #define FTM1_C1V *(volatile uint32_t *)0x40039018 // Channel 1 Value
  1012. #define FTM1_CNTIN *(volatile uint32_t *)0x4003904C // Counter Initial Value
  1013. #define FTM1_STATUS *(volatile uint32_t *)0x40039050 // Capture And Compare Status
  1014. #define FTM1_MODE *(volatile uint32_t *)0x40039054 // Features Mode Selection
  1015. #define FTM1_SYNC *(volatile uint32_t *)0x40039058 // Synchronization
  1016. #define FTM1_OUTINIT *(volatile uint32_t *)0x4003905C // Initial State For Channels Output
  1017. #define FTM1_OUTMASK *(volatile uint32_t *)0x40039060 // Output Mask
  1018. #define FTM1_COMBINE *(volatile uint32_t *)0x40039064 // Function For Linked Channels
  1019. #define FTM1_DEADTIME *(volatile uint32_t *)0x40039068 // Deadtime Insertion Control
  1020. #define FTM1_EXTTRIG *(volatile uint32_t *)0x4003906C // FTM External Trigger
  1021. #define FTM1_POL *(volatile uint32_t *)0x40039070 // Channels Polarity
  1022. #define FTM1_FMS *(volatile uint32_t *)0x40039074 // Fault Mode Status
  1023. #define FTM1_FILTER *(volatile uint32_t *)0x40039078 // Input Capture Filter Control
  1024. #define FTM1_FLTCTRL *(volatile uint32_t *)0x4003907C // Fault Control
  1025. #define FTM1_QDCTRL *(volatile uint32_t *)0x40039080 // Quadrature Decoder Control And Status
  1026. #define FTM1_CONF *(volatile uint32_t *)0x40039084 // Configuration
  1027. #define FTM1_FLTPOL *(volatile uint32_t *)0x40039088 // FTM Fault Input Polarity
  1028. #define FTM1_SYNCONF *(volatile uint32_t *)0x4003908C // Synchronization Configuration
  1029. #define FTM1_INVCTRL *(volatile uint32_t *)0x40039090 // FTM Inverting Control
  1030. #define FTM1_SWOCTRL *(volatile uint32_t *)0x40039094 // FTM Software Output Control
  1031. #define FTM1_PWMLOAD *(volatile uint32_t *)0x40039098 // FTM PWM Load
  1032. #define FTM2_SC *(volatile uint32_t *)0x400B8000 // Status And Control
  1033. #define FTM2_CNT *(volatile uint32_t *)0x400B8004 // Counter
  1034. #define FTM2_MOD *(volatile uint32_t *)0x400B8008 // Modulo
  1035. #define FTM2_C0SC *(volatile uint32_t *)0x400B800C // Channel 0 Status And Control
  1036. #define FTM2_C0V *(volatile uint32_t *)0x400B8010 // Channel 0 Value
  1037. #define FTM2_C1SC *(volatile uint32_t *)0x400B8014 // Channel 1 Status And Control
  1038. #define FTM2_C1V *(volatile uint32_t *)0x400B8018 // Channel 1 Value
  1039. #define FTM2_CNTIN *(volatile uint32_t *)0x400B804C // Counter Initial Value
  1040. #define FTM2_STATUS *(volatile uint32_t *)0x400B8050 // Capture And Compare Status
  1041. #define FTM2_MODE *(volatile uint32_t *)0x400B8054 // Features Mode Selection
  1042. #define FTM2_SYNC *(volatile uint32_t *)0x400B8058 // Synchronization
  1043. #define FTM2_OUTINIT *(volatile uint32_t *)0x400B805C // Initial State For Channels Output
  1044. #define FTM2_OUTMASK *(volatile uint32_t *)0x400B8060 // Output Mask
  1045. #define FTM2_COMBINE *(volatile uint32_t *)0x400B8064 // Function For Linked Channels
  1046. #define FTM2_DEADTIME *(volatile uint32_t *)0x400B8068 // Deadtime Insertion Control
  1047. #define FTM2_EXTTRIG *(volatile uint32_t *)0x400B806C // FTM External Trigger
  1048. #define FTM2_POL *(volatile uint32_t *)0x400B8070 // Channels Polarity
  1049. #define FTM2_FMS *(volatile uint32_t *)0x400B8074 // Fault Mode Status
  1050. #define FTM2_FILTER *(volatile uint32_t *)0x400B8078 // Input Capture Filter Control
  1051. #define FTM2_FLTCTRL *(volatile uint32_t *)0x400B807C // Fault Control
  1052. #define FTM2_QDCTRL *(volatile uint32_t *)0x400B8080 // Quadrature Decoder Control And Status
  1053. #define FTM2_CONF *(volatile uint32_t *)0x400B8084 // Configuration
  1054. #define FTM2_FLTPOL *(volatile uint32_t *)0x400B8088 // FTM Fault Input Polarity
  1055. #define FTM2_SYNCONF *(volatile uint32_t *)0x400B808C // Synchronization Configuration
  1056. #define FTM2_INVCTRL *(volatile uint32_t *)0x400B8090 // FTM Inverting Control
  1057. #define FTM2_SWOCTRL *(volatile uint32_t *)0x400B8094 // FTM Software Output Control
  1058. #define FTM2_PWMLOAD *(volatile uint32_t *)0x400B8098 // FTM PWM Load
  1059. // Chapter 36: Periodic Interrupt Timer (PIT)
  1060. #define PIT_MCR *(volatile uint32_t *)0x40037000 // PIT Module Control Register
  1061. #define PIT_LDVAL0 *(volatile uint32_t *)0x40037100 // Timer Load Value Register
  1062. #define PIT_CVAL0 *(volatile uint32_t *)0x40037104 // Current Timer Value Register
  1063. #define PIT_TCTRL0 *(volatile uint32_t *)0x40037108 // Timer Control Register
  1064. #define PIT_TFLG0 *(volatile uint32_t *)0x4003710C // Timer Flag Register
  1065. #define PIT_LDVAL1 *(volatile uint32_t *)0x40037110 // Timer Load Value Register
  1066. #define PIT_CVAL1 *(volatile uint32_t *)0x40037114 // Current Timer Value Register
  1067. #define PIT_TCTRL1 *(volatile uint32_t *)0x40037118 // Timer Control Register
  1068. #define PIT_TFLG1 *(volatile uint32_t *)0x4003711C // Timer Flag Register
  1069. #define PIT_LDVAL2 *(volatile uint32_t *)0x40037120 // Timer Load Value Register
  1070. #define PIT_CVAL2 *(volatile uint32_t *)0x40037124 // Current Timer Value Register
  1071. #define PIT_TCTRL2 *(volatile uint32_t *)0x40037128 // Timer Control Register
  1072. #define PIT_TFLG2 *(volatile uint32_t *)0x4003712C // Timer Flag Register
  1073. #define PIT_LDVAL3 *(volatile uint32_t *)0x40037130 // Timer Load Value Register
  1074. #define PIT_CVAL3 *(volatile uint32_t *)0x40037134 // Current Timer Value Register
  1075. #define PIT_TCTRL3 *(volatile uint32_t *)0x40037138 // Timer Control Register
  1076. #define PIT_TFLG3 *(volatile uint32_t *)0x4003713C // Timer Flag Register
  1077. // Chapter 37: Low-Power Timer (LPTMR)
  1078. #define LPTMR0_CSR *(volatile uint32_t *)0x40040000 // Low Power Timer Control Status Register
  1079. #define LPTMR0_PSR *(volatile uint32_t *)0x40040004 // Low Power Timer Prescale Register
  1080. #define LPTMR0_CMR *(volatile uint32_t *)0x40040008 // Low Power Timer Compare Register
  1081. #define LPTMR0_CNR *(volatile uint32_t *)0x4004000C // Low Power Timer Counter Register
  1082. // Chapter 38: Carrier Modulator Transmitter (CMT)
  1083. #define CMT_CGH1 *(volatile uint8_t *)0x40062000 // CMT Carrier Generator High Data Register 1
  1084. #define CMT_CGL1 *(volatile uint8_t *)0x40062001 // CMT Carrier Generator Low Data Register 1
  1085. #define CMT_CGH2 *(volatile uint8_t *)0x40062002 // CMT Carrier Generator High Data Register 2
  1086. #define CMT_CGL2 *(volatile uint8_t *)0x40062003 // CMT Carrier Generator Low Data Register 2
  1087. #define CMT_OC *(volatile uint8_t *)0x40062004 // CMT Output Control Register
  1088. #define CMT_MSC *(volatile uint8_t *)0x40062005 // CMT Modulator Status and Control Register
  1089. #define CMT_CMD1 *(volatile uint8_t *)0x40062006 // CMT Modulator Data Register Mark High
  1090. #define CMT_CMD2 *(volatile uint8_t *)0x40062007 // CMT Modulator Data Register Mark Low
  1091. #define CMT_CMD3 *(volatile uint8_t *)0x40062008 // CMT Modulator Data Register Space High
  1092. #define CMT_CMD4 *(volatile uint8_t *)0x40062009 // CMT Modulator Data Register Space Low
  1093. #define CMT_PPS *(volatile uint8_t *)0x4006200A // CMT Primary Prescaler Register
  1094. #define CMT_DMA *(volatile uint8_t *)0x4006200B // CMT Direct Memory Access Register
  1095. // Chapter 39: Real Time Clock (RTC)
  1096. #define RTC_TSR *(volatile uint32_t *)0x4003D000 // RTC Time Seconds Register
  1097. #define RTC_TPR *(volatile uint32_t *)0x4003D004 // RTC Time Prescaler Register
  1098. #define RTC_TAR *(volatile uint32_t *)0x4003D008 // RTC Time Alarm Register
  1099. #define RTC_TCR *(volatile uint32_t *)0x4003D00C // RTC Time Compensation Register
  1100. #define RTC_TCR_CIC(n) (((n) & 255) << 24) // Compensation Interval Counter
  1101. #define RTC_TCR_TCV(n) (((n) & 255) << 16) // Time Compensation Value
  1102. #define RTC_TCR_CIR(n) (((n) & 255) << 8) // Compensation Interval Register
  1103. #define RTC_TCR_TCR(n) (((n) & 255) << 0) // Time Compensation Register
  1104. #define RTC_CR *(volatile uint32_t *)0x4003D010 // RTC Control Register
  1105. #define RTC_CR_SC2P (uint32_t)0x00002000 //
  1106. #define RTC_CR_SC4P (uint32_t)0x00001000 //
  1107. #define RTC_CR_SC8P (uint32_t)0x00000800 //
  1108. #define RTC_CR_SC16P (uint32_t)0x00000400 //
  1109. #define RTC_CR_CLKO (uint32_t)0x00000200 //
  1110. #define RTC_CR_OSCE (uint32_t)0x00000100 //
  1111. #define RTC_CR_UM (uint32_t)0x00000008 //
  1112. #define RTC_CR_SUP (uint32_t)0x00000004 //
  1113. #define RTC_CR_WPE (uint32_t)0x00000002 //
  1114. #define RTC_CR_SWR (uint32_t)0x00000001 //
  1115. #define RTC_SR *(volatile uint32_t *)0x4003D014 // RTC Status Register
  1116. #define RTC_SR_TCE (uint32_t)0x00000010 //
  1117. #define RTC_SR_TAF (uint32_t)0x00000004 //
  1118. #define RTC_SR_TOF (uint32_t)0x00000002 //
  1119. #define RTC_SR_TIF (uint32_t)0x00000001 //
  1120. #define RTC_LR *(volatile uint32_t *)0x4003D018 // RTC Lock Register
  1121. #define RTC_IER *(volatile uint32_t *)0x4003D01C // RTC Interrupt Enable Register
  1122. #define RTC_WAR *(volatile uint32_t *)0x4003D800 // RTC Write Access Register
  1123. #define RTC_RAR *(volatile uint32_t *)0x4003D804 // RTC Read Access Register
  1124. // Chapter 40: Universal Serial Bus OTG Controller (USBOTG)
  1125. #define USB0_PERID *(const uint8_t *)0x40072000 // Peripheral ID register
  1126. #define USB0_IDCOMP *(const uint8_t *)0x40072004 // Peripheral ID Complement register
  1127. #define USB0_REV *(const uint8_t *)0x40072008 // Peripheral Revision register
  1128. #define USB0_ADDINFO *(volatile uint8_t *)0x4007200C // Peripheral Additional Info register
  1129. #define USB0_OTGISTAT *(volatile uint8_t *)0x40072010 // OTG Interrupt Status register
  1130. #define USB_OTGISTAT_IDCHG (uint8_t)0x80 //
  1131. #define USB_OTGISTAT_ONEMSEC (uint8_t)0x40 //
  1132. #define USB_OTGISTAT_LINE_STATE_CHG (uint8_t)0x20 //
  1133. #define USB_OTGISTAT_SESSVLDCHG (uint8_t)0x08 //
  1134. #define USB_OTGISTAT_B_SESS_CHG (uint8_t)0x04 //
  1135. #define USB_OTGISTAT_AVBUSCHG (uint8_t)0x01 //
  1136. #define USB0_OTGICR *(volatile uint8_t *)0x40072014 // OTG Interrupt Control Register
  1137. #define USB_OTGICR_IDEN (uint8_t)0x80 //
  1138. #define USB_OTGICR_ONEMSECEN (uint8_t)0x40 //
  1139. #define USB_OTGICR_LINESTATEEN (uint8_t)0x20 //
  1140. #define USB_OTGICR_SESSVLDEN (uint8_t)0x08 //
  1141. #define USB_OTGICR_BSESSEN (uint8_t)0x04 //
  1142. #define USB_OTGICR_AVBUSEN (uint8_t)0x01 //
  1143. #define USB0_OTGSTAT *(volatile uint8_t *)0x40072018 // OTG Status register
  1144. #define USB_OTGSTAT_ID (uint8_t)0x80 //
  1145. #define USB_OTGSTAT_ONEMSECEN (uint8_t)0x40 //
  1146. #define USB_OTGSTAT_LINESTATESTABLE (uint8_t)0x20 //
  1147. #define USB_OTGSTAT_SESS_VLD (uint8_t)0x08 //
  1148. #define USB_OTGSTAT_BSESSEND (uint8_t)0x04 //
  1149. #define USB_OTGSTAT_AVBUSVLD (uint8_t)0x01 //
  1150. #define USB0_OTGCTL *(volatile uint8_t *)0x4007201C // OTG Control Register
  1151. #define USB_OTGCTL_DPHIGH (uint8_t)0x80 //
  1152. #define USB_OTGCTL_DPLOW (uint8_t)0x20 //
  1153. #define USB_OTGCTL_DMLOW (uint8_t)0x10 //
  1154. #define USB_OTGCTL_OTGEN (uint8_t)0x04 //
  1155. #define USB0_ISTAT *(volatile uint8_t *)0x40072080 // Interrupt Status Register
  1156. #define USB_ISTAT_STALL (uint8_t)0x80 //
  1157. #define USB_ISTAT_ATTACH (uint8_t)0x40 //
  1158. #define USB_ISTAT_RESUME (uint8_t)0x20 //
  1159. #define USB_ISTAT_SLEEP (uint8_t)0x10 //
  1160. #define USB_ISTAT_TOKDNE (uint8_t)0x08 //
  1161. #define USB_ISTAT_SOFTOK (uint8_t)0x04 //
  1162. #define USB_ISTAT_ERROR (uint8_t)0x02 //
  1163. #define USB_ISTAT_USBRST (uint8_t)0x01 //
  1164. #define USB0_INTEN *(volatile uint8_t *)0x40072084 // Interrupt Enable Register
  1165. #define USB_INTEN_STALLEN (uint8_t)0x80 //
  1166. #define USB_INTEN_ATTACHEN (uint8_t)0x40 //
  1167. #define USB_INTEN_RESUMEEN (uint8_t)0x20 //
  1168. #define USB_INTEN_SLEEPEN (uint8_t)0x10 //
  1169. #define USB_INTEN_TOKDNEEN (uint8_t)0x08 //
  1170. #define USB_INTEN_SOFTOKEN (uint8_t)0x04 //
  1171. #define USB_INTEN_ERROREN (uint8_t)0x02 //
  1172. #define USB_INTEN_USBRSTEN (uint8_t)0x01 //
  1173. #define USB0_ERRSTAT *(volatile uint8_t *)0x40072088 // Error Interrupt Status Register
  1174. #define USB_ERRSTAT_BTSERR (uint8_t)0x80 //
  1175. #define USB_ERRSTAT_DMAERR (uint8_t)0x20 //
  1176. #define USB_ERRSTAT_BTOERR (uint8_t)0x10 //
  1177. #define USB_ERRSTAT_DFN8 (uint8_t)0x08 //
  1178. #define USB_ERRSTAT_CRC16 (uint8_t)0x04 //
  1179. #define USB_ERRSTAT_CRC5EOF (uint8_t)0x02 //
  1180. #define USB_ERRSTAT_PIDERR (uint8_t)0x01 //
  1181. #define USB0_ERREN *(volatile uint8_t *)0x4007208C // Error Interrupt Enable Register
  1182. #define USB_ERREN_BTSERREN (uint8_t)0x80 //
  1183. #define USB_ERREN_DMAERREN (uint8_t)0x20 //
  1184. #define USB_ERREN_BTOERREN (uint8_t)0x10 //
  1185. #define USB_ERREN_DFN8EN (uint8_t)0x08 //
  1186. #define USB_ERREN_CRC16EN (uint8_t)0x04 //
  1187. #define USB_ERREN_CRC5EOFEN (uint8_t)0x02 //
  1188. #define USB_ERREN_PIDERREN (uint8_t)0x01 //
  1189. #define USB0_STAT *(volatile uint8_t *)0x40072090 // Status Register
  1190. #define USB_STAT_TX (uint8_t)0x08 //
  1191. #define USB_STAT_ODD (uint8_t)0x04 //
  1192. #define USB_STAT_ENDP(n) (uint8_t)((n) >> 4) //
  1193. #define USB0_CTL *(volatile uint8_t *)0x40072094 // Control Register
  1194. #define USB_CTL_JSTATE (uint8_t)0x80 //
  1195. #define USB_CTL_SE0 (uint8_t)0x40 //
  1196. #define USB_CTL_TXSUSPENDTOKENBUSY (uint8_t)0x20 //
  1197. #define USB_CTL_RESET (uint8_t)0x10 //
  1198. #define USB_CTL_HOSTMODEEN (uint8_t)0x08 //
  1199. #define USB_CTL_RESUME (uint8_t)0x04 //
  1200. #define USB_CTL_ODDRST (uint8_t)0x02 //
  1201. #define USB_CTL_USBENSOFEN (uint8_t)0x01 //
  1202. #define USB0_ADDR *(volatile uint8_t *)0x40072098 // Address Register
  1203. #define USB0_BDTPAGE1 *(volatile uint8_t *)0x4007209C // BDT Page Register 1
  1204. #define USB0_FRMNUML *(volatile uint8_t *)0x400720A0 // Frame Number Register Low
  1205. #define USB0_FRMNUMH *(volatile uint8_t *)0x400720A4 // Frame Number Register High
  1206. #define USB0_TOKEN *(volatile uint8_t *)0x400720A8 // Token Register
  1207. #define USB0_SOFTHLD *(volatile uint8_t *)0x400720AC // SOF Threshold Register
  1208. #define USB0_BDTPAGE2 *(volatile uint8_t *)0x400720B0 // BDT Page Register 2
  1209. #define USB0_BDTPAGE3 *(volatile uint8_t *)0x400720B4 // BDT Page Register 3
  1210. #define USB0_ENDPT0 *(volatile uint8_t *)0x400720C0 // Endpoint Control Register
  1211. #define USB_ENDPT_HOSTWOHUB (uint8_t)0x80 // host only, enable low speed
  1212. #define USB_ENDPT_RETRYDIS (uint8_t)0x40 // host only, set to disable NAK retry
  1213. #define USB_ENDPT_EPCTLDIS (uint8_t)0x10 // 0=control, 1=bulk, interrupt, isync
  1214. #define USB_ENDPT_EPRXEN (uint8_t)0x08 // enables the endpoint for RX transfers.
  1215. #define USB_ENDPT_EPTXEN (uint8_t)0x04 // enables the endpoint for TX transfers.
  1216. #define USB_ENDPT_EPSTALL (uint8_t)0x02 // set to stall endpoint
  1217. #define USB_ENDPT_EPHSHK (uint8_t)0x01 // enable handshaking during a transaction, generally set unless Isochronous
  1218. #define USB0_ENDPT1 *(volatile uint8_t *)0x400720C4 // Endpoint Control Register
  1219. #define USB0_ENDPT2 *(volatile uint8_t *)0x400720C8 // Endpoint Control Register
  1220. #define USB0_ENDPT3 *(volatile uint8_t *)0x400720CC // Endpoint Control Register
  1221. #define USB0_ENDPT4 *(volatile uint8_t *)0x400720D0 // Endpoint Control Register
  1222. #define USB0_ENDPT5 *(volatile uint8_t *)0x400720D4 // Endpoint Control Register
  1223. #define USB0_ENDPT6 *(volatile uint8_t *)0x400720D8 // Endpoint Control Register
  1224. #define USB0_ENDPT7 *(volatile uint8_t *)0x400720DC // Endpoint Control Register
  1225. #define USB0_ENDPT8 *(volatile uint8_t *)0x400720E0 // Endpoint Control Register
  1226. #define USB0_ENDPT9 *(volatile uint8_t *)0x400720E4 // Endpoint Control Register
  1227. #define USB0_ENDPT10 *(volatile uint8_t *)0x400720E8 // Endpoint Control Register
  1228. #define USB0_ENDPT11 *(volatile uint8_t *)0x400720EC // Endpoint Control Register
  1229. #define USB0_ENDPT12 *(volatile uint8_t *)0x400720F0 // Endpoint Control Register
  1230. #define USB0_ENDPT13 *(volatile uint8_t *)0x400720F4 // Endpoint Control Register
  1231. #define USB0_ENDPT14 *(volatile uint8_t *)0x400720F8 // Endpoint Control Register
  1232. #define USB0_ENDPT15 *(volatile uint8_t *)0x400720FC // Endpoint Control Register
  1233. #define USB0_USBCTRL *(volatile uint8_t *)0x40072100 // USB Control Register
  1234. #define USB_USBCTRL_SUSP (uint8_t)0x80 // Places the USB transceiver into the suspend state.
  1235. #define USB_USBCTRL_PDE (uint8_t)0x40 // Enables the weak pulldowns on the USB transceiver.
  1236. #define USB0_OBSERVE *(volatile uint8_t *)0x40072104 // USB OTG Observe Register
  1237. #define USB_OBSERVE_DPPU (uint8_t)0x80 //
  1238. #define USB_OBSERVE_DPPD (uint8_t)0x40 //
  1239. #define USB_OBSERVE_DMPD (uint8_t)0x10 //
  1240. #define USB0_CONTROL *(volatile uint8_t *)0x40072108 // USB OTG Control Register
  1241. #define USB_CONTROL_DPPULLUPNONOTG (uint8_t)0x10 // Provides control of the DP PULLUP in the USB OTG module, if USB is configured in non-OTG device mode.
  1242. #define USB0_USBTRC0 *(volatile uint8_t *)0x4007210C // USB Transceiver Control Register 0
  1243. #define USB_USBTRC_USBRESET (uint8_t)0x80 //
  1244. #define USB_USBTRC_USBRESMEN (uint8_t)0x20 //
  1245. #define USB_USBTRC_SYNC_DET (uint8_t)0x02 //
  1246. #define USB_USBTRC_USB_RESUME_INT (uint8_t)0x01 //
  1247. #define USB0_USBFRMADJUST *(volatile uint8_t *)0x40072114 // Frame Adjust Register
  1248. // Chapter 41: USB Device Charger Detection Module (USBDCD)
  1249. #define USBDCD_CONTROL *(volatile uint32_t *)0x40035000 // Control register
  1250. #define USBDCD_CLOCK *(volatile uint32_t *)0x40035004 // Clock register
  1251. #define USBDCD_STATUS *(volatile uint32_t *)0x40035008 // Status register
  1252. #define USBDCD_TIMER0 *(volatile uint32_t *)0x40035010 // TIMER0 register
  1253. #define USBDCD_TIMER1 *(volatile uint32_t *)0x40035014 // TIMER1 register
  1254. #define USBDCD_TIMER2 *(volatile uint32_t *)0x40035018 // TIMER2 register
  1255. // Chapter 43: SPI (DSPI)
  1256. #define SPI0_MCR *(volatile uint32_t *)0x4002C000 // DSPI Module Configuration Register
  1257. #define SPI_MCR_MSTR (uint32_t)0x80000000 // Master/Slave Mode Select
  1258. #define SPI_MCR_CONT_SCKE (uint32_t)0x40000000 //
  1259. #define SPI_MCR_DCONF(n) (((n) & 3) << 28) //
  1260. #define SPI_MCR_FRZ (uint32_t)0x08000000 //
  1261. #define SPI_MCR_MTFE (uint32_t)0x04000000 //
  1262. #define SPI_MCR_ROOE (uint32_t)0x01000000 //
  1263. #define SPI_MCR_PCSIS(n) (((n) & 0x1F) << 16) //
  1264. #define SPI_MCR_DOZE (uint32_t)0x00008000 //
  1265. #define SPI_MCR_MDIS (uint32_t)0x00004000 //
  1266. #define SPI_MCR_DIS_TXF (uint32_t)0x00002000 //
  1267. #define SPI_MCR_DIS_RXF (uint32_t)0x00001000 //
  1268. #define SPI_MCR_CLR_TXF (uint32_t)0x00000800 //
  1269. #define SPI_MCR_CLR_RXF (uint32_t)0x00000400 //
  1270. #define SPI_MCR_SMPL_PT(n) (((n) & 3) << 8) //
  1271. #define SPI_MCR_HALT (uint32_t)0x00000001 //
  1272. #define SPI0_TCR *(volatile uint32_t *)0x4002C008 // DSPI Transfer Count Register
  1273. #define SPI0_CTAR0 *(volatile uint32_t *)0x4002C00C // DSPI Clock and Transfer Attributes Register, In Master Mode
  1274. #define SPI_CTAR_DBR (uint32_t)0x80000000 // Double Baud Rate
  1275. #define SPI_CTAR_FMSZ(n) (((n) & 15) << 27) // Frame Size (+1)
  1276. #define SPI_CTAR_CPOL (uint32_t)0x04000000 // Clock Polarity
  1277. #define SPI_CTAR_CPHA (uint32_t)0x02000000 // Clock Phase
  1278. #define SPI_CTAR_LSBFE (uint32_t)0x01000000 // LSB First
  1279. #define SPI_CTAR_PCSSCK(n) (((n) & 3) << 22) // PCS to SCK Delay Prescaler
  1280. #define SPI_CTAR_PASC(n) (((n) & 3) << 20) // After SCK Delay Prescaler
  1281. #define SPI_CTAR_PDT(n) (((n) & 3) << 18) // Delay after Transfer Prescaler
  1282. #define SPI_CTAR_PBR(n) (((n) & 3) << 16) // Baud Rate Prescaler
  1283. #define SPI_CTAR_CSSCK(n) (((n) & 15) << 12) // PCS to SCK Delay Scaler
  1284. #define SPI_CTAR_ASC(n) (((n) & 15) << 8) // After SCK Delay Scaler
  1285. #define SPI_CTAR_DT(n) (((n) & 15) << 4) // Delay After Transfer Scaler
  1286. #define SPI_CTAR_BR(n) (((n) & 15) << 0) // Baud Rate Scaler
  1287. #define SPI0_CTAR0_SLAVE *(volatile uint32_t *)0x4002C00C // DSPI Clock and Transfer Attributes Register, In Slave Mode
  1288. #define SPI0_CTAR1 *(volatile uint32_t *)0x4002C010 // DSPI Clock and Transfer Attributes Register, In Master Mode
  1289. #define SPI0_SR *(volatile uint32_t *)0x4002C02C // DSPI Status Register
  1290. #define SPI_SR_TCF (uint32_t)0x80000000 // Transfer Complete Flag
  1291. #define SPI_SR_TXRXS (uint32_t)0x40000000 // TX and RX Status
  1292. #define SPI_SR_EOQF (uint32_t)0x10000000 // End of Queue Flag
  1293. #define SPI_SR_TFUF (uint32_t)0x08000000 // Transmit FIFO Underflow Flag
  1294. #define SPI_SR_TFFF (uint32_t)0x02000000 // Transmit FIFO Fill Flag
  1295. #define SPI_SR_RFOF (uint32_t)0x00080000 // Receive FIFO Overflow Flag
  1296. #define SPI_SR_RFDF (uint32_t)0x00020000 // Receive FIFO Drain Flag
  1297. #define SPI0_RSER *(volatile uint32_t *)0x4002C030 // DSPI DMA/Interrupt Request Select and Enable Register
  1298. #define SPI_RSER_TCF_RE (uint32_t)0x80000000 // Transmission Complete Request Enable
  1299. #define SPI_RSER_EOQF_RE (uint32_t)0x10000000 // DSPI Finished Request Request Enable
  1300. #define SPI_RSER_TFUF_RE (uint32_t)0x08000000 // Transmit FIFO Underflow Request Enable
  1301. #define SPI_RSER_TFFF_RE (uint32_t)0x02000000 // Transmit FIFO Fill Request Enable
  1302. #define SPI_RSER_TFFF_DIRS (uint32_t)0x01000000 // Transmit FIFO FIll Dma or Interrupt Request Select
  1303. #define SPI_RSER_RFOF_RE (uint32_t)0x00080000 // Receive FIFO Overflow Request Enable
  1304. #define SPI_RSER_RFDF_RE (uint32_t)0x00020000 // Receive FIFO Drain Request Enable
  1305. #define SPI_RSER_RFDF_DIRS (uint32_t)0x00010000 // Receive FIFO Drain DMA or Interrupt Request Select
  1306. #define SPI0_PUSHR *(volatile uint32_t *)0x4002C034 // DSPI PUSH TX FIFO Register In Master Mode
  1307. #define SPI_PUSHR_CONT (uint32_t)0x80000000 //
  1308. #define SPI_PUSHR_CTAS(n) (((n) & 7) << 28) //
  1309. #define SPI_PUSHR_EOQ (uint32_t)0x08000000 //
  1310. #define SPI_PUSHR_CTCNT (uint32_t)0x04000000 //
  1311. #define SPI_PUSHR_PCS(n) (((n) & 31) << 16) //
  1312. #define SPI0_PUSHR_SLAVE *(volatile uint32_t *)0x4002C034 // DSPI PUSH TX FIFO Register In Slave Mode
  1313. #define SPI0_POPR *(volatile uint32_t *)0x4002C038 // DSPI POP RX FIFO Register
  1314. #define SPI0_TXFR0 *(volatile uint32_t *)0x4002C03C // DSPI Transmit FIFO Registers
  1315. #define SPI0_TXFR1 *(volatile uint32_t *)0x4002C040 // DSPI Transmit FIFO Registers
  1316. #define SPI0_TXFR2 *(volatile uint32_t *)0x4002C044 // DSPI Transmit FIFO Registers
  1317. #define SPI0_TXFR3 *(volatile uint32_t *)0x4002C048 // DSPI Transmit FIFO Registers
  1318. #define SPI0_RXFR0 *(volatile uint32_t *)0x4002C07C // DSPI Receive FIFO Registers
  1319. #define SPI0_RXFR1 *(volatile uint32_t *)0x4002C080 // DSPI Receive FIFO Registers
  1320. #define SPI0_RXFR2 *(volatile uint32_t *)0x4002C084 // DSPI Receive FIFO Registers
  1321. #define SPI0_RXFR3 *(volatile uint32_t *)0x4002C088 // DSPI Receive FIFO Registers
  1322. typedef struct {
  1323. volatile uint32_t MCR; // 0
  1324. volatile uint32_t unused1;// 4
  1325. volatile uint32_t TCR; // 8
  1326. volatile uint32_t CTAR0; // c
  1327. volatile uint32_t CTAR1; // 10
  1328. volatile uint32_t CTAR2; // 14
  1329. volatile uint32_t CTAR3; // 18
  1330. volatile uint32_t CTAR4; // 1c
  1331. volatile uint32_t CTAR5; // 20
  1332. volatile uint32_t CTAR6; // 24
  1333. volatile uint32_t CTAR7; // 28
  1334. volatile uint32_t SR; // 2c
  1335. volatile uint32_t RSER; // 30
  1336. volatile uint32_t PUSHR; // 34
  1337. volatile uint32_t POPR; // 38
  1338. volatile uint32_t TXFR[16]; // 3c
  1339. volatile uint32_t RXFR[16]; // 7c
  1340. } SPI_t;
  1341. #define SPI0 (*(SPI_t *)0x4002C000)
  1342. // Chapter 44: Inter-Integrated Circuit (I2C)
  1343. #define I2C0_A1 *(volatile uint8_t *)0x40066000 // I2C Address Register 1
  1344. #define I2C0_F *(volatile uint8_t *)0x40066001 // I2C Frequency Divider register
  1345. #define I2C0_C1 *(volatile uint8_t *)0x40066002 // I2C Control Register 1
  1346. #define I2C_C1_IICEN (uint8_t)0x80 // I2C Enable
  1347. #define I2C_C1_IICIE (uint8_t)0x40 // I2C Interrupt Enable
  1348. #define I2C_C1_MST (uint8_t)0x20 // Master Mode Select
  1349. #define I2C_C1_TX (uint8_t)0x10 // Transmit Mode Select
  1350. #define I2C_C1_TXAK (uint8_t)0x08 // Transmit Acknowledge Enable
  1351. #define I2C_C1_RSTA (uint8_t)0x04 // Repeat START
  1352. #define I2C_C1_WUEN (uint8_t)0x02 // Wakeup Enable
  1353. #define I2C_C1_DMAEN (uint8_t)0x01 // DMA Enable
  1354. #define I2C0_S *(volatile uint8_t *)0x40066003 // I2C Status register
  1355. #define I2C_S_TCF (uint8_t)0x80 // Transfer Complete Flag
  1356. #define I2C_S_IAAS (uint8_t)0x40 // Addressed As A Slave
  1357. #define I2C_S_BUSY (uint8_t)0x20 // Bus Busy
  1358. #define I2C_S_ARBL (uint8_t)0x10 // Arbitration Lost
  1359. #define I2C_S_RAM (uint8_t)0x08 // Range Address Match
  1360. #define I2C_S_SRW (uint8_t)0x04 // Slave Read/Write
  1361. #define I2C_S_IICIF (uint8_t)0x02 // Interrupt Flag
  1362. #define I2C_S_RXAK (uint8_t)0x01 // Receive Acknowledge
  1363. #define I2C0_D *(volatile uint8_t *)0x40066004 // I2C Data I/O register
  1364. #define I2C0_C2 *(volatile uint8_t *)0x40066005 // I2C Control Register 2
  1365. #define I2C_C2_GCAEN (uint8_t)0x80 // General Call Address Enable
  1366. #define I2C_C2_ADEXT (uint8_t)0x40 // Address Extension
  1367. #define I2C_C2_HDRS (uint8_t)0x20 // High Drive Select
  1368. #define I2C_C2_SBRC (uint8_t)0x10 // Slave Baud Rate Control
  1369. #define I2C_C2_RMEN (uint8_t)0x08 // Range Address Matching Enable
  1370. #define I2C_C2_AD(n) ((n) & 7) // Slave Address, upper 3 bits
  1371. #define I2C0_FLT *(volatile uint8_t *)0x40066006 // I2C Programmable Input Glitch Filter register
  1372. #define I2C0_RA *(volatile uint8_t *)0x40066007 // I2C Range Address register
  1373. #define I2C0_SMB *(volatile uint8_t *)0x40066008 // I2C SMBus Control and Status register
  1374. #define I2C0_A2 *(volatile uint8_t *)0x40066009 // I2C Address Register 2
  1375. #define I2C0_SLTH *(volatile uint8_t *)0x4006600A // I2C SCL Low Timeout Register High
  1376. #define I2C0_SLTL *(volatile uint8_t *)0x4006600B // I2C SCL Low Timeout Register Low
  1377. // Chapter 45: Universal Asynchronous Receiver/Transmitter (UART)
  1378. #define UART0_BDH *(volatile uint8_t *)0x4006A000 // UART Baud Rate Registers: High
  1379. #define UART0_BDL *(volatile uint8_t *)0x4006A001 // UART Baud Rate Registers: Low
  1380. #define UART0_C1 *(volatile uint8_t *)0x4006A002 // UART Control Register 1
  1381. #define UART_C1_LOOPS (uint8_t)0x80 // When LOOPS is set, the RxD pin is disconnected from the UART and the transmitter output is internally connected to the receiver input
  1382. #define UART_C1_UARTSWAI (uint8_t)0x40 // UART Stops in Wait Mode
  1383. #define UART_C1_RSRC (uint8_t)0x20 // When LOOPS is set, the RSRC field determines the source for the receiver shift register input
  1384. #define UART_C1_M (uint8_t)0x10 // 9-bit or 8-bit Mode Select
  1385. #define UART_C1_WAKE (uint8_t)0x08 // Determines which condition wakes the UART
  1386. #define UART_C1_ILT (uint8_t)0x04 // Idle Line Type Select
  1387. #define UART_C1_PE (uint8_t)0x02 // Parity Enable
  1388. #define UART_C1_PT (uint8_t)0x01 // Parity Type, 0=even, 1=odd
  1389. #define UART0_C2 *(volatile uint8_t *)0x4006A003 // UART Control Register 2
  1390. #define UART_C2_TIE (uint8_t)0x80 // Transmitter Interrupt or DMA Transfer Enable.
  1391. #define UART_C2_TCIE (uint8_t)0x40 // Transmission Complete Interrupt Enable
  1392. #define UART_C2_RIE (uint8_t)0x20 // Receiver Full Interrupt or DMA Transfer Enable
  1393. #define UART_C2_ILIE (uint8_t)0x10 // Idle Line Interrupt Enable
  1394. #define UART_C2_TE (uint8_t)0x08 // Transmitter Enable
  1395. #define UART_C2_RE (uint8_t)0x04 // Receiver Enable
  1396. #define UART_C2_RWU (uint8_t)0x02 // Receiver Wakeup Control
  1397. #define UART_C2_SBK (uint8_t)0x01 // Send Break
  1398. #define UART0_S1 *(volatile uint8_t *)0x4006A004 // UART Status Register 1
  1399. #define UART_S1_TDRE (uint8_t)0x80 // Transmit Data Register Empty Flag
  1400. #define UART_S1_TC (uint8_t)0x40 // Transmit Complete Flag
  1401. #define UART_S1_RDRF (uint8_t)0x20 // Receive Data Register Full Flag
  1402. #define UART_S1_IDLE (uint8_t)0x10 // Idle Line Flag
  1403. #define UART_S1_OR (uint8_t)0x08 // Receiver Overrun Flag
  1404. #define UART_S1_NF (uint8_t)0x04 // Noise Flag
  1405. #define UART_S1_FE (uint8_t)0x02 // Framing Error Flag
  1406. #define UART_S1_PF (uint8_t)0x01 // Parity Error Flag
  1407. #define UART0_S2 *(volatile uint8_t *)0x4006A005 // UART Status Register 2
  1408. #define UART0_C3 *(volatile uint8_t *)0x4006A006 // UART Control Register 3
  1409. #define UART0_D *(volatile uint8_t *)0x4006A007 // UART Data Register
  1410. #define UART0_MA1 *(volatile uint8_t *)0x4006A008 // UART Match Address Registers 1
  1411. #define UART0_MA2 *(volatile uint8_t *)0x4006A009 // UART Match Address Registers 2
  1412. #define UART0_C4 *(volatile uint8_t *)0x4006A00A // UART Control Register 4
  1413. #define UART0_C5 *(volatile uint8_t *)0x4006A00B // UART Control Register 5
  1414. #define UART0_ED *(volatile uint8_t *)0x4006A00C // UART Extended Data Register
  1415. #define UART0_MODEM *(volatile uint8_t *)0x4006A00D // UART Modem Register
  1416. #define UART0_IR *(volatile uint8_t *)0x4006A00E // UART Infrared Register
  1417. #define UART0_PFIFO *(volatile uint8_t *)0x4006A010 // UART FIFO Parameters
  1418. #define UART_PFIFO_TXFE (uint8_t)0x80
  1419. #define UART_PFIFO_RXFE (uint8_t)0x08
  1420. #define UART0_CFIFO *(volatile uint8_t *)0x4006A011 // UART FIFO Control Register
  1421. #define UART_CFIFO_TXFLUSH (uint8_t)0x80 //
  1422. #define UART_CFIFO_RXFLUSH (uint8_t)0x40 //
  1423. #define UART_CFIFO_RXOFE (uint8_t)0x04 //
  1424. #define UART_CFIFO_TXOFE (uint8_t)0x02 //
  1425. #define UART_CFIFO_RXUFE (uint8_t)0x01 //
  1426. #define UART0_SFIFO *(volatile uint8_t *)0x4006A012 // UART FIFO Status Register
  1427. #define UART_SFIFO_TXEMPT (uint8_t)0x80
  1428. #define UART_SFIFO_RXEMPT (uint8_t)0x40
  1429. #define UART_SFIFO_RXOF (uint8_t)0x04
  1430. #define UART_SFIFO_TXOF (uint8_t)0x02
  1431. #define UART_SFIFO_RXUF (uint8_t)0x01
  1432. #define UART0_TWFIFO *(volatile uint8_t *)0x4006A013 // UART FIFO Transmit Watermark
  1433. #define UART0_TCFIFO *(volatile uint8_t *)0x4006A014 // UART FIFO Transmit Count
  1434. #define UART0_RWFIFO *(volatile uint8_t *)0x4006A015 // UART FIFO Receive Watermark
  1435. #define UART0_RCFIFO *(volatile uint8_t *)0x4006A016 // UART FIFO Receive Count
  1436. #define UART0_C7816 *(volatile uint8_t *)0x4006A018 // UART 7816 Control Register
  1437. #define UART0_IE7816 *(volatile uint8_t *)0x4006A019 // UART 7816 Interrupt Enable Register
  1438. #define UART0_IS7816 *(volatile uint8_t *)0x4006A01A // UART 7816 Interrupt Status Register
  1439. #define UART0_WP7816T0 *(volatile uint8_t *)0x4006A01B // UART 7816 Wait Parameter Register
  1440. #define UART0_WP7816T1 *(volatile uint8_t *)0x4006A01B // UART 7816 Wait Parameter Register
  1441. #define UART0_WN7816 *(volatile uint8_t *)0x4006A01C // UART 7816 Wait N Register
  1442. #define UART0_WF7816 *(volatile uint8_t *)0x4006A01D // UART 7816 Wait FD Register
  1443. #define UART0_ET7816 *(volatile uint8_t *)0x4006A01E // UART 7816 Error Threshold Register
  1444. #define UART0_TL7816 *(volatile uint8_t *)0x4006A01F // UART 7816 Transmit Length Register
  1445. #define UART0_C6 *(volatile uint8_t *)0x4006A021 // UART CEA709.1-B Control Register 6
  1446. #define UART0_PCTH *(volatile uint8_t *)0x4006A022 // UART CEA709.1-B Packet Cycle Time Counter High
  1447. #define UART0_PCTL *(volatile uint8_t *)0x4006A023 // UART CEA709.1-B Packet Cycle Time Counter Low
  1448. #define UART0_B1T *(volatile uint8_t *)0x4006A024 // UART CEA709.1-B Beta1 Timer
  1449. #define UART0_SDTH *(volatile uint8_t *)0x4006A025 // UART CEA709.1-B Secondary Delay Timer High
  1450. #define UART0_SDTL *(volatile uint8_t *)0x4006A026 // UART CEA709.1-B Secondary Delay Timer Low
  1451. #define UART0_PRE *(volatile uint8_t *)0x4006A027 // UART CEA709.1-B Preamble
  1452. #define UART0_TPL *(volatile uint8_t *)0x4006A028 // UART CEA709.1-B Transmit Packet Length
  1453. #define UART0_IE *(volatile uint8_t *)0x4006A029 // UART CEA709.1-B Interrupt Enable Register
  1454. #define UART0_WB *(volatile uint8_t *)0x4006A02A // UART CEA709.1-B WBASE
  1455. #define UART0_S3 *(volatile uint8_t *)0x4006A02B // UART CEA709.1-B Status Register
  1456. #define UART0_S4 *(volatile uint8_t *)0x4006A02C // UART CEA709.1-B Status Register
  1457. #define UART0_RPL *(volatile uint8_t *)0x4006A02D // UART CEA709.1-B Received Packet Length
  1458. #define UART0_RPREL *(volatile uint8_t *)0x4006A02E // UART CEA709.1-B Received Preamble Length
  1459. #define UART0_CPW *(volatile uint8_t *)0x4006A02F // UART CEA709.1-B Collision Pulse Width
  1460. #define UART0_RIDT *(volatile uint8_t *)0x4006A030 // UART CEA709.1-B Receive Indeterminate Time
  1461. #define UART0_TIDT *(volatile uint8_t *)0x4006A031 // UART CEA709.1-B Transmit Indeterminate Time
  1462. #define UART1_BDH *(volatile uint8_t *)0x4006B000 // UART Baud Rate Registers: High
  1463. #define UART1_BDL *(volatile uint8_t *)0x4006B001 // UART Baud Rate Registers: Low
  1464. #define UART1_C1 *(volatile uint8_t *)0x4006B002 // UART Control Register 1
  1465. #define UART1_C2 *(volatile uint8_t *)0x4006B003 // UART Control Register 2
  1466. #define UART1_S1 *(volatile uint8_t *)0x4006B004 // UART Status Register 1
  1467. #define UART1_S2 *(volatile uint8_t *)0x4006B005 // UART Status Register 2
  1468. #define UART1_C3 *(volatile uint8_t *)0x4006B006 // UART Control Register 3
  1469. #define UART1_D *(volatile uint8_t *)0x4006B007 // UART Data Register
  1470. #define UART1_MA1 *(volatile uint8_t *)0x4006B008 // UART Match Address Registers 1
  1471. #define UART1_MA2 *(volatile uint8_t *)0x4006B009 // UART Match Address Registers 2
  1472. #define UART1_C4 *(volatile uint8_t *)0x4006B00A // UART Control Register 4
  1473. #define UART1_C5 *(volatile uint8_t *)0x4006B00B // UART Control Register 5
  1474. #define UART1_ED *(volatile uint8_t *)0x4006B00C // UART Extended Data Register
  1475. #define UART1_MODEM *(volatile uint8_t *)0x4006B00D // UART Modem Register
  1476. #define UART1_IR *(volatile uint8_t *)0x4006B00E // UART Infrared Register
  1477. #define UART1_PFIFO *(volatile uint8_t *)0x4006B010 // UART FIFO Parameters
  1478. #define UART1_CFIFO *(volatile uint8_t *)0x4006B011 // UART FIFO Control Register
  1479. #define UART1_SFIFO *(volatile uint8_t *)0x4006B012 // UART FIFO Status Register
  1480. #define UART1_TWFIFO *(volatile uint8_t *)0x4006B013 // UART FIFO Transmit Watermark
  1481. #define UART1_TCFIFO *(volatile uint8_t *)0x4006B014 // UART FIFO Transmit Count
  1482. #define UART1_RWFIFO *(volatile uint8_t *)0x4006B015 // UART FIFO Receive Watermark
  1483. #define UART1_RCFIFO *(volatile uint8_t *)0x4006B016 // UART FIFO Receive Count
  1484. #define UART1_C7816 *(volatile uint8_t *)0x4006B018 // UART 7816 Control Register
  1485. #define UART1_IE7816 *(volatile uint8_t *)0x4006B019 // UART 7816 Interrupt Enable Register
  1486. #define UART1_IS7816 *(volatile uint8_t *)0x4006B01A // UART 7816 Interrupt Status Register
  1487. #define UART1_WP7816T0 *(volatile uint8_t *)0x4006B01B // UART 7816 Wait Parameter Register
  1488. #define UART1_WP7816T1 *(volatile uint8_t *)0x4006B01B // UART 7816 Wait Parameter Register
  1489. #define UART1_WN7816 *(volatile uint8_t *)0x4006B01C // UART 7816 Wait N Register
  1490. #define UART1_WF7816 *(volatile uint8_t *)0x4006B01D // UART 7816 Wait FD Register
  1491. #define UART1_ET7816 *(volatile uint8_t *)0x4006B01E // UART 7816 Error Threshold Register
  1492. #define UART1_TL7816 *(volatile uint8_t *)0x4006B01F // UART 7816 Transmit Length Register
  1493. #define UART1_C6 *(volatile uint8_t *)0x4006B021 // UART CEA709.1-B Control Register 6
  1494. #define UART1_PCTH *(volatile uint8_t *)0x4006B022 // UART CEA709.1-B Packet Cycle Time Counter High
  1495. #define UART1_PCTL *(volatile uint8_t *)0x4006B023 // UART CEA709.1-B Packet Cycle Time Counter Low
  1496. #define UART1_B1T *(volatile uint8_t *)0x4006B024 // UART CEA709.1-B Beta1 Timer
  1497. #define UART1_SDTH *(volatile uint8_t *)0x4006B025 // UART CEA709.1-B Secondary Delay Timer High
  1498. #define UART1_SDTL *(volatile uint8_t *)0x4006B026 // UART CEA709.1-B Secondary Delay Timer Low
  1499. #define UART1_PRE *(volatile uint8_t *)0x4006B027 // UART CEA709.1-B Preamble
  1500. #define UART1_TPL *(volatile uint8_t *)0x4006B028 // UART CEA709.1-B Transmit Packet Length
  1501. #define UART1_IE *(volatile uint8_t *)0x4006B029 // UART CEA709.1-B Interrupt Enable Register
  1502. #define UART1_WB *(volatile uint8_t *)0x4006B02A // UART CEA709.1-B WBASE
  1503. #define UART1_S3 *(volatile uint8_t *)0x4006B02B // UART CEA709.1-B Status Register
  1504. #define UART1_S4 *(volatile uint8_t *)0x4006B02C // UART CEA709.1-B Status Register
  1505. #define UART1_RPL *(volatile uint8_t *)0x4006B02D // UART CEA709.1-B Received Packet Length
  1506. #define UART1_RPREL *(volatile uint8_t *)0x4006B02E // UART CEA709.1-B Received Preamble Length
  1507. #define UART1_CPW *(volatile uint8_t *)0x4006B02F // UART CEA709.1-B Collision Pulse Width
  1508. #define UART1_RIDT *(volatile uint8_t *)0x4006B030 // UART CEA709.1-B Receive Indeterminate Time
  1509. #define UART1_TIDT *(volatile uint8_t *)0x4006B031 // UART CEA709.1-B Transmit Indeterminate Time
  1510. #define UART2_BDH *(volatile uint8_t *)0x4006C000 // UART Baud Rate Registers: High
  1511. #define UART2_BDL *(volatile uint8_t *)0x4006C001 // UART Baud Rate Registers: Low
  1512. #define UART2_C1 *(volatile uint8_t *)0x4006C002 // UART Control Register 1
  1513. #define UART2_C2 *(volatile uint8_t *)0x4006C003 // UART Control Register 2
  1514. #define UART2_S1 *(volatile uint8_t *)0x4006C004 // UART Status Register 1
  1515. #define UART2_S2 *(volatile uint8_t *)0x4006C005 // UART Status Register 2
  1516. #define UART2_C3 *(volatile uint8_t *)0x4006C006 // UART Control Register 3
  1517. #define UART2_D *(volatile uint8_t *)0x4006C007 // UART Data Register
  1518. #define UART2_MA1 *(volatile uint8_t *)0x4006C008 // UART Match Address Registers 1
  1519. #define UART2_MA2 *(volatile uint8_t *)0x4006C009 // UART Match Address Registers 2
  1520. #define UART2_C4 *(volatile uint8_t *)0x4006C00A // UART Control Register 4
  1521. #define UART2_C5 *(volatile uint8_t *)0x4006C00B // UART Control Register 5
  1522. #define UART2_ED *(volatile uint8_t *)0x4006C00C // UART Extended Data Register
  1523. #define UART2_MODEM *(volatile uint8_t *)0x4006C00D // UART Modem Register
  1524. #define UART2_IR *(volatile uint8_t *)0x4006C00E // UART Infrared Register
  1525. #define UART2_PFIFO *(volatile uint8_t *)0x4006C010 // UART FIFO Parameters
  1526. #define UART2_CFIFO *(volatile uint8_t *)0x4006C011 // UART FIFO Control Register
  1527. #define UART2_SFIFO *(volatile uint8_t *)0x4006C012 // UART FIFO Status Register
  1528. #define UART2_TWFIFO *(volatile uint8_t *)0x4006C013 // UART FIFO Transmit Watermark
  1529. #define UART2_TCFIFO *(volatile uint8_t *)0x4006C014 // UART FIFO Transmit Count
  1530. #define UART2_RWFIFO *(volatile uint8_t *)0x4006C015 // UART FIFO Receive Watermark
  1531. #define UART2_RCFIFO *(volatile uint8_t *)0x4006C016 // UART FIFO Receive Count
  1532. #define UART2_C7816 *(volatile uint8_t *)0x4006C018 // UART 7816 Control Register
  1533. #define UART2_IE7816 *(volatile uint8_t *)0x4006C019 // UART 7816 Interrupt Enable Register
  1534. #define UART2_IS7816 *(volatile uint8_t *)0x4006C01A // UART 7816 Interrupt Status Register
  1535. #define UART2_WP7816T0 *(volatile uint8_t *)0x4006C01B // UART 7816 Wait Parameter Register
  1536. #define UART2_WP7816T1 *(volatile uint8_t *)0x4006C01B // UART 7816 Wait Parameter Register
  1537. #define UART2_WN7816 *(volatile uint8_t *)0x4006C01C // UART 7816 Wait N Register
  1538. #define UART2_WF7816 *(volatile uint8_t *)0x4006C01D // UART 7816 Wait FD Register
  1539. #define UART2_ET7816 *(volatile uint8_t *)0x4006C01E // UART 7816 Error Threshold Register
  1540. #define UART2_TL7816 *(volatile uint8_t *)0x4006C01F // UART 7816 Transmit Length Register
  1541. #define UART2_C6 *(volatile uint8_t *)0x4006C021 // UART CEA709.1-B Control Register 6
  1542. #define UART2_PCTH *(volatile uint8_t *)0x4006C022 // UART CEA709.1-B Packet Cycle Time Counter High
  1543. #define UART2_PCTL *(volatile uint8_t *)0x4006C023 // UART CEA709.1-B Packet Cycle Time Counter Low
  1544. #define UART2_B1T *(volatile uint8_t *)0x4006C024 // UART CEA709.1-B Beta1 Timer
  1545. #define UART2_SDTH *(volatile uint8_t *)0x4006C025 // UART CEA709.1-B Secondary Delay Timer High
  1546. #define UART2_SDTL *(volatile uint8_t *)0x4006C026 // UART CEA709.1-B Secondary Delay Timer Low
  1547. #define UART2_PRE *(volatile uint8_t *)0x4006C027 // UART CEA709.1-B Preamble
  1548. #define UART2_TPL *(volatile uint8_t *)0x4006C028 // UART CEA709.1-B Transmit Packet Length
  1549. #define UART2_IE *(volatile uint8_t *)0x4006C029 // UART CEA709.1-B Interrupt Enable Register
  1550. #define UART2_WB *(volatile uint8_t *)0x4006C02A // UART CEA709.1-B WBASE
  1551. #define UART2_S3 *(volatile uint8_t *)0x4006C02B // UART CEA709.1-B Status Register
  1552. #define UART2_S4 *(volatile uint8_t *)0x4006C02C // UART CEA709.1-B Status Register
  1553. #define UART2_RPL *(volatile uint8_t *)0x4006C02D // UART CEA709.1-B Received Packet Length
  1554. #define UART2_RPREL *(volatile uint8_t *)0x4006C02E // UART CEA709.1-B Received Preamble Length
  1555. #define UART2_CPW *(volatile uint8_t *)0x4006C02F // UART CEA709.1-B Collision Pulse Width
  1556. #define UART2_RIDT *(volatile uint8_t *)0x4006C030 // UART CEA709.1-B Receive Indeterminate Time
  1557. #define UART2_TIDT *(volatile uint8_t *)0x4006C031 // UART CEA709.1-B Transmit Indeterminate Time
  1558. // Chapter 46: Synchronous Audio Interface (SAI)
  1559. #define I2S0_TCSR *(volatile uint32_t *)0x4002F000 // SAI Transmit Control Register
  1560. #define I2S_TCSR_TE (uint32_t)0x80000000 // Transmitter Enable
  1561. #define I2S_TCSR_STOPE (uint32_t)0x40000000 // Transmitter Enable in Stop mode
  1562. #define I2S_TCSR_DBGE (uint32_t)0x20000000 // Transmitter Enable in Debug mode
  1563. #define I2S_TCSR_BCE (uint32_t)0x10000000 // Bit Clock Enable
  1564. #define I2S_TCSR_FR (uint32_t)0x02000000 // FIFO Reset
  1565. #define I2S_TCSR_SR (uint32_t)0x01000000 // Software Reset
  1566. #define I2S_TCSR_WSF (uint32_t)0x00100000 // Word Start Flag
  1567. #define I2S_TCSR_SEF (uint32_t)0x00080000 // Sync Error Flag
  1568. #define I2S_TCSR_FEF (uint32_t)0x00040000 // FIFO Error Flag (underrun)
  1569. #define I2S_TCSR_FWF (uint32_t)0x00020000 // FIFO Warning Flag (empty)
  1570. #define I2S_TCSR_FRF (uint32_t)0x00010000 // FIFO Request Flag (Data Ready)
  1571. #define I2S_TCSR_WSIE (uint32_t)0x00001000 // Word Start Interrupt Enable
  1572. #define I2S_TCSR_SEIE (uint32_t)0x00000800 // Sync Error Interrupt Enable
  1573. #define I2S_TCSR_FEIE (uint32_t)0x00000400 // FIFO Error Interrupt Enable
  1574. #define I2S_TCSR_FWIE (uint32_t)0x00000200 // FIFO Warning Interrupt Enable
  1575. #define I2S_TCSR_FRIE (uint32_t)0x00000100 // FIFO Request Interrupt Enable
  1576. #define I2S_TCSR_FWDE (uint32_t)0x00000002 // FIFO Warning DMA Enable
  1577. #define I2S_TCSR_FRDE (uint32_t)0x00000001 // FIFO Request DMA Enable
  1578. #define I2S0_TCR1 *(volatile uint32_t *)0x4002F004 // SAI Transmit Configuration 1 Register
  1579. #define I2S_TCR1_TFW(n) ((uint32_t)n & 0x03) // Transmit FIFO watermark
  1580. #define I2S0_TCR2 *(volatile uint32_t *)0x4002F008 // SAI Transmit Configuration 2 Register
  1581. #define I2S_TCR2_DIV(n) ((uint32_t)n & 0xff) // Bit clock divide by (DIV+1)*2
  1582. #define I2S_TCR2_BCD ((uint32_t)1<<24) // Bit clock direction
  1583. #define I2S_TCR2_BCP ((uint32_t)1<<25) // Bit clock polarity
  1584. #define I2S_TCR2_MSEL(n) ((uint32_t)(n & 3)<<26) // MCLK select, 0=bus clock, 1=I2S0_MCLK
  1585. #define I2S_TCR2_BCI ((uint32_t)1<<28) // Bit clock input
  1586. #define I2S_TCR2_BCS ((uint32_t)1<<29) // Bit clock swap
  1587. #define I2S_TCR2_SYNC(n) ((uint32_t)(n & 3)<<30) // 0=async 1=sync with receiver
  1588. #define I2S0_TCR3 *(volatile uint32_t *)0x4002F00C // SAI Transmit Configuration 3 Register
  1589. #define I2S_TCR3_WDFL(n) ((uint32_t)n & 0x0f) // word flag configuration
  1590. #define I2S_TCR3_TCE ((uint32_t)0x10000) // transmit channel enable
  1591. #define I2S0_TCR4 *(volatile uint32_t *)0x4002F010 // SAI Transmit Configuration 4 Register
  1592. #define I2S_TCR4_FSD ((uint32_t)1) // Frame Sync Direction
  1593. #define I2S_TCR4_FSP ((uint32_t)2) // Frame Sync Polarity
  1594. #define I2S_TCR4_FSE ((uint32_t)8) // Frame Sync Early
  1595. #define I2S_TCR4_MF ((uint32_t)0x10) // MSB First
  1596. #define I2S_TCR4_SYWD(n) ((uint32_t)(n & 0x1f)<<8) // Sync Width
  1597. #define I2S_TCR4_FRSZ(n) ((uint32_t)(n & 0x0f)<<16) // Frame Size
  1598. #define I2S0_TCR5 *(volatile uint32_t *)0x4002F014 // SAI Transmit Configuration 5 Register
  1599. #define I2S_TCR5_FBT(n) ((uint32_t)(n & 0x1f)<<8) // First Bit Shifted
  1600. #define I2S_TCR5_W0W(n) ((uint32_t)(n & 0x1f)<<16) // Word 0 Width
  1601. #define I2S_TCR5_WNW(n) ((uint32_t)(n & 0x1f)<<24) // Word N Width
  1602. #define I2S0_TDR0 *(volatile uint32_t *)0x4002F020 // SAI Transmit Data Register
  1603. #define I2S0_TFR0 *(volatile uint32_t *)0x4002F040 // SAI Transmit FIFO Register
  1604. #define I2S_TFR_RFP(n) ((uint32_t)n & 7) // read FIFO pointer
  1605. #define I2S_TFR_WFP(n) ((uint32_t)(n & 7)<<16) // write FIFO pointer
  1606. #define I2S0_TMR *(volatile uint32_t *)0x4002F060 // SAI Transmit Mask Register
  1607. #define I2S_TMR_TWM(n) ((uint32_t)n & 0xFFFFFFFF)
  1608. #define I2S0_RCSR *(volatile uint32_t *)0x4002F080 // SAI Receive Control Register
  1609. #define I2S_RCSR_RE (uint32_t)0x80000000 // Receiver Enable
  1610. #define I2S_RCSR_STOPE (uint32_t)0x40000000 // Receiver Enable in Stop mode
  1611. #define I2S_RCSR_DBGE (uint32_t)0x20000000 // Receiver Enable in Debug mode
  1612. #define I2S_RCSR_BCE (uint32_t)0x10000000 // Bit Clock Enable
  1613. #define I2S_RCSR_FR (uint32_t)0x02000000 // FIFO Reset
  1614. #define I2S_RCSR_SR (uint32_t)0x01000000 // Software Reset
  1615. #define I2S_RCSR_WSF (uint32_t)0x00100000 // Word Start Flag
  1616. #define I2S_RCSR_SEF (uint32_t)0x00080000 // Sync Error Flag
  1617. #define I2S_RCSR_FEF (uint32_t)0x00040000 // FIFO Error Flag (underrun)
  1618. #define I2S_RCSR_FWF (uint32_t)0x00020000 // FIFO Warning Flag (empty)
  1619. #define I2S_RCSR_FRF (uint32_t)0x00010000 // FIFO Request Flag (Data Ready)
  1620. #define I2S_RCSR_WSIE (uint32_t)0x00001000 // Word Start Interrupt Enable
  1621. #define I2S_RCSR_SEIE (uint32_t)0x00000800 // Sync Error Interrupt Enable
  1622. #define I2S_RCSR_FEIE (uint32_t)0x00000400 // FIFO Error Interrupt Enable
  1623. #define I2S_RCSR_FWIE (uint32_t)0x00000200 // FIFO Warning Interrupt Enable
  1624. #define I2S_RCSR_FRIE (uint32_t)0x00000100 // FIFO Request Interrupt Enable
  1625. #define I2S_RCSR_FWDE (uint32_t)0x00000002 // FIFO Warning DMA Enable
  1626. #define I2S_RCSR_FRDE (uint32_t)0x00000001 // FIFO Request DMA Enable
  1627. #define I2S0_RCR1 *(volatile uint32_t *)0x4002F084 // SAI Receive Configuration 1 Register
  1628. #define I2S_RCR1_RFW(n) ((uint32_t)n & 0x03) // Receive FIFO watermark
  1629. #define I2S0_RCR2 *(volatile uint32_t *)0x4002F088 // SAI Receive Configuration 2 Register
  1630. #define I2S_RCR2_DIV(n) ((uint32_t)n & 0xff) // Bit clock divide by (DIV+1)*2
  1631. #define I2S_RCR2_BCD ((uint32_t)1<<24) // Bit clock direction
  1632. #define I2S_RCR2_BCP ((uint32_t)1<<25) // Bit clock polarity
  1633. #define I2S_RCR2_MSEL(n) ((uint32_t)(n & 3)<<26) // MCLK select, 0=bus clock, 1=I2S0_MCLK
  1634. #define I2S_RCR2_BCI ((uint32_t)1<<28) // Bit clock input
  1635. #define I2S_RCR2_BCS ((uint32_t)1<<29) // Bit clock swap
  1636. #define I2S_RCR2_SYNC(n) ((uint32_t)(n & 3)<<30) // 0=async 1=sync with receiver
  1637. #define I2S0_RCR3 *(volatile uint32_t *)0x4002F08C // SAI Receive Configuration 3 Register
  1638. #define I2S_RCR3_WDFL(n) ((uint32_t)n & 0x0f) // word flag configuration
  1639. #define I2S_RCR3_RCE ((uint32_t)0x10000) // receive channel enable
  1640. #define I2S0_RCR4 *(volatile uint32_t *)0x4002F090 // SAI Receive Configuration 4 Register
  1641. #define I2S_RCR4_FSD ((uint32_t)1) // Frame Sync Direction
  1642. #define I2S_RCR4_FSP ((uint32_t)2) // Frame Sync Polarity
  1643. #define I2S_RCR4_FSE ((uint32_t)8) // Frame Sync Early
  1644. #define I2S_RCR4_MF ((uint32_t)0x10) // MSB First
  1645. #define I2S_RCR4_SYWD(n) ((uint32_t)(n & 0x1f)<<8) // Sync Width
  1646. #define I2S_RCR4_FRSZ(n) ((uint32_t)(n & 0x0f)<<16) // Frame Size
  1647. #define I2S0_RCR5 *(volatile uint32_t *)0x4002F094 // SAI Receive Configuration 5 Register
  1648. #define I2S_RCR5_FBT(n) ((uint32_t)(n & 0x1f)<<8) // First Bit Shifted
  1649. #define I2S_RCR5_W0W(n) ((uint32_t)(n & 0x1f)<<16) // Word 0 Width
  1650. #define I2S_RCR5_WNW(n) ((uint32_t)(n & 0x1f)<<24) // Word N Width
  1651. #define I2S0_RDR0 *(volatile uint32_t *)0x4002F0A0 // SAI Receive Data Register
  1652. #define I2S0_RFR0 *(volatile uint32_t *)0x4002F0C0 // SAI Receive FIFO Register
  1653. #define I2S_RFR_RFP(n) ((uint32_t)n & 7) // read FIFO pointer
  1654. #define I2S_RFR_WFP(n) ((uint32_t)(n & 7)<<16) // write FIFO pointer
  1655. #define I2S0_RMR *(volatile uint32_t *)0x4002F0E0 // SAI Receive Mask Register
  1656. #define I2S_RMR_RWM(n) ((uint32_t)n & 0xFFFFFFFF)
  1657. #define I2S0_MCR *(volatile uint32_t *)0x4002F100 // SAI MCLK Control Register
  1658. #define I2S_MCR_DUF ((uint32_t)1<<31) // Divider Update Flag
  1659. #define I2S_MCR_MOE ((uint32_t)1<<30) // MCLK Output Enable
  1660. #define I2S_MCR_MICS(n) ((uint32_t)(n & 3)<<24) // MCLK Input Clock Select
  1661. #define I2S0_MDR *(volatile uint32_t *)0x4002F104 // SAI MCLK Divide Register
  1662. #define I2S_MDR_FRACT(n) ((uint32_t)(n & 0xff)<<12) // MCLK Fraction
  1663. #define I2S_MDR_DIVIDE(n) ((uint32_t)(n & 0xfff)) // MCLK Divide
  1664. // Chapter 47: General-Purpose Input/Output (GPIO)
  1665. #define GPIOA_PDOR *(volatile uint32_t *)0x400FF000 // Port Data Output Register
  1666. #define GPIOA_PSOR *(volatile uint32_t *)0x400FF004 // Port Set Output Register
  1667. #define GPIOA_PCOR *(volatile uint32_t *)0x400FF008 // Port Clear Output Register
  1668. #define GPIOA_PTOR *(volatile uint32_t *)0x400FF00C // Port Toggle Output Register
  1669. #define GPIOA_PDIR *(volatile uint32_t *)0x400FF010 // Port Data Input Register
  1670. #define GPIOA_PDDR *(volatile uint32_t *)0x400FF014 // Port Data Direction Register
  1671. #define GPIOB_PDOR *(volatile uint32_t *)0x400FF040 // Port Data Output Register
  1672. #define GPIOB_PSOR *(volatile uint32_t *)0x400FF044 // Port Set Output Register
  1673. #define GPIOB_PCOR *(volatile uint32_t *)0x400FF048 // Port Clear Output Register
  1674. #define GPIOB_PTOR *(volatile uint32_t *)0x400FF04C // Port Toggle Output Register
  1675. #define GPIOB_PDIR *(volatile uint32_t *)0x400FF050 // Port Data Input Register
  1676. #define GPIOB_PDDR *(volatile uint32_t *)0x400FF054 // Port Data Direction Register
  1677. #define GPIOC_PDOR *(volatile uint32_t *)0x400FF080 // Port Data Output Register
  1678. #define GPIOC_PSOR *(volatile uint32_t *)0x400FF084 // Port Set Output Register
  1679. #define GPIOC_PCOR *(volatile uint32_t *)0x400FF088 // Port Clear Output Register
  1680. #define GPIOC_PTOR *(volatile uint32_t *)0x400FF08C // Port Toggle Output Register
  1681. #define GPIOC_PDIR *(volatile uint32_t *)0x400FF090 // Port Data Input Register
  1682. #define GPIOC_PDDR *(volatile uint32_t *)0x400FF094 // Port Data Direction Register
  1683. #define GPIOD_PDOR *(volatile uint32_t *)0x400FF0C0 // Port Data Output Register
  1684. #define GPIOD_PSOR *(volatile uint32_t *)0x400FF0C4 // Port Set Output Register
  1685. #define GPIOD_PCOR *(volatile uint32_t *)0x400FF0C8 // Port Clear Output Register
  1686. #define GPIOD_PTOR *(volatile uint32_t *)0x400FF0CC // Port Toggle Output Register
  1687. #define GPIOD_PDIR *(volatile uint32_t *)0x400FF0D0 // Port Data Input Register
  1688. #define GPIOD_PDDR *(volatile uint32_t *)0x400FF0D4 // Port Data Direction Register
  1689. #define GPIOE_PDOR *(volatile uint32_t *)0x400FF100 // Port Data Output Register
  1690. #define GPIOE_PSOR *(volatile uint32_t *)0x400FF104 // Port Set Output Register
  1691. #define GPIOE_PCOR *(volatile uint32_t *)0x400FF108 // Port Clear Output Register
  1692. #define GPIOE_PTOR *(volatile uint32_t *)0x400FF10C // Port Toggle Output Register
  1693. #define GPIOE_PDIR *(volatile uint32_t *)0x400FF110 // Port Data Input Register
  1694. #define GPIOE_PDDR *(volatile uint32_t *)0x400FF114 // Port Data Direction Register
  1695. // Chapter 48: Touch sense input (TSI)
  1696. #define TSI0_GENCS *(volatile uint32_t *)0x40045000 // General Control and Status Register
  1697. #define TSI_GENCS_LPCLKS (uint32_t)0x10000000 //
  1698. #define TSI_GENCS_LPSCNITV(n) (((n) & 15) << 24) //
  1699. #define TSI_GENCS_NSCN(n) (((n) & 31) << 19) //
  1700. #define TSI_GENCS_PS(n) (((n) & 7) << 16) //
  1701. #define TSI_GENCS_EOSF (uint32_t)0x00008000 //
  1702. #define TSI_GENCS_OUTRGF (uint32_t)0x00004000 //
  1703. #define TSI_GENCS_EXTERF (uint32_t)0x00002000 //
  1704. #define TSI_GENCS_OVRF (uint32_t)0x00001000 //
  1705. #define TSI_GENCS_SCNIP (uint32_t)0x00000200 //
  1706. #define TSI_GENCS_SWTS (uint32_t)0x00000100 //
  1707. #define TSI_GENCS_TSIEN (uint32_t)0x00000080 //
  1708. #define TSI_GENCS_TSIIE (uint32_t)0x00000040 //
  1709. #define TSI_GENCS_ERIE (uint32_t)0x00000020 //
  1710. #define TSI_GENCS_ESOR (uint32_t)0x00000010 //
  1711. #define TSI_GENCS_STM (uint32_t)0x00000002 //
  1712. #define TSI_GENCS_STPE (uint32_t)0x00000001 //
  1713. #define TSI0_SCANC *(volatile uint32_t *)0x40045004 // SCAN Control Register
  1714. #define TSI_SCANC_REFCHRG(n) (((n) & 15) << 24) //
  1715. #define TSI_SCANC_EXTCHRG(n) (((n) & 7) << 16) //
  1716. #define TSI_SCANC_SMOD(n) (((n) & 255) << 8) //
  1717. #define TSI_SCANC_AMCLKS(n) (((n) & 3) << 3) //
  1718. #define TSI_SCANC_AMPSC(n) (((n) & 7) << 0) //
  1719. #define TSI0_PEN *(volatile uint32_t *)0x40045008 // Pin Enable Register
  1720. #define TSI0_WUCNTR *(volatile uint32_t *)0x4004500C // Wake-Up Channel Counter Register
  1721. #define TSI0_CNTR1 *(volatile uint32_t *)0x40045100 // Counter Register
  1722. #define TSI0_CNTR3 *(volatile uint32_t *)0x40045104 // Counter Register
  1723. #define TSI0_CNTR5 *(volatile uint32_t *)0x40045108 // Counter Register
  1724. #define TSI0_CNTR7 *(volatile uint32_t *)0x4004510C // Counter Register
  1725. #define TSI0_CNTR9 *(volatile uint32_t *)0x40045110 // Counter Register
  1726. #define TSI0_CNTR11 *(volatile uint32_t *)0x40045114 // Counter Register
  1727. #define TSI0_CNTR13 *(volatile uint32_t *)0x40045118 // Counter Register
  1728. #define TSI0_CNTR15 *(volatile uint32_t *)0x4004511C // Counter Register
  1729. #define TSI0_THRESHOLD *(volatile uint32_t *)0x40045120 // Low Power Channel Threshold Register
  1730. // Nested Vectored Interrupt Controller, Table 3-4 & ARMv7 ref, appendix B3.4 (page 750)
  1731. #define NVIC_ENABLE_IRQ(n) (*((volatile uint32_t *)0xE000E100 + (n >> 5)) = (1 << (n & 31)))
  1732. #define NVIC_DISABLE_IRQ(n) (*((volatile uint32_t *)0xE000E180 + (n >> 5)) = (1 << (n & 31)))
  1733. #define NVIC_SET_PENDING(n) (*((volatile uint32_t *)0xE000E200 + (n >> 5)) = (1 << (n & 31)))
  1734. #define NVIC_CLEAR_PENDING(n) (*((volatile uint32_t *)0xE000E280 + (n >> 5)) = (1 << (n & 31)))
  1735. #define NVIC_ISER0 *(volatile uint32_t *)0xE000E100
  1736. #define NVIC_ISER1 *(volatile uint32_t *)0xE000E104
  1737. #define NVIC_ICER0 *(volatile uint32_t *)0xE000E180
  1738. #define NVIC_ICER1 *(volatile uint32_t *)0xE000E184
  1739. // 0 = highest priority
  1740. // Cortex-M4: 0,16,32,48,64,80,96,112,128,144,160,176,192,208,224,240
  1741. // Cortex-M0: 0,64,128,192
  1742. #define NVIC_SET_PRIORITY(irqnum, priority) (*((volatile uint8_t *)0xE000E400 + (irqnum)) = (uint8_t)(priority))
  1743. #define NVIC_GET_PRIORITY(irqnum) (*((uint8_t *)0xE000E400 + (irqnum)))
  1744. #if defined(__MK20DX128__)
  1745. #define IRQ_DMA_CH0 0
  1746. #define IRQ_DMA_CH1 1
  1747. #define IRQ_DMA_CH2 2
  1748. #define IRQ_DMA_CH3 3
  1749. #define IRQ_DMA_ERROR 4
  1750. #define IRQ_FTFL_COMPLETE 6
  1751. #define IRQ_FTFL_COLLISION 7
  1752. #define IRQ_LOW_VOLTAGE 8
  1753. #define IRQ_LLWU 9
  1754. #define IRQ_WDOG 10
  1755. #define IRQ_I2C0 11
  1756. #define IRQ_SPI0 12
  1757. #define IRQ_I2S0_TX 13
  1758. #define IRQ_I2S0_RX 14
  1759. #define IRQ_UART0_LON 15
  1760. #define IRQ_UART0_STATUS 16
  1761. #define IRQ_UART0_ERROR 17
  1762. #define IRQ_UART1_STATUS 18
  1763. #define IRQ_UART1_ERROR 19
  1764. #define IRQ_UART2_STATUS 20
  1765. #define IRQ_UART2_ERROR 21
  1766. #define IRQ_ADC0 22
  1767. #define IRQ_CMP0 23
  1768. #define IRQ_CMP1 24
  1769. #define IRQ_FTM0 25
  1770. #define IRQ_FTM1 26
  1771. #define IRQ_CMT 27
  1772. #define IRQ_RTC_ALARM 28
  1773. #define IRQ_RTC_SECOND 29
  1774. #define IRQ_PIT_CH0 30
  1775. #define IRQ_PIT_CH1 31
  1776. #define IRQ_PIT_CH2 32
  1777. #define IRQ_PIT_CH3 33
  1778. #define IRQ_PDB 34
  1779. #define IRQ_USBOTG 35
  1780. #define IRQ_USBDCD 36
  1781. #define IRQ_TSI 37
  1782. #define IRQ_MCG 38
  1783. #define IRQ_LPTMR 39
  1784. #define IRQ_PORTA 40
  1785. #define IRQ_PORTB 41
  1786. #define IRQ_PORTC 42
  1787. #define IRQ_PORTD 43
  1788. #define IRQ_PORTE 44
  1789. #define IRQ_SOFTWARE 45
  1790. #define NVIC_NUM_INTERRUPTS 46
  1791. #elif defined(__MK20DX256__)
  1792. #define IRQ_DMA_CH0 0
  1793. #define IRQ_DMA_CH1 1
  1794. #define IRQ_DMA_CH2 2
  1795. #define IRQ_DMA_CH3 3
  1796. #define IRQ_DMA_CH4 4
  1797. #define IRQ_DMA_CH5 5
  1798. #define IRQ_DMA_CH6 6
  1799. #define IRQ_DMA_CH7 7
  1800. #define IRQ_DMA_CH8 8
  1801. #define IRQ_DMA_CH9 9
  1802. #define IRQ_DMA_CH10 10
  1803. #define IRQ_DMA_CH11 11
  1804. #define IRQ_DMA_CH12 12
  1805. #define IRQ_DMA_CH13 13
  1806. #define IRQ_DMA_CH14 14
  1807. #define IRQ_DMA_CH15 15
  1808. #define IRQ_DMA_ERROR 16
  1809. #define IRQ_FTFL_COMPLETE 18
  1810. #define IRQ_FTFL_COLLISION 19
  1811. #define IRQ_LOW_VOLTAGE 20
  1812. #define IRQ_LLWU 21
  1813. #define IRQ_WDOG 22
  1814. #define IRQ_I2C0 24
  1815. #define IRQ_I2C1 25
  1816. #define IRQ_SPI0 26
  1817. #define IRQ_SPI1 27
  1818. #define IRQ_CAN_MESSAGE 29
  1819. #define IRQ_CAN_BUS_OFF 30
  1820. #define IRQ_CAN_ERROR 31
  1821. #define IRQ_CAN_TX_WARN 32
  1822. #define IRQ_CAN_RX_WARN 33
  1823. #define IRQ_CAN_WAKEUP 34
  1824. #define IRQ_I2S0_TX 35
  1825. #define IRQ_I2S0_RX 36
  1826. #define IRQ_UART0_LON 44
  1827. #define IRQ_UART0_STATUS 45
  1828. #define IRQ_UART0_ERROR 46
  1829. #define IRQ_UART1_STATUS 47
  1830. #define IRQ_UART1_ERROR 48
  1831. #define IRQ_UART2_STATUS 49
  1832. #define IRQ_UART2_ERROR 50
  1833. #define IRQ_ADC0 57
  1834. #define IRQ_ADC1 58
  1835. #define IRQ_CMP0 59
  1836. #define IRQ_CMP1 60
  1837. #define IRQ_CMP2 61
  1838. #define IRQ_FTM0 62
  1839. #define IRQ_FTM1 63
  1840. #define IRQ_FTM2 64
  1841. #define IRQ_CMT 65
  1842. #define IRQ_RTC_ALARM 66
  1843. #define IRQ_RTC_SECOND 67
  1844. #define IRQ_PIT_CH0 68
  1845. #define IRQ_PIT_CH1 69
  1846. #define IRQ_PIT_CH2 70
  1847. #define IRQ_PIT_CH3 71
  1848. #define IRQ_PDB 72
  1849. #define IRQ_USBOTG 73
  1850. #define IRQ_USBDCD 74
  1851. #define IRQ_DAC0 81
  1852. #define IRQ_TSI 83
  1853. #define IRQ_MCG 84
  1854. #define IRQ_LPTMR 85
  1855. #define IRQ_PORTA 87
  1856. #define IRQ_PORTB 88
  1857. #define IRQ_PORTC 89
  1858. #define IRQ_PORTD 90
  1859. #define IRQ_PORTE 91
  1860. #define IRQ_SOFTWARE 94
  1861. #define NVIC_NUM_INTERRUPTS 95
  1862. #endif
  1863. #define __disable_irq() asm volatile("CPSID i");
  1864. #define __enable_irq() asm volatile("CPSIE i");
  1865. // System Control Space (SCS), ARMv7 ref manual, B3.2, page 708
  1866. #define SCB_CPUID *(const uint32_t *)0xE000ED00 // CPUID Base Register
  1867. #define SCB_ICSR *(volatile uint32_t *)0xE000ED04 // Interrupt Control and State
  1868. #define SCB_ICSR_PENDSTSET (uint32_t)0x04000000
  1869. #define SCB_VTOR *(volatile uint32_t *)0xE000ED08 // Vector Table Offset
  1870. #define SCB_AIRCR *(volatile uint32_t *)0xE000ED0C // Application Interrupt and Reset Control
  1871. #define SCB_SCR *(volatile uint32_t *)0xE000ED10 // System Control Register
  1872. #define SCB_CCR *(volatile uint32_t *)0xE000ED14 // Configuration and Control
  1873. #define SCB_SHPR1 *(volatile uint32_t *)0xE000ED18 // System Handler Priority Register 1
  1874. #define SCB_SHPR2 *(volatile uint32_t *)0xE000ED1C // System Handler Priority Register 2
  1875. #define SCB_SHPR3 *(volatile uint32_t *)0xE000ED20 // System Handler Priority Register 3
  1876. #define SCB_SHCSR *(volatile uint32_t *)0xE000ED24 // System Handler Control and State
  1877. #define SCB_CFSR *(volatile uint32_t *)0xE000ED28 // Configurable Fault Status Register
  1878. #define SCB_HFSR *(volatile uint32_t *)0xE000ED2C // HardFault Status
  1879. #define SCB_DFSR *(volatile uint32_t *)0xE000ED30 // Debug Fault Status
  1880. #define SCB_MMFAR *(volatile uint32_t *)0xE000ED34 // MemManage Fault Address
  1881. #define SYST_CSR *(volatile uint32_t *)0xE000E010 // SysTick Control and Status
  1882. #define SYST_CSR_COUNTFLAG (uint32_t)0x00010000
  1883. #define SYST_CSR_CLKSOURCE (uint32_t)0x00000004
  1884. #define SYST_CSR_TICKINT (uint32_t)0x00000002
  1885. #define SYST_CSR_ENABLE (uint32_t)0x00000001
  1886. #define SYST_RVR *(volatile uint32_t *)0xE000E014 // SysTick Reload Value Register
  1887. #define SYST_CVR *(volatile uint32_t *)0xE000E018 // SysTick Current Value Register
  1888. #define SYST_CALIB *(const uint32_t *)0xE000E01C // SysTick Calibration Value
  1889. #define ARM_DEMCR *(volatile uint32_t *)0xE000EDFC // Debug Exception and Monitor Control
  1890. #define ARM_DEMCR_TRCENA (1 << 24) // Enable debugging & monitoring blocks
  1891. #define ARM_DWT_CTRL *(volatile uint32_t *)0xE0001000 // DWT control register
  1892. #define ARM_DWT_CTRL_CYCCNTENA (1 << 0) // Enable cycle count
  1893. #define ARM_DWT_CYCCNT *(volatile uint32_t *)0xE0001004 // Cycle count register
  1894. extern int nvic_execution_priority(void);
  1895. extern void nmi_isr(void);
  1896. extern void hard_fault_isr(void);
  1897. extern void memmanage_fault_isr(void);
  1898. extern void bus_fault_isr(void);
  1899. extern void usage_fault_isr(void);
  1900. extern void svcall_isr(void);
  1901. extern void debugmonitor_isr(void);
  1902. extern void pendablesrvreq_isr(void);
  1903. extern void systick_isr(void);
  1904. extern void dma_ch0_isr(void);
  1905. extern void dma_ch1_isr(void);
  1906. extern void dma_ch2_isr(void);
  1907. extern void dma_ch3_isr(void);
  1908. extern void dma_ch4_isr(void);
  1909. extern void dma_ch5_isr(void);
  1910. extern void dma_ch6_isr(void);
  1911. extern void dma_ch7_isr(void);
  1912. extern void dma_ch8_isr(void);
  1913. extern void dma_ch9_isr(void);
  1914. extern void dma_ch10_isr(void);
  1915. extern void dma_ch11_isr(void);
  1916. extern void dma_ch12_isr(void);
  1917. extern void dma_ch13_isr(void);
  1918. extern void dma_ch14_isr(void);
  1919. extern void dma_ch15_isr(void);
  1920. extern void dma_error_isr(void);
  1921. extern void mcm_isr(void);
  1922. extern void flash_cmd_isr(void);
  1923. extern void flash_error_isr(void);
  1924. extern void low_voltage_isr(void);
  1925. extern void wakeup_isr(void);
  1926. extern void watchdog_isr(void);
  1927. extern void i2c0_isr(void);
  1928. extern void i2c1_isr(void);
  1929. extern void i2c2_isr(void);
  1930. extern void spi0_isr(void);
  1931. extern void spi1_isr(void);
  1932. extern void spi2_isr(void);
  1933. extern void sdhc_isr(void);
  1934. extern void can0_message_isr(void);
  1935. extern void can0_bus_off_isr(void);
  1936. extern void can0_error_isr(void);
  1937. extern void can0_tx_warn_isr(void);
  1938. extern void can0_rx_warn_isr(void);
  1939. extern void can0_wakeup_isr(void);
  1940. extern void i2s0_tx_isr(void);
  1941. extern void i2s0_rx_isr(void);
  1942. extern void uart0_lon_isr(void);
  1943. extern void uart0_status_isr(void);
  1944. extern void uart0_error_isr(void);
  1945. extern void uart1_status_isr(void);
  1946. extern void uart1_error_isr(void);
  1947. extern void uart2_status_isr(void);
  1948. extern void uart2_error_isr(void);
  1949. extern void uart3_status_isr(void);
  1950. extern void uart3_error_isr(void);
  1951. extern void uart4_status_isr(void);
  1952. extern void uart4_error_isr(void);
  1953. extern void uart5_status_isr(void);
  1954. extern void uart5_error_isr(void);
  1955. extern void adc0_isr(void);
  1956. extern void adc1_isr(void);
  1957. extern void cmp0_isr(void);
  1958. extern void cmp1_isr(void);
  1959. extern void cmp2_isr(void);
  1960. extern void ftm0_isr(void);
  1961. extern void ftm1_isr(void);
  1962. extern void ftm2_isr(void);
  1963. extern void ftm3_isr(void);
  1964. extern void cmt_isr(void);
  1965. extern void rtc_alarm_isr(void);
  1966. extern void rtc_seconds_isr(void);
  1967. extern void pit0_isr(void);
  1968. extern void pit1_isr(void);
  1969. extern void pit2_isr(void);
  1970. extern void pit3_isr(void);
  1971. extern void pdb_isr(void);
  1972. extern void usb_isr(void);
  1973. extern void usb_charge_isr(void);
  1974. extern void dac0_isr(void);
  1975. extern void dac1_isr(void);
  1976. extern void tsi0_isr(void);
  1977. extern void mcg_isr(void);
  1978. extern void lptmr_isr(void);
  1979. extern void porta_isr(void);
  1980. extern void portb_isr(void);
  1981. extern void portc_isr(void);
  1982. extern void portd_isr(void);
  1983. extern void porte_isr(void);
  1984. extern void software_isr(void);
  1985. #ifdef __cplusplus
  1986. }
  1987. #endif
  1988. #endif