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imxrt1062_t41.ld 2.5KB

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  1. MEMORY
  2. {
  3. ITCM (rwx): ORIGIN = 0x00000000, LENGTH = 512K
  4. DTCM (rwx): ORIGIN = 0x20000000, LENGTH = 512K
  5. RAM (rwx): ORIGIN = 0x20200000, LENGTH = 512K
  6. FLASH (rwx): ORIGIN = 0x60000000, LENGTH = 7936K
  7. ERAM (rwx): ORIGIN = 0x70000000, LENGTH = 16384K
  8. }
  9. ENTRY(ImageVectorTable)
  10. SECTIONS
  11. {
  12. .text.progmem : {
  13. KEEP(*(.flashconfig))
  14. FILL(0xFF)
  15. . = ORIGIN(FLASH) + 0x1000;
  16. KEEP(*(.ivt))
  17. KEEP(*(.bootdata))
  18. KEEP(*(.startup))
  19. *(.flashmem*)
  20. *(.progmem*)
  21. . = ALIGN(4);
  22. KEEP(*(.init))
  23. __preinit_array_start = .;
  24. KEEP (*(.preinit_array))
  25. __preinit_array_end = .;
  26. __init_array_start = .;
  27. KEEP (*(.init_array))
  28. __init_array_end = .;
  29. . = ALIGN(16);
  30. } > FLASH
  31. .text.itcm : {
  32. . = . + 32; /* MPU to trap NULL pointer deref */
  33. *(.fastrun)
  34. *(.text*)
  35. . = ALIGN(16);
  36. } > ITCM AT> FLASH
  37. .ARM.exidx : {
  38. __exidx_start = .;
  39. *(.ARM.exidx* .gnu.linkonce.armexidx.*)
  40. __exidx_end = .;
  41. } > ITCM AT> FLASH
  42. .text.itcm.padding (NOLOAD) : {
  43. . = ALIGN(32768);
  44. } > ITCM
  45. .data : {
  46. *(.rodata*)
  47. *(.data*)
  48. } > DTCM AT> FLASH
  49. .bss ALIGN(4) : {
  50. *(.bss*)
  51. *(COMMON)
  52. . = ALIGN(32);
  53. . = . + 32; /* MPU to trap stack overflow */
  54. } > DTCM
  55. .bss.dma (NOLOAD) : {
  56. *(.hab_log)
  57. *(.dmabuffers)
  58. . = ALIGN(32);
  59. } > RAM
  60. .bss.extram (NOLOAD) : {
  61. *(.externalram)
  62. . = ALIGN(32);
  63. } > ERAM
  64. .text.csf : {
  65. FILL(0xFF)
  66. . = ALIGN(4);
  67. KEEP(*(.csf))
  68. } > FLASH
  69. _stext = ADDR(.text.itcm);
  70. _etext = ADDR(.text.itcm) + SIZEOF(.text.itcm) + SIZEOF(.ARM.exidx);
  71. _stextload = LOADADDR(.text.itcm);
  72. _sdata = ADDR(.data);
  73. _edata = ADDR(.data) + SIZEOF(.data);
  74. _sdataload = LOADADDR(.data);
  75. _sbss = ADDR(.bss);
  76. _ebss = ADDR(.bss) + SIZEOF(.bss);
  77. _heap_start = ADDR(.bss.dma) + SIZEOF(.bss.dma);
  78. _heap_end = ORIGIN(RAM) + LENGTH(RAM);
  79. _extram_start = ADDR(.bss.extram);
  80. _extram_end = ADDR(.bss.extram) + SIZEOF(.bss.extram);
  81. _itcm_block_count = (SIZEOF(.text.itcm) + SIZEOF(.ARM.exidx) + 0x7FFF) >> 15;
  82. _flexram_bank_config = 0xAAAAAAAA | ((1 << (_itcm_block_count * 2)) - 1);
  83. _estack = ORIGIN(DTCM) + ((16 - _itcm_block_count) << 15);
  84. _flashimagelen = SIZEOF(.text.progmem) + SIZEOF(.text.itcm) + SIZEOF(.ARM.exidx) + SIZEOF(.data) + SIZEOF(.text.csf);
  85. _teensy_model_identifier = 0x25;
  86. .debug_info 0 : { *(.debug_info) }
  87. .debug_abbrev 0 : { *(.debug_abbrev) }
  88. .debug_line 0 : { *(.debug_line) }
  89. .debug_frame 0 : { *(.debug_frame) }
  90. .debug_str 0 : { *(.debug_str) }
  91. .debug_loc 0 : { *(.debug_loc) }
  92. }