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HardwareSerial.cpp 18KB

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  1. /* Teensyduino Core Library
  2. * http://www.pjrc.com/teensy/
  3. * Copyright (c) 2019 PJRC.COM, LLC.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining
  6. * a copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sublicense, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * 1. The above copyright notice and this permission notice shall be
  14. * included in all copies or substantial portions of the Software.
  15. *
  16. * 2. If the Software is incorporated into a build system that allows
  17. * selection among a list of target devices, then similar target
  18. * devices manufactured by PJRC.COM must be included in the list of
  19. * target devices and selectable in the same manner.
  20. *
  21. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  24. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  25. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  26. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  27. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  28. * SOFTWARE.
  29. */
  30. #include "HardwareSerial.h"
  31. #include "core_pins.h"
  32. #include "Arduino.h"
  33. //#include "debug/printf.h"
  34. /*typedef struct {
  35. const uint32_t VERID;
  36. const uint32_t PARAM;
  37. volatile uint32_t GLOBAL;
  38. volatile uint32_t PINCFG;
  39. volatile uint32_t BAUD;
  40. volatile uint32_t STAT;
  41. volatile uint32_t CTRL;
  42. volatile uint32_t DATA;
  43. volatile uint32_t MATCH;
  44. volatile uint32_t MODIR;
  45. volatile uint32_t FIFO;
  46. volatile uint32_t WATER;
  47. } IMXRT_LPUART_t; */
  48. //. From Onewire utility files
  49. #define PIN_TO_BASEREG(pin) (portOutputRegister(pin))
  50. #define PIN_TO_BITMASK(pin) (digitalPinToBitMask(pin))
  51. #define IO_REG_TYPE uint32_t
  52. #define IO_REG_BASE_ATTR
  53. #define IO_REG_MASK_ATTR
  54. #define DIRECT_READ(base, mask) ((*((base)+2) & (mask)) ? 1 : 0)
  55. #define DIRECT_MODE_INPUT(base, mask) (*((base)+1) &= ~(mask))
  56. #define DIRECT_MODE_OUTPUT(base, mask) (*((base)+1) |= (mask))
  57. #define DIRECT_WRITE_LOW(base, mask) (*((base)+34) = (mask))
  58. #define DIRECT_WRITE_HIGH(base, mask) (*((base)+33) = (mask))
  59. #define UART_CLOCK 24000000
  60. #if defined(ARDUINO_TEENSY41)
  61. SerialEventCheckingFunctionPointer HardwareSerial::serial_event_handler_checks[8] = {nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr};
  62. #else
  63. SerialEventCheckingFunctionPointer HardwareSerial::serial_event_handler_checks[7] = {nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr};
  64. #endif
  65. uint8_t HardwareSerial::serial_event_handlers_active = 0;
  66. #define CTRL_ENABLE (LPUART_CTRL_TE | LPUART_CTRL_RE | LPUART_CTRL_RIE | LPUART_CTRL_ILIE)
  67. #define CTRL_TX_ACTIVE (CTRL_ENABLE | LPUART_CTRL_TIE)
  68. #define CTRL_TX_COMPLETING (CTRL_ENABLE | LPUART_CTRL_TCIE)
  69. #define CTRL_TX_INACTIVE CTRL_ENABLE
  70. // Copied from T3.x - probably should move to other location.
  71. int nvic_execution_priority(void)
  72. {
  73. uint32_t priority=256;
  74. uint32_t primask, faultmask, basepri, ipsr;
  75. // full algorithm in ARM DDI0403D, page B1-639
  76. // this isn't quite complete, but hopefully good enough
  77. __asm__ volatile("mrs %0, faultmask\n" : "=r" (faultmask)::);
  78. if (faultmask) return -1;
  79. __asm__ volatile("mrs %0, primask\n" : "=r" (primask)::);
  80. if (primask) return 0;
  81. __asm__ volatile("mrs %0, ipsr\n" : "=r" (ipsr)::);
  82. if (ipsr) {
  83. if (ipsr < 16) priority = 0; // could be non-zero
  84. else priority = NVIC_GET_PRIORITY(ipsr - 16);
  85. }
  86. __asm__ volatile("mrs %0, basepri\n" : "=r" (basepri)::);
  87. if (basepri > 0 && basepri < priority) priority = basepri;
  88. return priority;
  89. }
  90. void HardwareSerial::begin(uint32_t baud, uint16_t format)
  91. {
  92. //printf("HardwareSerial begin\n");
  93. float base = (float)UART_CLOCK / (float)baud;
  94. float besterr = 1e20;
  95. int bestdiv = 1;
  96. int bestosr = 4;
  97. for (int osr=4; osr <= 32; osr++) {
  98. float div = base / (float)osr;
  99. int divint = (int)(div + 0.5f);
  100. if (divint < 1) divint = 1;
  101. else if (divint > 8191) divint = 8191;
  102. float err = ((float)divint - div) / div;
  103. if (err < 0.0f) err = -err;
  104. if (err <= besterr) {
  105. besterr = err;
  106. bestdiv = divint;
  107. bestosr = osr;
  108. }
  109. }
  110. //printf(" baud %d: osr=%d, div=%d\n", baud, bestosr, bestdiv);
  111. rx_buffer_head_ = 0;
  112. rx_buffer_tail_ = 0;
  113. tx_buffer_head_ = 0;
  114. tx_buffer_tail_ = 0;
  115. rts_low_watermark_ = rx_buffer_total_size_ - hardware->rts_low_watermark;
  116. rts_high_watermark_ = rx_buffer_total_size_ - hardware->rts_high_watermark;
  117. transmitting_ = 0;
  118. hardware->ccm_register |= hardware->ccm_value;
  119. // uint32_t fastio = IOMUXC_PAD_SRE | IOMUXC_PAD_DSE(3) | IOMUXC_PAD_SPEED(3);
  120. *(portControlRegister(hardware->rx_pins[rx_pin_index_].pin)) = IOMUXC_PAD_DSE(7) | IOMUXC_PAD_PKE | IOMUXC_PAD_PUE | IOMUXC_PAD_PUS(3) | IOMUXC_PAD_HYS;
  121. *(portConfigRegister(hardware->rx_pins[rx_pin_index_].pin)) = hardware->rx_pins[rx_pin_index_].mux_val;
  122. if (hardware->rx_pins[rx_pin_index_].select_input_register) {
  123. *(hardware->rx_pins[rx_pin_index_].select_input_register) = hardware->rx_pins[rx_pin_index_].select_val;
  124. }
  125. *(portControlRegister(hardware->tx_pins[tx_pin_index_].pin)) = IOMUXC_PAD_SRE | IOMUXC_PAD_DSE(3) | IOMUXC_PAD_SPEED(3);
  126. *(portConfigRegister(hardware->tx_pins[tx_pin_index_].pin)) = hardware->tx_pins[tx_pin_index_].mux_val;
  127. //hardware->rx_mux_register = hardware->rx_mux_val;
  128. //hardware->tx_mux_register = hardware->tx_mux_val;
  129. port->BAUD = LPUART_BAUD_OSR(bestosr - 1) | LPUART_BAUD_SBR(bestdiv)
  130. | (bestosr <= 8 ? LPUART_BAUD_BOTHEDGE : 0);
  131. port->PINCFG = 0;
  132. // Enable the transmitter, receiver and enable receiver interrupt
  133. attachInterruptVector(hardware->irq, hardware->irq_handler);
  134. NVIC_SET_PRIORITY(hardware->irq, hardware->irq_priority); // maybe should put into hardware...
  135. NVIC_ENABLE_IRQ(hardware->irq);
  136. uint16_t tx_fifo_size = (((port->FIFO >> 4) & 0x7) << 2);
  137. uint8_t tx_water = (tx_fifo_size < 16) ? tx_fifo_size >> 1 : 7;
  138. uint16_t rx_fifo_size = (((port->FIFO >> 0) & 0x7) << 2);
  139. uint8_t rx_water = (rx_fifo_size < 16) ? rx_fifo_size >> 1 : 7;
  140. /*
  141. Serial.printf("SerialX::begin stat:%x ctrl:%x fifo:%x water:%x\n", port->STAT, port->CTRL, port->FIFO, port->WATER );
  142. Serial.printf(" FIFO sizes: tx:%d rx:%d\n",tx_fifo_size, rx_fifo_size);
  143. Serial.printf(" Watermark tx:%d, rx: %d\n", tx_water, rx_water);
  144. */
  145. port->WATER = LPUART_WATER_RXWATER(rx_water) | LPUART_WATER_TXWATER(tx_water);
  146. port->FIFO |= LPUART_FIFO_TXFE | LPUART_FIFO_RXFE;
  147. // lets configure up our CTRL register value
  148. uint32_t ctrl = CTRL_TX_INACTIVE;
  149. // Now process the bits in the Format value passed in
  150. // Bits 0-2 - Parity plus 9 bit.
  151. ctrl |= (format & (LPUART_CTRL_PT | LPUART_CTRL_PE) ); // configure parity - turn off PT, PE, M and configure PT, PE
  152. if (format & 0x04) ctrl |= LPUART_CTRL_M; // 9 bits (might include parity)
  153. if ((format & 0x0F) == 0x04) ctrl |= LPUART_CTRL_R9T8; // 8N2 is 9 bit with 9th bit always 1
  154. // Bit 5 TXINVERT
  155. if (format & 0x20) ctrl |= LPUART_CTRL_TXINV; // tx invert
  156. // write out computed CTRL
  157. port->CTRL = ctrl;
  158. // Bit 3 10 bit - Will assume that begin already cleared it.
  159. // process some other bits which change other registers.
  160. if (format & 0x08) port->BAUD |= LPUART_BAUD_M10;
  161. // Bit 4 RXINVERT
  162. uint32_t c = port->STAT & ~LPUART_STAT_RXINV;
  163. if (format & 0x10) c |= LPUART_STAT_RXINV; // rx invert
  164. port->STAT = c;
  165. // bit 8 can turn on 2 stop bit mote
  166. if ( format & 0x100) port->BAUD |= LPUART_BAUD_SBNS;
  167. //Serial.printf(" stat:%x ctrl:%x fifo:%x water:%x\n", port->STAT, port->CTRL, port->FIFO, port->WATER );
  168. enableSerialEvents(); // Enable the processing of serialEvent for this object
  169. };
  170. inline void HardwareSerial::rts_assert()
  171. {
  172. DIRECT_WRITE_LOW(rts_pin_baseReg_, rts_pin_bitmask_);
  173. }
  174. inline void HardwareSerial::rts_deassert()
  175. {
  176. DIRECT_WRITE_HIGH(rts_pin_baseReg_, rts_pin_bitmask_);
  177. }
  178. void HardwareSerial::end(void)
  179. {
  180. if (!(hardware->ccm_register & hardware->ccm_value)) return;
  181. while (transmitting_) yield(); // wait for buffered data to send
  182. port->CTRL = 0; // disable the TX and RX ...
  183. // Not sure if this is best, but I think most IO pins default to Mode 5? which appears to be digital IO?
  184. *(portConfigRegister(hardware->rx_pins[rx_pin_index_].pin)) = 5;
  185. *(portConfigRegister(hardware->tx_pins[tx_pin_index_].pin)) = 5;
  186. // Might need to clear out other areas as well?
  187. rx_buffer_head_ = 0;
  188. rx_buffer_tail_ = 0;
  189. if (rts_pin_baseReg_) rts_deassert();
  190. //
  191. disableSerialEvents(); // disable the processing of serialEvent for this object
  192. }
  193. void HardwareSerial::transmitterEnable(uint8_t pin)
  194. {
  195. while (transmitting_) ;
  196. pinMode(pin, OUTPUT);
  197. transmit_pin_baseReg_ = PIN_TO_BASEREG(pin);
  198. transmit_pin_bitmask_ = PIN_TO_BITMASK(pin);
  199. DIRECT_WRITE_LOW(transmit_pin_baseReg_, transmit_pin_bitmask_);
  200. }
  201. void HardwareSerial::setRX(uint8_t pin)
  202. {
  203. if (pin != hardware->rx_pins[rx_pin_index_].pin) {
  204. for (uint8_t rx_pin_new_index = 0; rx_pin_new_index < cnt_rx_pins; rx_pin_new_index++) {
  205. if (pin == hardware->rx_pins[rx_pin_index_].pin) {
  206. // new pin - so lets maybe reset the old pin to INPUT? and then set new pin parameters
  207. *(portConfigRegister(hardware->rx_pins[rx_pin_index_].pin)) = 5;
  208. // now set new pin info.
  209. rx_pin_index_ = rx_pin_new_index;
  210. *(portControlRegister(hardware->rx_pins[rx_pin_index_].pin)) = IOMUXC_PAD_DSE(7) | IOMUXC_PAD_PKE | IOMUXC_PAD_PUE | IOMUXC_PAD_PUS(3) | IOMUXC_PAD_HYS;;
  211. *(portConfigRegister(hardware->rx_pins[rx_pin_index_].pin)) = hardware->rx_pins[rx_pin_index_].mux_val;
  212. if (hardware->rx_pins[rx_pin_index_].select_input_register) {
  213. *(hardware->rx_pins[rx_pin_index_].select_input_register) = hardware->rx_pins[rx_pin_index_].select_val;
  214. }
  215. break;
  216. }
  217. }
  218. }
  219. }
  220. void HardwareSerial::setTX(uint8_t pin, bool opendrain)
  221. {
  222. uint8_t tx_pin_new_index = tx_pin_index_;
  223. if (pin != hardware->tx_pins[tx_pin_index_].pin) {
  224. for (tx_pin_new_index = 0; tx_pin_new_index < cnt_tx_pins; tx_pin_new_index++) {
  225. if (pin == hardware->tx_pins[tx_pin_index_].pin) {
  226. break;
  227. }
  228. }
  229. if (tx_pin_new_index == cnt_tx_pins) return; // not a new valid pid...
  230. }
  231. // turn on or off opendrain mode.
  232. // new pin - so lets maybe reset the old pin to INPUT? and then set new pin parameters
  233. if (tx_pin_new_index != tx_pin_index_) {
  234. *(portConfigRegister(hardware->tx_pins[tx_pin_index_].pin)) = 5;
  235. *(portConfigRegister(hardware->tx_pins[tx_pin_new_index].pin)) = hardware->tx_pins[tx_pin_new_index].mux_val;
  236. }
  237. // now set new pin info.
  238. tx_pin_index_ = tx_pin_new_index;
  239. if (opendrain)
  240. *(portControlRegister(pin)) = IOMUXC_PAD_ODE | IOMUXC_PAD_DSE(3) | IOMUXC_PAD_SPEED(3);
  241. else
  242. *(portControlRegister(pin)) = IOMUXC_PAD_SRE | IOMUXC_PAD_DSE(3) | IOMUXC_PAD_SPEED(3);
  243. }
  244. bool HardwareSerial::attachRts(uint8_t pin)
  245. {
  246. if (!(hardware->ccm_register & hardware->ccm_value)) return 0;
  247. if (pin < CORE_NUM_DIGITAL) {
  248. rts_pin_baseReg_ = PIN_TO_BASEREG(pin);
  249. rts_pin_bitmask_ = PIN_TO_BITMASK(pin);
  250. pinMode(pin, OUTPUT);
  251. rts_assert();
  252. } else {
  253. rts_pin_baseReg_ = NULL;
  254. return 0;
  255. }
  256. return 1;
  257. }
  258. bool HardwareSerial::attachCts(uint8_t pin)
  259. {
  260. if (!(hardware->ccm_register & hardware->ccm_value)) return false;
  261. if ((pin != 0xff) && (pin == hardware->cts_pin)) {
  262. // Setup the IO pin as weak PULL down.
  263. *(portControlRegister(pin)) = IOMUXC_PAD_DSE(7) | IOMUXC_PAD_PKE | IOMUXC_PAD_PUE | IOMUXC_PAD_PUS(0) | IOMUXC_PAD_HYS;
  264. *(portConfigRegister(hardware->cts_pin)) = hardware->cts_mux_val;
  265. port->MODIR |= LPUART_MODIR_TXCTSE;
  266. return true;
  267. } else {
  268. port->MODIR &= ~LPUART_MODIR_TXCTSE;
  269. return false;
  270. }
  271. }
  272. void HardwareSerial::clear(void)
  273. {
  274. // BUGBUG:: deal with FIFO
  275. rx_buffer_head_ = rx_buffer_tail_;
  276. if (rts_pin_baseReg_) rts_assert();
  277. }
  278. int HardwareSerial::availableForWrite(void)
  279. {
  280. uint32_t head, tail;
  281. head = tx_buffer_head_;
  282. tail = tx_buffer_tail_;
  283. if (head >= tail) return tx_buffer_total_size_ - 1 - head + tail;
  284. return tail - head - 1;
  285. }
  286. int HardwareSerial::available(void)
  287. {
  288. uint32_t head, tail;
  289. head = rx_buffer_head_;
  290. tail = rx_buffer_tail_;
  291. if (head >= tail) return head - tail;
  292. return rx_buffer_total_size_ + head - tail;
  293. }
  294. void HardwareSerial::addStorageForRead(void *buffer, size_t length)
  295. {
  296. rx_buffer_storage_ = (BUFTYPE*)buffer;
  297. if (buffer) {
  298. rx_buffer_total_size_ = rx_buffer_total_size_ + length;
  299. } else {
  300. rx_buffer_total_size_ = rx_buffer_total_size_;
  301. }
  302. rts_low_watermark_ = rx_buffer_total_size_ - hardware->rts_low_watermark;
  303. rts_high_watermark_ = rx_buffer_total_size_ - hardware->rts_high_watermark;
  304. }
  305. void HardwareSerial::addStorageForWrite(void *buffer, size_t length)
  306. {
  307. tx_buffer_storage_ = (BUFTYPE*)buffer;
  308. if (buffer) {
  309. tx_buffer_total_size_ = tx_buffer_total_size_ + length;
  310. } else {
  311. tx_buffer_total_size_ = tx_buffer_total_size_;
  312. }
  313. }
  314. int HardwareSerial::peek(void)
  315. {
  316. uint32_t head, tail;
  317. head = rx_buffer_head_;
  318. tail = rx_buffer_tail_;
  319. if (head == tail) return -1;
  320. if (++tail >= rx_buffer_total_size_) tail = 0;
  321. if (tail < rx_buffer_size_) {
  322. return rx_buffer_[tail];
  323. } else {
  324. return rx_buffer_storage_[tail-rx_buffer_size_];
  325. }
  326. }
  327. int HardwareSerial::read(void)
  328. {
  329. uint32_t head, tail;
  330. int c;
  331. head = rx_buffer_head_;
  332. tail = rx_buffer_tail_;
  333. if (head == tail) return -1;
  334. if (++tail >= rx_buffer_total_size_) tail = 0;
  335. if (tail < rx_buffer_size_) {
  336. c = rx_buffer_[tail];
  337. } else {
  338. c = rx_buffer_storage_[tail-rx_buffer_size_];
  339. }
  340. rx_buffer_tail_ = tail;
  341. if (rts_pin_baseReg_) {
  342. uint32_t avail;
  343. if (head >= tail) avail = head - tail;
  344. else avail = rx_buffer_total_size_ + head - tail;
  345. if (avail <= rts_low_watermark_) rts_assert();
  346. }
  347. return c;
  348. }
  349. void HardwareSerial::flush(void)
  350. {
  351. while (transmitting_) yield(); // wait
  352. }
  353. size_t HardwareSerial::write(uint8_t c)
  354. {
  355. // use the 9 bit version (maybe 10 bit) do do the work.
  356. return write9bit(c);
  357. }
  358. size_t HardwareSerial::write9bit(uint32_t c)
  359. {
  360. uint32_t head, n;
  361. //digitalWrite(3, HIGH);
  362. //digitalWrite(5, HIGH);
  363. if (transmit_pin_baseReg_) DIRECT_WRITE_HIGH(transmit_pin_baseReg_, transmit_pin_bitmask_);
  364. head = tx_buffer_head_;
  365. if (++head >= tx_buffer_total_size_) head = 0;
  366. while (tx_buffer_tail_ == head) {
  367. int priority = nvic_execution_priority();
  368. if (priority <= hardware->irq_priority) {
  369. if ((port->STAT & LPUART_STAT_TDRE)) {
  370. uint32_t tail = tx_buffer_tail_;
  371. if (++tail >= tx_buffer_total_size_) tail = 0;
  372. if (tail < tx_buffer_size_) {
  373. n = tx_buffer_[tail];
  374. } else {
  375. n = tx_buffer_storage_[tail-tx_buffer_size_];
  376. }
  377. port->DATA = n;
  378. tx_buffer_tail_ = tail;
  379. }
  380. } else if (priority >= 256)
  381. {
  382. yield(); // wait
  383. }
  384. }
  385. //digitalWrite(5, LOW);
  386. //Serial.printf("WR %x %d %d %d %x %x\n", c, head, tx_buffer_size_, tx_buffer_total_size_, (uint32_t)tx_buffer_, (uint32_t)tx_buffer_storage_);
  387. if (head < tx_buffer_size_) {
  388. tx_buffer_[head] = c;
  389. } else {
  390. tx_buffer_storage_[head - tx_buffer_size_] = c;
  391. }
  392. __disable_irq();
  393. transmitting_ = 1;
  394. tx_buffer_head_ = head;
  395. port->CTRL |= LPUART_CTRL_TIE; // (may need to handle this issue)BITBAND_SET_BIT(LPUART0_CTRL, TIE_BIT);
  396. __enable_irq();
  397. //digitalWrite(3, LOW);
  398. return 1;
  399. }
  400. void HardwareSerial::IRQHandler()
  401. {
  402. //digitalWrite(4, HIGH);
  403. uint32_t head, tail, n;
  404. uint32_t ctrl;
  405. // See if we have stuff to read in.
  406. // Todo - Check idle.
  407. if (port->STAT & (LPUART_STAT_RDRF | LPUART_STAT_IDLE)) {
  408. // See how many bytes or pending.
  409. //digitalWrite(5, HIGH);
  410. uint8_t avail = (port->WATER >> 24) & 0x7;
  411. if (avail) {
  412. uint32_t newhead;
  413. head = rx_buffer_head_;
  414. tail = rx_buffer_tail_;
  415. do {
  416. n = port->DATA & 0x3ff; // Use only up to 10 bits of data
  417. newhead = head + 1;
  418. if (newhead >= rx_buffer_total_size_) newhead = 0;
  419. if (newhead != rx_buffer_tail_) {
  420. head = newhead;
  421. if (newhead < rx_buffer_size_) {
  422. rx_buffer_[head] = n;
  423. } else {
  424. rx_buffer_storage_[head-rx_buffer_size_] = n;
  425. }
  426. }
  427. } while (--avail > 0) ;
  428. rx_buffer_head_ = head;
  429. if (rts_pin_baseReg_) {
  430. uint32_t avail;
  431. if (head >= tail) avail = head - tail;
  432. else avail = rx_buffer_total_size_ + head - tail;
  433. if (avail >= rts_high_watermark_) rts_deassert();
  434. }
  435. }
  436. // If it was an idle status clear the idle
  437. if (port->STAT & LPUART_STAT_IDLE) {
  438. port->STAT |= LPUART_STAT_IDLE; // writing a 1 to idle should clear it.
  439. }
  440. //digitalWrite(5, LOW);
  441. }
  442. // See if we are transmitting and room in buffer.
  443. ctrl = port->CTRL;
  444. if ((ctrl & LPUART_CTRL_TIE) && (port->STAT & LPUART_STAT_TDRE))
  445. {
  446. //digitalWrite(3, HIGH);
  447. head = tx_buffer_head_;
  448. tail = tx_buffer_tail_;
  449. do {
  450. if (head == tail) break;
  451. if (++tail >= tx_buffer_total_size_) tail = 0;
  452. if (tail < tx_buffer_size_) {
  453. n = tx_buffer_[tail];
  454. } else {
  455. n = tx_buffer_storage_[tail-tx_buffer_size_];
  456. }
  457. port->DATA = n;
  458. } while (((port->WATER >> 8) & 0x7) < 4); // need to computer properly
  459. tx_buffer_tail_ = tail;
  460. if (head == tail) {
  461. port->CTRL &= ~LPUART_CTRL_TIE;
  462. port->CTRL |= LPUART_CTRL_TCIE; // Actually wondering if we can just leave this one on...
  463. }
  464. //digitalWrite(3, LOW);
  465. }
  466. if ((ctrl & LPUART_CTRL_TCIE) && (port->STAT & LPUART_STAT_TC))
  467. {
  468. transmitting_ = 0;
  469. if (transmit_pin_baseReg_) DIRECT_WRITE_LOW(transmit_pin_baseReg_, transmit_pin_bitmask_);
  470. port->CTRL &= ~LPUART_CTRL_TCIE;
  471. }
  472. //digitalWrite(4, LOW);
  473. }
  474. void HardwareSerial::processSerialEvents()
  475. {
  476. if (!serial_event_handlers_active) return; // bail quick if no one processing SerialEvents.
  477. uint8_t handlers_still_to_process = serial_event_handlers_active;
  478. for (uint8_t i = 0; i < 8; i++) {
  479. if (serial_event_handler_checks[i]) {
  480. (*serial_event_handler_checks[i])();
  481. if (--handlers_still_to_process == 0) return;
  482. }
  483. }
  484. }
  485. void HardwareSerial::enableSerialEvents()
  486. {
  487. if (!serial_event_handler_checks[hardware->serial_index]) {
  488. serial_event_handler_checks[hardware->serial_index] = hardware->serial_event_handler_check; // clear it out
  489. serial_event_handlers_active++;
  490. }
  491. }
  492. void HardwareSerial::disableSerialEvents()
  493. {
  494. if (serial_event_handler_checks[hardware->serial_index]) {
  495. serial_event_handler_checks[hardware->serial_index] = nullptr; // clear it out
  496. serial_event_handlers_active--;
  497. }
  498. }