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#define FTM2_CONF (*(volatile uint32_t *)0x4003A084) // Configuration |
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#define FTM2_CONF (*(volatile uint32_t *)0x4003A084) // Configuration |
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#endif |
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#endif |
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// Chapter 36: Periodic Interrupt Timer (PIT) |
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// Chapter 36 (3.1)/Chapter 32 (LC): Periodic Interrupt Timer (PIT) |
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#define PIT_MCR (*(volatile uint32_t *)0x40037000) // PIT Module Control Register |
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#define PIT_MCR (*(volatile uint32_t *)0x40037000) // PIT Module Control Register |
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#define PIT_MCR_MDIS (1<<1) // Module disable |
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#define PIT_MCR_FRZ (1<<0) // Freeze |
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#if defined(KINETISL) |
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#define PIT_LTMR64H (*(volatile uint32_t *)0x400370E0) // PIT Upper Lifetime Timer Register |
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#define PIT_LTMR64L (*(volatile uint32_t *)0x400370E4) // PIT Lower Lifetime Timer Register |
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#endif // defined(KINETISL) |
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#define PIT_LDVAL0 (*(volatile uint32_t *)0x40037100) // Timer Load Value Register |
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#define PIT_LDVAL0 (*(volatile uint32_t *)0x40037100) // Timer Load Value Register |
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#define PIT_CVAL0 (*(volatile uint32_t *)0x40037104) // Current Timer Value Register |
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#define PIT_CVAL0 (*(volatile uint32_t *)0x40037104) // Current Timer Value Register |
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#define PIT_TCTRL0 (*(volatile uint32_t *)0x40037108) // Timer Control Register |
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#define PIT_TCTRL0 (*(volatile uint32_t *)0x40037108) // Timer Control Register |
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#define PIT_TCTRL_CHN (1<<2) // Chain Mode |
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#define PIT_TCTRL_TIE (1<<1) // Timer Interrupt Enable |
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#define PIT_TCTRL_TEN (1<<0) // Timer Enable |
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#define PIT_TFLG0 (*(volatile uint32_t *)0x4003710C) // Timer Flag Register |
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#define PIT_TFLG0 (*(volatile uint32_t *)0x4003710C) // Timer Flag Register |
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#define PIT_TFLG_TIF (1<<0) // Timer Interrupt Flag (write 1 to clear) |
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#define PIT_LDVAL1 (*(volatile uint32_t *)0x40037110) // Timer Load Value Register |
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#define PIT_LDVAL1 (*(volatile uint32_t *)0x40037110) // Timer Load Value Register |
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#define PIT_CVAL1 (*(volatile uint32_t *)0x40037114) // Current Timer Value Register |
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#define PIT_CVAL1 (*(volatile uint32_t *)0x40037114) // Current Timer Value Register |
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#define PIT_TCTRL1 (*(volatile uint32_t *)0x40037118) // Timer Control Register |
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#define PIT_TCTRL1 (*(volatile uint32_t *)0x40037118) // Timer Control Register |
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#define PIT_TFLG1 (*(volatile uint32_t *)0x4003711C) // Timer Flag Register |
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#define PIT_TFLG1 (*(volatile uint32_t *)0x4003711C) // Timer Flag Register |
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#if defined(KINETISK) // the 3.1 has 4 PITs, LC has only 2 |
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#define PIT_LDVAL2 (*(volatile uint32_t *)0x40037120) // Timer Load Value Register |
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#define PIT_LDVAL2 (*(volatile uint32_t *)0x40037120) // Timer Load Value Register |
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#define PIT_CVAL2 (*(volatile uint32_t *)0x40037124) // Current Timer Value Register |
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#define PIT_CVAL2 (*(volatile uint32_t *)0x40037124) // Current Timer Value Register |
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#define PIT_TCTRL2 (*(volatile uint32_t *)0x40037128) // Timer Control Register |
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#define PIT_TCTRL2 (*(volatile uint32_t *)0x40037128) // Timer Control Register |
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#define PIT_CVAL3 (*(volatile uint32_t *)0x40037134) // Current Timer Value Register |
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#define PIT_CVAL3 (*(volatile uint32_t *)0x40037134) // Current Timer Value Register |
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#define PIT_TCTRL3 (*(volatile uint32_t *)0x40037138) // Timer Control Register |
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#define PIT_TCTRL3 (*(volatile uint32_t *)0x40037138) // Timer Control Register |
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#define PIT_TFLG3 (*(volatile uint32_t *)0x4003713C) // Timer Flag Register |
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#define PIT_TFLG3 (*(volatile uint32_t *)0x4003713C) // Timer Flag Register |
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#endif // defined(KINETISK) |
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// Chapter 37: Low-Power Timer (LPTMR) |
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// Chapter 37: Low-Power Timer (LPTMR) |
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#define LPTMR0_CSR (*(volatile uint32_t *)0x40040000) // Low Power Timer Control Status Register |
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#define LPTMR0_CSR (*(volatile uint32_t *)0x40040000) // Low Power Timer Control Status Register |