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#if defined(__IMXRT1062__) |
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#if defined(__IMXRT1062__) |
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#define CORE_NUM_TOTAL_PINS 34 |
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#define CORE_NUM_DIGITAL 34 |
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#define CORE_NUM_INTERRUPT 34 |
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#define CORE_NUM_TOTAL_PINS 40 |
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#define CORE_NUM_DIGITAL 40 |
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#define CORE_NUM_INTERRUPT 40 |
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#define CORE_NUM_ANALOG 14 |
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#define CORE_NUM_ANALOG 14 |
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#define CORE_NUM_PWM 27 |
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#define CORE_NUM_PWM 27 |
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#define CORE_PIN31_BIT 23 |
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#define CORE_PIN31_BIT 23 |
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#define CORE_PIN32_BIT 12 |
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#define CORE_PIN32_BIT 12 |
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#define CORE_PIN33_BIT 7 |
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#define CORE_PIN33_BIT 7 |
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#define CORE_PIN34_BIT 15 |
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#define CORE_PIN35_BIT 14 |
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#define CORE_PIN36_BIT 13 |
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#define CORE_PIN37_BIT 12 |
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#define CORE_PIN38_BIT 17 |
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#define CORE_PIN39_BIT 16 |
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#define CORE_PIN0_BITMASK (1<<(CORE_PIN0_BIT)) |
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#define CORE_PIN0_BITMASK (1<<(CORE_PIN0_BIT)) |
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#define CORE_PIN1_BITMASK (1<<(CORE_PIN1_BIT)) |
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#define CORE_PIN1_BITMASK (1<<(CORE_PIN1_BIT)) |
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#define CORE_PIN31_BITMASK (1<<(CORE_PIN31_BIT)) |
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#define CORE_PIN31_BITMASK (1<<(CORE_PIN31_BIT)) |
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#define CORE_PIN32_BITMASK (1<<(CORE_PIN32_BIT)) |
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#define CORE_PIN32_BITMASK (1<<(CORE_PIN32_BIT)) |
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#define CORE_PIN33_BITMASK (1<<(CORE_PIN33_BIT)) |
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#define CORE_PIN33_BITMASK (1<<(CORE_PIN33_BIT)) |
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#define CORE_PIN34_BITMASK (1<<(CORE_PIN34_BIT)) |
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#define CORE_PIN35_BITMASK (1<<(CORE_PIN35_BIT)) |
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#define CORE_PIN36_BITMASK (1<<(CORE_PIN36_BIT)) |
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#define CORE_PIN37_BITMASK (1<<(CORE_PIN37_BIT)) |
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#define CORE_PIN38_BITMASK (1<<(CORE_PIN38_BIT)) |
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#define CORE_PIN39_BITMASK (1<<(CORE_PIN39_BIT)) |
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#define CORE_PIN0_PORTREG GPIO1_DR |
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#define CORE_PIN0_PORTREG GPIO1_DR |
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#define CORE_PIN1_PORTREG GPIO1_DR |
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#define CORE_PIN1_PORTREG GPIO1_DR |
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#define CORE_PIN31_PORTREG GPIO4_DR |
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#define CORE_PIN31_PORTREG GPIO4_DR |
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#define CORE_PIN32_PORTREG GPIO2_DR |
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#define CORE_PIN32_PORTREG GPIO2_DR |
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#define CORE_PIN33_PORTREG GPIO4_DR |
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#define CORE_PIN33_PORTREG GPIO4_DR |
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#define CORE_PIN34_PORTREG GPIO3_DR |
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#define CORE_PIN35_PORTREG GPIO3_DR |
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#define CORE_PIN36_PORTREG GPIO3_DR |
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#define CORE_PIN37_PORTREG GPIO3_DR |
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#define CORE_PIN38_PORTREG GPIO3_DR |
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#define CORE_PIN39_PORTREG GPIO3_DR |
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#define CORE_PIN0_PORTSET GPIO1_DR_SET |
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#define CORE_PIN0_PORTSET GPIO1_DR_SET |
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#define CORE_PIN1_PORTSET GPIO1_DR_SET |
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#define CORE_PIN1_PORTSET GPIO1_DR_SET |
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#define CORE_PIN31_PORTSET GPIO4_DR_SET |
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#define CORE_PIN31_PORTSET GPIO4_DR_SET |
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#define CORE_PIN32_PORTSET GPIO2_DR_SET |
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#define CORE_PIN32_PORTSET GPIO2_DR_SET |
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#define CORE_PIN33_PORTSET GPIO4_DR_SET |
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#define CORE_PIN33_PORTSET GPIO4_DR_SET |
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#define CORE_PIN34_PORTSET GPIO3_DR_SET |
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#define CORE_PIN35_PORTSET GPIO3_DR_SET |
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#define CORE_PIN36_PORTSET GPIO3_DR_SET |
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#define CORE_PIN37_PORTSET GPIO3_DR_SET |
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#define CORE_PIN38_PORTSET GPIO3_DR_SET |
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#define CORE_PIN39_PORTSET GPIO3_DR_SET |
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#define CORE_PIN0_PORTCLEAR GPIO1_DR_CLEAR |
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#define CORE_PIN0_PORTCLEAR GPIO1_DR_CLEAR |
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#define CORE_PIN1_PORTCLEAR GPIO1_DR_CLEAR |
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#define CORE_PIN1_PORTCLEAR GPIO1_DR_CLEAR |
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#define CORE_PIN31_PORTCLEAR GPIO4_DR_CLEAR |
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#define CORE_PIN31_PORTCLEAR GPIO4_DR_CLEAR |
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#define CORE_PIN32_PORTCLEAR GPIO2_DR_CLEAR |
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#define CORE_PIN32_PORTCLEAR GPIO2_DR_CLEAR |
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#define CORE_PIN33_PORTCLEAR GPIO4_DR_CLEAR |
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#define CORE_PIN33_PORTCLEAR GPIO4_DR_CLEAR |
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#define CORE_PIN34_PORTCLEAR GPIO3_DR_CLEAR |
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#define CORE_PIN35_PORTCLEAR GPIO3_DR_CLEAR |
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#define CORE_PIN36_PORTCLEAR GPIO3_DR_CLEAR |
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#define CORE_PIN37_PORTCLEAR GPIO3_DR_CLEAR |
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#define CORE_PIN38_PORTCLEAR GPIO3_DR_CLEAR |
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#define CORE_PIN39_PORTCLEAR GPIO3_DR_CLEAR |
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#define CORE_PIN0_DDRREG GPIO1_GDIR |
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#define CORE_PIN0_DDRREG GPIO1_GDIR |
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#define CORE_PIN1_DDRREG GPIO1_GDIR |
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#define CORE_PIN1_DDRREG GPIO1_GDIR |
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#define CORE_PIN31_DDRREG GPIO4_GDIR |
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#define CORE_PIN31_DDRREG GPIO4_GDIR |
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#define CORE_PIN32_DDRREG GPIO2_GDIR |
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#define CORE_PIN32_DDRREG GPIO2_GDIR |
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#define CORE_PIN33_DDRREG GPIO4_GDIR |
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#define CORE_PIN33_DDRREG GPIO4_GDIR |
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#define CORE_PIN34_DDRREG GPIO3_GDIR |
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#define CORE_PIN35_DDRREG GPIO3_GDIR |
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#define CORE_PIN36_DDRREG GPIO3_GDIR |
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#define CORE_PIN37_DDRREG GPIO3_GDIR |
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#define CORE_PIN38_DDRREG GPIO3_GDIR |
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#define CORE_PIN39_DDRREG GPIO3_GDIR |
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#define CORE_PIN0_PINREG GPIO1_PSR |
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#define CORE_PIN0_PINREG GPIO1_PSR |
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#define CORE_PIN1_PINREG GPIO1_PSR |
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#define CORE_PIN1_PINREG GPIO1_PSR |
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#define CORE_PIN31_PINREG GPIO4_PSR |
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#define CORE_PIN31_PINREG GPIO4_PSR |
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#define CORE_PIN32_PINREG GPIO2_PSR |
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#define CORE_PIN32_PINREG GPIO2_PSR |
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#define CORE_PIN33_PINREG GPIO4_PSR |
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#define CORE_PIN33_PINREG GPIO4_PSR |
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#define CORE_PIN34_PINREG GPIO3_PSR |
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#define CORE_PIN35_PINREG GPIO3_PSR |
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#define CORE_PIN36_PINREG GPIO3_PSR |
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#define CORE_PIN37_PINREG GPIO3_PSR |
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#define CORE_PIN38_PINREG GPIO3_PSR |
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#define CORE_PIN39_PINREG GPIO3_PSR |
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// mux config registers control which peripheral uses the pin |
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// mux config registers control which peripheral uses the pin |
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#define CORE_PIN0_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 |
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#define CORE_PIN0_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 |
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#define CORE_PIN31_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 |
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#define CORE_PIN31_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 |
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#define CORE_PIN32_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12 |
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#define CORE_PIN32_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12 |
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#define CORE_PIN33_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 |
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#define CORE_PIN33_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 |
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#define CORE_PIN34_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 |
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#define CORE_PIN35_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 |
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#define CORE_PIN36_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 |
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#define CORE_PIN37_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 |
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#define CORE_PIN38_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 |
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#define CORE_PIN39_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 |
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// pad config registers control pullup/pulldown/keeper, drive strength, etc |
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// pad config registers control pullup/pulldown/keeper, drive strength, etc |
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#define CORE_PIN0_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 |
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#define CORE_PIN0_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 |
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#define CORE_PIN31_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 |
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#define CORE_PIN31_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 |
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#define CORE_PIN32_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12 |
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#define CORE_PIN32_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12 |
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#define CORE_PIN33_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 |
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#define CORE_PIN33_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 |
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#define CORE_PIN34_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 |
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#define CORE_PIN35_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 |
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#define CORE_PIN36_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 |
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#define CORE_PIN37_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 |
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#define CORE_PIN38_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 |
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#define CORE_PIN39_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 |
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#define CORE_LED0_PIN 13 |
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#define CORE_LED0_PIN 13 |
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#define CORE_RXD0_PIN 0 |
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#define CORE_RXD0_PIN 0 |
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#define CORE_TXD0_PIN 1 |
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#define CORE_TXD0_PIN 1 |
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#define CORE_RXD1_PIN 6 |
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#define CORE_TXD1_PIN 7 |
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#define CORE_RXD1_PIN 7 |
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#define CORE_TXD1_PIN 8 |
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#define CORE_RXD2_PIN 15 |
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#define CORE_RXD2_PIN 15 |
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#define CORE_TXD2_PIN 14 |
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#define CORE_TXD2_PIN 14 |
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#define CORE_RXD3_PIN 16 |
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#define CORE_RXD3_PIN 16 |
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#define CORE_INT31_PIN 31 |
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#define CORE_INT31_PIN 31 |
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#define CORE_INT32_PIN 32 |
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#define CORE_INT32_PIN 32 |
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#define CORE_INT33_PIN 33 |
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#define CORE_INT33_PIN 33 |
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#define CORE_INT34_PIN 34 |
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#define CORE_INT35_PIN 35 |
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#define CORE_INT36_PIN 36 |
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#define CORE_INT37_PIN 37 |
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#define CORE_INT38_PIN 38 |
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#define CORE_INT39_PIN 39 |
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#define CORE_INT_EVERY_PIN 1 |
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#define CORE_INT_EVERY_PIN 1 |
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CORE_PIN32_PORTSET = CORE_PIN32_BITMASK; |
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CORE_PIN32_PORTSET = CORE_PIN32_BITMASK; |
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} else if (pin == 33) { |
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} else if (pin == 33) { |
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CORE_PIN33_PORTSET = CORE_PIN33_BITMASK; |
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CORE_PIN33_PORTSET = CORE_PIN33_BITMASK; |
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#if defined(__IMXRT1062__) |
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} else if (pin == 34) { |
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CORE_PIN34_PORTSET = CORE_PIN34_BITMASK; |
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} else if (pin == 35) { |
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CORE_PIN35_PORTSET = CORE_PIN35_BITMASK; |
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} else if (pin == 36) { |
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CORE_PIN36_PORTSET = CORE_PIN36_BITMASK; |
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} else if (pin == 37) { |
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CORE_PIN37_PORTSET = CORE_PIN37_BITMASK; |
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} else if (pin == 38) { |
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CORE_PIN38_PORTSET = CORE_PIN38_BITMASK; |
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} else if (pin == 39) { |
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CORE_PIN39_PORTSET = CORE_PIN39_BITMASK; |
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#endif |
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} |
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} |
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} else { |
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} else { |
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if (pin == 0) { |
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if (pin == 0) { |
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CORE_PIN32_PORTCLEAR = CORE_PIN32_BITMASK; |
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CORE_PIN32_PORTCLEAR = CORE_PIN32_BITMASK; |
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} else if (pin == 33) { |
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} else if (pin == 33) { |
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CORE_PIN33_PORTCLEAR = CORE_PIN33_BITMASK; |
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CORE_PIN33_PORTCLEAR = CORE_PIN33_BITMASK; |
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#if defined(__IMXRT1062__) |
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} else if (pin == 34) { |
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CORE_PIN34_PORTCLEAR = CORE_PIN34_BITMASK; |
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} else if (pin == 35) { |
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CORE_PIN35_PORTCLEAR = CORE_PIN35_BITMASK; |
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} else if (pin == 36) { |
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CORE_PIN36_PORTCLEAR = CORE_PIN36_BITMASK; |
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} else if (pin == 37) { |
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CORE_PIN37_PORTCLEAR = CORE_PIN37_BITMASK; |
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} else if (pin == 38) { |
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CORE_PIN38_PORTCLEAR = CORE_PIN38_BITMASK; |
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} else if (pin == 39) { |
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CORE_PIN39_PORTCLEAR = CORE_PIN39_BITMASK; |
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#endif |
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} |
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} |
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} |
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} |
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} else { |
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} else { |