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#define CORE_PIN33_PINREG GPIO4_PSR |
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#define CORE_PIN33_PINREG GPIO4_PSR |
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// mux config registers control which peripheral uses the pin |
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// mux config registers control which peripheral uses the pin |
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#define CORE_PIN0_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 |
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#define CORE_PIN1_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 |
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#define CORE_PIN0_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 |
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#define CORE_PIN1_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 |
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#define CORE_PIN2_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 |
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#define CORE_PIN2_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 |
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#define CORE_PIN3_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 |
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#define CORE_PIN3_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 |
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#define CORE_PIN4_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 |
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#define CORE_PIN4_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 |