Use fast GPIO registers on IMXRT1062, probably breaks attachInterrupt

teensy4/core_pins.h

@@ -138,6 +138,217 @@
 #define CORE_PIN38_BITMASK	(1<<(CORE_PIN38_BIT))
 #define CORE_PIN39_BITMASK	(1<<(CORE_PIN39_BIT))
 
+
+#if 1
+// Fast GPIO
+#define CORE_PIN0_PORTREG	GPIO6_DR
+#define CORE_PIN1_PORTREG	GPIO6_DR
+#define CORE_PIN2_PORTREG	GPIO9_DR
+#define CORE_PIN3_PORTREG	GPIO9_DR
+#define CORE_PIN4_PORTREG	GPIO9_DR
+#define CORE_PIN5_PORTREG	GPIO9_DR
+#define CORE_PIN6_PORTREG	GPIO7_DR
+#define CORE_PIN7_PORTREG	GPIO7_DR
+#define CORE_PIN8_PORTREG	GPIO7_DR
+#define CORE_PIN9_PORTREG	GPIO7_DR
+#define CORE_PIN10_PORTREG	GPIO7_DR
+#define CORE_PIN11_PORTREG	GPIO7_DR
+#define CORE_PIN12_PORTREG	GPIO7_DR
+#define CORE_PIN13_PORTREG	GPIO7_DR
+#define CORE_PIN14_PORTREG	GPIO6_DR
+#define CORE_PIN15_PORTREG	GPIO6_DR
+#define CORE_PIN16_PORTREG	GPIO6_DR
+#define CORE_PIN17_PORTREG	GPIO6_DR
+#define CORE_PIN18_PORTREG	GPIO6_DR
+#define CORE_PIN19_PORTREG	GPIO6_DR
+#define CORE_PIN20_PORTREG	GPIO6_DR
+#define CORE_PIN21_PORTREG	GPIO6_DR
+#define CORE_PIN22_PORTREG	GPIO6_DR
+#define CORE_PIN23_PORTREG	GPIO6_DR
+#define CORE_PIN24_PORTREG	GPIO6_DR
+#define CORE_PIN25_PORTREG	GPIO6_DR
+#define CORE_PIN26_PORTREG	GPIO6_DR
+#define CORE_PIN27_PORTREG	GPIO6_DR
+#define CORE_PIN28_PORTREG	GPIO8_DR
+#define CORE_PIN29_PORTREG	GPIO9_DR
+#define CORE_PIN30_PORTREG	GPIO9_DR
+#define CORE_PIN31_PORTREG	GPIO9_DR
+#define CORE_PIN32_PORTREG	GPIO7_DR
+#define CORE_PIN33_PORTREG	GPIO9_DR
+#define CORE_PIN34_PORTREG	GPIO8_DR
+#define CORE_PIN35_PORTREG	GPIO8_DR
+#define CORE_PIN36_PORTREG	GPIO8_DR
+#define CORE_PIN37_PORTREG	GPIO8_DR
+#define CORE_PIN38_PORTREG	GPIO8_DR
+#define CORE_PIN39_PORTREG	GPIO8_DR
+
+#define CORE_PIN0_PORTSET	GPIO6_DR_SET
+#define CORE_PIN1_PORTSET	GPIO6_DR_SET
+#define CORE_PIN2_PORTSET	GPIO9_DR_SET
+#define CORE_PIN3_PORTSET	GPIO9_DR_SET
+#define CORE_PIN4_PORTSET	GPIO9_DR_SET
+#define CORE_PIN5_PORTSET	GPIO9_DR_SET
+#define CORE_PIN6_PORTSET	GPIO7_DR_SET
+#define CORE_PIN7_PORTSET	GPIO7_DR_SET
+#define CORE_PIN8_PORTSET	GPIO7_DR_SET
+#define CORE_PIN9_PORTSET	GPIO7_DR_SET
+#define CORE_PIN10_PORTSET	GPIO7_DR_SET
+#define CORE_PIN11_PORTSET	GPIO7_DR_SET
+#define CORE_PIN12_PORTSET	GPIO7_DR_SET
+#define CORE_PIN13_PORTSET	GPIO7_DR_SET
+#define CORE_PIN14_PORTSET	GPIO6_DR_SET
+#define CORE_PIN15_PORTSET	GPIO6_DR_SET
+#define CORE_PIN16_PORTSET	GPIO6_DR_SET
+#define CORE_PIN17_PORTSET	GPIO6_DR_SET
+#define CORE_PIN18_PORTSET	GPIO6_DR_SET
+#define CORE_PIN19_PORTSET	GPIO6_DR_SET
+#define CORE_PIN20_PORTSET	GPIO6_DR_SET
+#define CORE_PIN21_PORTSET	GPIO6_DR_SET
+#define CORE_PIN22_PORTSET	GPIO6_DR_SET
+#define CORE_PIN23_PORTSET	GPIO6_DR_SET
+#define CORE_PIN24_PORTSET	GPIO6_DR_SET
+#define CORE_PIN25_PORTSET	GPIO6_DR_SET
+#define CORE_PIN26_PORTSET	GPIO6_DR_SET
+#define CORE_PIN27_PORTSET	GPIO6_DR_SET
+#define CORE_PIN28_PORTSET	GPIO8_DR_SET
+#define CORE_PIN29_PORTSET	GPIO9_DR_SET
+#define CORE_PIN30_PORTSET	GPIO9_DR_SET
+#define CORE_PIN31_PORTSET	GPIO9_DR_SET
+#define CORE_PIN32_PORTSET	GPIO7_DR_SET
+#define CORE_PIN33_PORTSET	GPIO9_DR_SET
+#define CORE_PIN34_PORTSET	GPIO8_DR_SET
+#define CORE_PIN35_PORTSET	GPIO8_DR_SET
+#define CORE_PIN36_PORTSET	GPIO8_DR_SET
+#define CORE_PIN37_PORTSET	GPIO8_DR_SET
+#define CORE_PIN38_PORTSET	GPIO8_DR_SET
+#define CORE_PIN39_PORTSET	GPIO8_DR_SET
+
+#define CORE_PIN0_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN1_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN2_PORTCLEAR	GPIO9_DR_CLEAR
+#define CORE_PIN3_PORTCLEAR	GPIO9_DR_CLEAR
+#define CORE_PIN4_PORTCLEAR	GPIO9_DR_CLEAR
+#define CORE_PIN5_PORTCLEAR	GPIO9_DR_CLEAR
+#define CORE_PIN6_PORTCLEAR	GPIO7_DR_CLEAR
+#define CORE_PIN7_PORTCLEAR	GPIO7_DR_CLEAR
+#define CORE_PIN8_PORTCLEAR	GPIO7_DR_CLEAR
+#define CORE_PIN9_PORTCLEAR	GPIO7_DR_CLEAR
+#define CORE_PIN10_PORTCLEAR	GPIO7_DR_CLEAR
+#define CORE_PIN11_PORTCLEAR	GPIO7_DR_CLEAR
+#define CORE_PIN12_PORTCLEAR	GPIO7_DR_CLEAR
+#define CORE_PIN13_PORTCLEAR	GPIO7_DR_CLEAR
+#define CORE_PIN14_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN15_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN16_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN17_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN18_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN19_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN20_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN21_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN22_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN23_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN24_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN25_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN26_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN27_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN28_PORTCLEAR	GPIO8_DR_CLEAR
+#define CORE_PIN29_PORTCLEAR	GPIO9_DR_CLEAR
+#define CORE_PIN30_PORTCLEAR	GPIO9_DR_CLEAR
+#define CORE_PIN31_PORTCLEAR	GPIO9_DR_CLEAR
+#define CORE_PIN32_PORTCLEAR	GPIO7_DR_CLEAR
+#define CORE_PIN33_PORTCLEAR	GPIO9_DR_CLEAR
+#define CORE_PIN34_PORTCLEAR	GPIO8_DR_CLEAR
+#define CORE_PIN35_PORTCLEAR	GPIO8_DR_CLEAR
+#define CORE_PIN36_PORTCLEAR	GPIO8_DR_CLEAR
+#define CORE_PIN37_PORTCLEAR	GPIO8_DR_CLEAR
+#define CORE_PIN38_PORTCLEAR	GPIO8_DR_CLEAR
+#define CORE_PIN39_PORTCLEAR	GPIO8_DR_CLEAR
+
+#define CORE_PIN0_DDRREG	GPIO6_GDIR
+#define CORE_PIN1_DDRREG	GPIO6_GDIR
+#define CORE_PIN2_DDRREG	GPIO9_GDIR
+#define CORE_PIN3_DDRREG	GPIO9_GDIR
+#define CORE_PIN4_DDRREG	GPIO9_GDIR
+#define CORE_PIN5_DDRREG	GPIO9_GDIR
+#define CORE_PIN6_DDRREG	GPIO7_GDIR
+#define CORE_PIN7_DDRREG	GPIO7_GDIR
+#define CORE_PIN8_DDRREG	GPIO7_GDIR
+#define CORE_PIN9_DDRREG	GPIO7_GDIR
+#define CORE_PIN10_DDRREG	GPIO7_GDIR
+#define CORE_PIN11_DDRREG	GPIO7_GDIR
+#define CORE_PIN12_DDRREG	GPIO7_GDIR
+#define CORE_PIN13_DDRREG	GPIO7_GDIR
+#define CORE_PIN14_DDRREG	GPIO6_GDIR
+#define CORE_PIN15_DDRREG	GPIO6_GDIR
+#define CORE_PIN16_DDRREG	GPIO6_GDIR
+#define CORE_PIN17_DDRREG	GPIO6_GDIR
+#define CORE_PIN18_DDRREG	GPIO6_GDIR
+#define CORE_PIN19_DDRREG	GPIO6_GDIR
+#define CORE_PIN20_DDRREG	GPIO6_GDIR
+#define CORE_PIN21_DDRREG	GPIO6_GDIR
+#define CORE_PIN22_DDRREG	GPIO6_GDIR
+#define CORE_PIN23_DDRREG	GPIO6_GDIR
+#define CORE_PIN24_DDRREG	GPIO6_GDIR
+#define CORE_PIN25_DDRREG	GPIO6_GDIR
+#define CORE_PIN26_DDRREG	GPIO6_GDIR
+#define CORE_PIN27_DDRREG	GPIO6_GDIR
+#define CORE_PIN28_DDRREG	GPIO8_GDIR
+#define CORE_PIN29_DDRREG	GPIO9_GDIR
+#define CORE_PIN30_DDRREG	GPIO9_GDIR
+#define CORE_PIN31_DDRREG	GPIO9_GDIR
+#define CORE_PIN32_DDRREG	GPIO7_GDIR
+#define CORE_PIN33_DDRREG	GPIO9_GDIR
+#define CORE_PIN34_DDRREG	GPIO8_GDIR
+#define CORE_PIN35_DDRREG	GPIO8_GDIR
+#define CORE_PIN36_DDRREG	GPIO8_GDIR
+#define CORE_PIN37_DDRREG	GPIO8_GDIR
+#define CORE_PIN38_DDRREG	GPIO8_GDIR
+#define CORE_PIN39_DDRREG	GPIO8_GDIR
+
+#define CORE_PIN0_PINREG	GPIO6_PSR
+#define CORE_PIN1_PINREG	GPIO6_PSR
+#define CORE_PIN2_PINREG	GPIO9_PSR
+#define CORE_PIN3_PINREG	GPIO9_PSR
+#define CORE_PIN4_PINREG	GPIO9_PSR
+#define CORE_PIN5_PINREG	GPIO9_PSR
+#define CORE_PIN6_PINREG	GPIO7_PSR
+#define CORE_PIN7_PINREG	GPIO7_PSR
+#define CORE_PIN8_PINREG	GPIO7_PSR
+#define CORE_PIN9_PINREG	GPIO7_PSR
+#define CORE_PIN10_PINREG	GPIO7_PSR
+#define CORE_PIN11_PINREG	GPIO7_PSR
+#define CORE_PIN12_PINREG	GPIO7_PSR
+#define CORE_PIN13_PINREG	GPIO7_PSR
+#define CORE_PIN14_PINREG	GPIO6_PSR
+#define CORE_PIN15_PINREG	GPIO6_PSR
+#define CORE_PIN16_PINREG	GPIO6_PSR
+#define CORE_PIN17_PINREG	GPIO6_PSR
+#define CORE_PIN18_PINREG	GPIO6_PSR
+#define CORE_PIN19_PINREG	GPIO6_PSR
+#define CORE_PIN20_PINREG	GPIO6_PSR
+#define CORE_PIN21_PINREG	GPIO6_PSR
+#define CORE_PIN22_PINREG	GPIO6_PSR
+#define CORE_PIN23_PINREG	GPIO6_PSR
+#define CORE_PIN24_PINREG	GPIO6_PSR
+#define CORE_PIN25_PINREG	GPIO6_PSR
+#define CORE_PIN26_PINREG	GPIO6_PSR
+#define CORE_PIN27_PINREG	GPIO6_PSR
+#define CORE_PIN28_PINREG	GPIO8_PSR
+#define CORE_PIN29_PINREG	GPIO9_PSR
+#define CORE_PIN30_PINREG	GPIO9_PSR
+#define CORE_PIN31_PINREG	GPIO9_PSR
+#define CORE_PIN32_PINREG	GPIO7_PSR
+#define CORE_PIN33_PINREG	GPIO9_PSR
+#define CORE_PIN34_PINREG	GPIO8_PSR
+#define CORE_PIN35_PINREG	GPIO8_PSR
+#define CORE_PIN36_PINREG	GPIO8_PSR
+#define CORE_PIN37_PINREG	GPIO8_PSR
+#define CORE_PIN38_PINREG	GPIO8_PSR
+#define CORE_PIN39_PINREG	GPIO8_PSR
+
+
+#else
+// Slow GPIO
 #define CORE_PIN0_PORTREG	GPIO1_DR
 #define CORE_PIN1_PORTREG	GPIO1_DR
 #define CORE_PIN2_PORTREG	GPIO4_DR
@@ -342,6 +553,8 @@
 #define CORE_PIN37_PINREG	GPIO3_PSR
 #define CORE_PIN38_PINREG	GPIO3_PSR
 #define CORE_PIN39_PINREG	GPIO3_PSR
+#endif // Slow GPIO
+
 
 // mux config registers control which peripheral uses the pin
 #define CORE_PIN0_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03

teensy4/interrupt.c

@@ -5,6 +5,8 @@
 static void dummy_isr() {};
 typedef void (*voidFuncPtr)(void);
 
+// TODO: Use of Fast GPIO6 - GPIO9 probably breaks everything about attachInterrupt()
+
 // TODO: define these properly in core_pins.h - don't waste memory
 #define CORE_MAX_PIN_PORT1 31
 #define CORE_MAX_PIN_PORT2 31

teensy4/startup.c

@@ -70,6 +70,14 @@ void ResetHandler(void)
 	// UARTs run from 24 MHz clock (works if PLL3 off or bypassed)
 	CCM_CSCDR1 = (CCM_CSCDR1 & ~CCM_CSCDR1_UART_CLK_PODF(0x3F)) | CCM_CSCDR1_UART_CLK_SEL;
 
+#if defined(__IMXRT1062__)
+	// Use fast GPIO6, GPIO7, GPIO8, GPIO9
+	IOMUXC_GPR_GPR26 = 0xFFFFFFFF;
+	IOMUXC_GPR_GPR27 = 0xFFFFFFFF;
+	IOMUXC_GPR_GPR28 = 0xFFFFFFFF;
+	IOMUXC_GPR_GPR29 = 0xFFFFFFFF;
+#endif
+
 	// must enable PRINT_DEBUG_STUFF in debug/print.h
 	printf_debug_init();
 	printf("\n***********IMXRT Startup**********\n");