Group address defines together

teensy4/imxrt.h

@@ -319,6 +319,114 @@ enum IRQ_NUMBER_t {
 #define DMAMUX_SOURCE_ENET2_TIMER0		124
 #define DMAMUX_SOURCE_ENET2_TIMER1		125
 
+#define IMXRT_CMP1_ADDRESS		0x40094000
+#define IMXRT_CMP2_ADDRESS		0x40094008
+#define IMXRT_CMP3_ADDRESS		0x40094010
+#define IMXRT_CMP4_ADDRESS		0x40094018
+#define IMXRT_ADC1_ADDRESS		0x400C4000
+#define IMXRT_ADC2_ADDRESS		0x400C8000
+#define IMXRT_ADC_ETC_ADDRESS		0x403B0000
+#define IMXRT_AIPSTZ1_ADDRESS		0x4007C000
+#define IMXRT_AIPSTZ2_ADDRESS		0x4017C000
+#define IMXRT_AIPSTZ3_ADDRESS		0x4027C000
+#define IMXRT_AIPSTZ4_ADDRESS		0x4037C000
+#define IMXRT_AOI1_ADDRESS		0x403B4000
+#define IMXRT_AOI2_ADDRESS		0x403B8000
+#define IMXRT_CCM_ADDRESS		0x400FC000
+#define IMXRT_CCM_ANALOG_ADDRESS	0x400D8000
+#define IMXRT_CSI_ADDRESS		0x402BC000
+#define IMXRT_DCDC_ADDRESS		0x40080000
+#define IMXRT_DMAMUX_ADDRESS		0x400EC000
+#define IMXRT_DMA_ADDRESS		0x400E8000
+#define IMXRT_ENC1_ADDRESS		0x403C8000
+#define IMXRT_ENC2_ADDRESS		0x403CC000
+#define IMXRT_ENC3_ADDRESS		0x403D0000
+#define IMXRT_ENC4_ADDRESS		0x403D4000
+#define IMXRT_ENET_ADDRESS		0x402D8000
+#define IMXRT_ENET2_ADDRESS		0x402D4000
+#define IMXRT_EWM_ADDRESS		0x400B4000
+#define IMXRT_FLEXCAN1_ADDRESS		0x401D0000
+#define IMXRT_FLEXCAN2_ADDRESS		0x401D4000
+#define IMXRT_FLEXCAN3_ADDRESS		0x401D8000
+#define IMXRT_FLEXIO1_ADDRESS		0x401AC000
+#define IMXRT_FLEXIO2_ADDRESS		0x401B0000
+#define IMXRT_FLEXIO3_ADDRESS		0x42020000
+#define IMXRT_FLEXPWM1_ADDRESS		0x403DC000
+#define IMXRT_FLEXPWM2_ADDRESS		0x403E0000
+#define IMXRT_FLEXPWM3_ADDRESS		0x403E4000
+#define IMXRT_FLEXPWM4_ADDRESS		0x403E8000
+#define IMXRT_FLEXRAM_ADDRESS		0x400B0000
+#define IMXRT_FLEXSPI_ADDRESS		0x402A8000
+#define IMXRT_FLEXSPI2_ADDRESS		0x402A4000
+#define IMXRT_GPC_ADDRESS		0x400F4000
+#define IMXRT_GPIO1_ADDRESS		0x401B8000
+#define IMXRT_GPIO2_ADDRESS		0x401BC000
+#define IMXRT_GPIO3_ADDRESS		0x401C0000
+#define IMXRT_GPIO4_ADDRESS		0x401C4000
+#define IMXRT_GPIO5_ADDRESS		0x400C0000
+#define IMXRT_GPIO6_ADDRESS		0x42000000
+#define IMXRT_GPIO7_ADDRESS		0x42004000
+#define IMXRT_GPIO8_ADDRESS		0x42008000
+#define IMXRT_GPIO9_ADDRESS		0x4200C000
+#define IMXRT_GPT1_ADDRESS		0x401EC000
+#define IMXRT_GPT2_ADDRESS		0x401F0000
+#define IMXRT_IOMUXC_GPR_ADDRESS	0x400AC000
+#define IMXRT_IOMUXC_SNVS_ADDRESS	0x400A8000
+#define IMXRT_IOMUXC_SNVS_GPR_ADDRESS	0x400A4000
+#define IMXRT_IOMUXC_ADDRESS		0x401F8000
+#define IMXRT_KPP_ADDRESS		0x401FC000
+#define IMXRT_LCDIF_ADDRESS		0x402B8000
+#define IMXRT_LPI2C1_ADDRESS		0x403F0000
+#define IMXRT_LPI2C2_ADDRESS		0x403F4000
+#define IMXRT_LPI2C3_ADDRESS		0x403F8000
+#define IMXRT_LPI2C4_ADDRESS		0x403FC000
+#define IMXRT_LPSPI1_ADDRESS		0x40394000
+#define IMXRT_LPSPI2_ADDRESS		0x40398000
+#define IMXRT_LPSPI3_ADDRESS		0x4039C000
+#define IMXRT_LPSPI4_ADDRESS		0x403A0000
+#define IMXRT_LPUART1_ADDRESS		0x40184000
+#define IMXRT_LPUART2_ADDRESS		0x40188000
+#define IMXRT_LPUART3_ADDRESS		0x4018C000
+#define IMXRT_LPUART4_ADDRESS		0x40190000
+#define IMXRT_LPUART5_ADDRESS		0x40194000
+#define IMXRT_LPUART6_ADDRESS		0x40198000
+#define IMXRT_LPUART7_ADDRESS		0x4019C000
+#define IMXRT_LPUART8_ADDRESS		0x401A0000
+#define IMXRT_OCOTP_ADDRESS		0x401F4000
+#define IMXRT_PIT_ADDRESS		0x40084000
+#define IMXRT_PMU_ADDRESS		0x400D8000
+#define IMXRT_PXP_ADDRESS		0x402B4000
+#define IMXRT_TMR1_ADDRESS		0x401DC000
+#define IMXRT_TMR2_ADDRESS		0x401E0000
+#define IMXRT_TMR3_ADDRESS		0x401E4000
+#define IMXRT_TMR4_ADDRESS		0x401E8000
+#define IMXRT_I2S1_ADDRESS		0x40384000
+#define IMXRT_I2S2_ADDRESS		0x40388000
+#define IMXRT_I2S3_ADDRESS		0x4038C000
+#define IMXRT_SEMC_ADDRESS		0x402F0000
+#define IMXRT_SNVS_ADDRESS		0x400D4000
+#define IMXRT_SPDIF_ADDRESS		0x40380000
+#define IMXRT_SRC_ADDRESS		0x400F8000
+#define IMXRT_TEMPMON_ADDRESS		0x400D8180
+#define IMXRT_TRNG_ADDRESS		0x400CC000
+#define IMXRT_TSC_ADDRESS		0x400E0000
+#define IMXRT_USB1_ADDRESS		0x402E0000
+#define IMXRT_USB2_ADDRESS		0x402E0200
+#define IMXRT_USBPHY1_ADDRESS		0x400D9000
+#define IMXRT_USBPHY2_ADDRESS		0x400DA000
+#define IMXRT_USDHC1_ADDRESS		0x402C0000
+#define IMXRT_USDHC2_ADDRESS		0x402C4000
+#define IMXRT_WDOG1_ADDRESS		0x400B8000
+#define IMXRT_WDOG2_ADDRESS		0x400D0000
+#define IMXRT_WDOG3_ADDRESS		0x400BC000
+#define IMXRT_XBARA1_ADDRESS		0x403BC000
+#define IMXRT_XBARB2_ADDRESS		0x403C0000
+#define IMXRT_XBARB3_ADDRESS		0x403C4000
+#define IMXRT_XTALOSC24M_ADDRESS	0x400D8000
+
+
+
+
 
 #ifdef __cplusplus
 extern "C" void (* _VectorsRam[NVIC_NUM_INTERRUPTS+16])(void);
@@ -868,7 +976,6 @@ typedef struct {
 } IMXRT_REGISTER8_t;
 
 // 65.3: page 3302
-#define IMXRT_CMP1_ADDRESS	0x40094000
 #define IMXRT_CMP1		(*(IMXRT_REGISTER8_t *)IMXRT_CMP1_ADDRESS)
 #define CMP1_CR0			(IMXRT_CMP1.offset00)
 #define CMP1_CR1			(IMXRT_CMP1.offset01)
@@ -876,7 +983,6 @@ typedef struct {
 #define CMP1_SCR			(IMXRT_CMP1.offset03)
 #define CMP1_DACCR			(IMXRT_CMP1.offset04)
 #define CMP1_MUXCR			(IMXRT_CMP1.offset05)
-#define IMXRT_CMP2_ADDRESS	0x40094008
 #define IMXRT_CMP2		(*(IMXRT_REGISTER8_t *)IMXRT_CMP2_ADDRESS)
 #define CMP2_CR0			(IMXRT_CMP2.offset00)
 #define CMP2_CR1			(IMXRT_CMP2.offset01)
@@ -884,7 +990,6 @@ typedef struct {
 #define CMP2_SCR			(IMXRT_CMP2.offset03)
 #define CMP2_DACCR			(IMXRT_CMP2.offset04)
 #define CMP2_MUXCR			(IMXRT_CMP2.offset05)
-#define IMXRT_CMP3_ADDRESS	0x40094010
 #define IMXRT_CMP3		(*(IMXRT_REGISTER8_t *)IMXRT_CMP3_ADDRESS)
 #define CMP3_CR0			(IMXRT_CMP3.offset00)
 #define CMP3_CR1			(IMXRT_CMP3.offset01)
@@ -892,7 +997,6 @@ typedef struct {
 #define CMP3_SCR			(IMXRT_CMP3.offset03)
 #define CMP3_DACCR			(IMXRT_CMP3.offset04)
 #define CMP3_MUXCR			(IMXRT_CMP3.offset05)
-#define IMXRT_CMP4_ADDRESS	0x40094018
 #define IMXRT_CMP4		(*(IMXRT_REGISTER8_t *)IMXRT_CMP4_ADDRESS)
 #define CMP4_CR0			(IMXRT_CMP4.offset00)
 #define CMP4_CR1			(IMXRT_CMP4.offset01)
@@ -929,7 +1033,6 @@ typedef struct {
 } IMXRT_ADCS_t;
 
 
-#define IMXRT_ADC1_ADDRESS	    0x400C4000
 #define IMXRT_ADC1                  (*(IMXRT_ADCS_t *)IMXRT_ADC1_ADDRESS)
 #define IMXRT_ADC1S                 (*(IMXRT_ADCS_t *)IMXRT_ADC1_ADDRESS)
 #define ADC1_HC0			(IMXRT_ADC1.HC0)
@@ -955,7 +1058,6 @@ typedef struct {
 #define ADC1_CV				(IMXRT_ADC1.CV)
 #define ADC1_OFS			(IMXRT_ADC1.OFS)
 #define ADC1_CAL			(IMXRT_ADC1.CAL)
-#define IMXRT_ADC2_ADDRESS	   0x400C8000
 #define IMXRT_ADC2                 (*(IMXRT_ADCS_t *)IMXRT_ADC2_ADDRESS)
 #define IMXRT_ADC2S                (*(IMXRT_ADCS_t *)IMXRT_ADC2_ADDRESS)
 #define ADC2_HC0			(IMXRT_ADC2.HC0)
@@ -1032,7 +1134,6 @@ typedef struct {
   } TRIG[7];
 } IMXRT_ADC_ETC_t;
 
-#define IMXRT_ADC_ETC_ADDRESS	0x403B0000
 #define IMXRT_ADC_ETC		(*(IMXRT_ADC_ETC_t *)IMXRT_ADC_ETC_ADDRESS)
 #define ADC_ETC_CTRL			(IMXRT_ADC_ETC.CTRL)
 #define ADC_ETC_DONE0_1_IRQ		(IMXRT_ADC_ETC.DONE0_1_IRQ)
@@ -1162,7 +1263,6 @@ typedef struct {
 #define ADC_ETC_TRIG_RESULT_DATA0(n)    ((uint32_t)(((n) & 0xfff) << 0))
 
 // 32.8: page 1778
-#define IMXRT_AIPSTZ1_ADDRESS	0x4007C000
 #define IMXRT_AIPSTZ1		(*(IMXRT_REGISTER32_t *)IMXRT_AIPSTZ1_ADDRESS)
 #define AIPSTZ1_MPR			(IMXRT_AIPSTZ1.offset000)
 #define AIPSTZ1_OPACR			(IMXRT_AIPSTZ1.offset040)
@@ -1170,7 +1270,6 @@ typedef struct {
 #define AIPSTZ1_OPACR2			(IMXRT_AIPSTZ1.offset048)
 #define AIPSTZ1_OPACR3			(IMXRT_AIPSTZ1.offset04C)
 #define AIPSTZ1_OPACR4			(IMXRT_AIPSTZ1.offset050)
-#define IMXRT_AIPSTZ2_ADDRESS	0x4017C000
 #define IMXRT_AIPSTZ2		(*(IMXRT_REGISTER32_t *)IMXRT_AIPSTZ2_ADDRESS)
 #define AIPSTZ2_MPR			(IMXRT_AIPSTZ2.offset000)
 #define AIPSTZ2_OPACR			(IMXRT_AIPSTZ2.offset040)
@@ -1178,7 +1277,6 @@ typedef struct {
 #define AIPSTZ2_OPACR2			(IMXRT_AIPSTZ2.offset048)
 #define AIPSTZ2_OPACR3			(IMXRT_AIPSTZ2.offset04C)
 #define AIPSTZ2_OPACR4			(IMXRT_AIPSTZ2.offset050)
-#define IMXRT_AIPSTZ3_ADDRESS	0x4027C000
 #define IMXRT_AIPSTZ3		(*(IMXRT_REGISTER32_t *)IMXRT_AIPSTZ3_ADDRESS)
 #define AIPSTZ3_MPR			(IMXRT_AIPSTZ3.offset000)
 #define AIPSTZ3_OPACR			(IMXRT_AIPSTZ3.offset040)
@@ -1186,7 +1284,6 @@ typedef struct {
 #define AIPSTZ3_OPACR2			(IMXRT_AIPSTZ3.offset048)
 #define AIPSTZ3_OPACR3			(IMXRT_AIPSTZ3.offset04C)
 #define AIPSTZ3_OPACR4			(IMXRT_AIPSTZ3.offset050)
-#define IMXRT_AIPSTZ4_ADDRESS	0x4037C000
 #define IMXRT_AIPSTZ4		(*(IMXRT_REGISTER32_t *)IMXRT_AIPSTZ4_ADDRESS)
 #define AIPSTZ4_MPR			(IMXRT_AIPSTZ4.offset000)
 #define AIPSTZ4_OPACR			(IMXRT_AIPSTZ4.offset040)
@@ -1196,7 +1293,6 @@ typedef struct {
 #define AIPSTZ4_OPACR4			(IMXRT_AIPSTZ4.offset050)
 
 // 63.4: page 3287
-#define IMXRT_AOI1_ADDRESS	0x403B4000
 #define IMXRT_AOI1		(*(IMXRT_REGISTER16_t *)IMXRT_AOI1_ADDRESS)
 #define AOI1_BFCRT010			(IMXRT_AOI1.offset000)
 #define AOI1_BFCRT230			(IMXRT_AOI1.offset002)
@@ -1206,7 +1302,6 @@ typedef struct {
 #define AOI1_BFCRT232			(IMXRT_AOI1.offset00A)
 #define AOI1_BFCRT013			(IMXRT_AOI1.offset00C)
 #define AOI1_BFCRT233			(IMXRT_AOI1.offset00E)
-#define IMXRT_AOI2_ADDRESS	0x403B8000
 #define IMXRT_AOI2		(*(IMXRT_REGISTER16_t *)IMXRT_AOI2_ADDRESS)
 #define AOI2_BFCRT010			(IMXRT_AOI2.offset000)
 #define AOI2_BFCRT230			(IMXRT_AOI2.offset002)
@@ -1218,7 +1313,6 @@ typedef struct {
 #define AOI2_BFCRT233			(IMXRT_AOI2.offset00E)
 
 // 14.7: page 1045
-#define IMXRT_CCM_ADDRESS	0x400FC000
 #define IMXRT_CCM		(*(IMXRT_REGISTER32_t *))IMXRT_CCM_ADDRESS
 #define CCM_CCR				(IMXRT_CCM.offset000)
 #define CCM_CSR				(IMXRT_CCM.offset008)
@@ -1505,7 +1599,6 @@ typedef struct {
 #define CCM_CDCDR_SPDIF0_CLK_PODF_MASK		(CCM_CDCDR_SPDIF0_CLK_PODF(0x07))
 
 // 14.8: page 1096
-#define IMXRT_CCM_ANALOG_ADDRESS 0x400D8000
 #define IMXRT_CCM_ANALOG	(*(IMXRT_REGISTER32_t *)IMXRT_CCM_ANALOG_ADDRESS)
 #define CCM_ANALOG_PLL_ARM		(IMXRT_CCM_ANALOG.offset000)
 #define CCM_ANALOG_PLL_ARM_SET		(IMXRT_CCM_ANALOG.offset004)
@@ -1657,7 +1750,6 @@ typedef struct {
 
 
 // 34.8: page 1818
-#define IMXRT_CSI_ADDRESS	0x402BC000
 #define IMXRT_CSI		(*(IMXRT_REGISTER32_t *)IMXRT_CSI_ADDRESS)
 #define CSI_CSICR1			(IMXRT_CSI.offset000)
 #define CSI_CSICR2			(IMXRT_CSI.offset004)
@@ -1769,7 +1861,6 @@ typedef struct {
 
 
 // 18.7.1.1: page 1209
-#define IMXRT_DCDC_ADDRESS	0x40080000
 #define IMXRT_DCDC		(*(IMXRT_REGISTER32_t *)IMXRT_DCDC_ADDRESS)
 #define DCDC_REG0			(IMXRT_DCDC.offset000)
 #define DCDC_REG1			(IMXRT_DCDC.offset004)
@@ -1818,7 +1909,6 @@ typedef struct {
 #define DCDC_REG3_TRG_MASK			((uint32_t)(0x1F << 0))
 
 // 5.6.1.1: page 85
-#define IMXRT_DMAMUX_ADDRESS	0x400EC000
 #define IMXRT_DMAMUX		(*(IMXRT_REGISTER32_t *)IMXRT_DMAMUX_ADDRESS)
 #define DMAMUX_CHCFG0			(IMXRT_DMAMUX.offset000)
 #define DMAMUX_CHCFG1			(IMXRT_DMAMUX.offset004)
@@ -1949,7 +2039,6 @@ typedef struct {
 		volatile uint16_t BITER_ELINKNO;
 	};
 } IMXRT_DMA_TCD_t;
-#define IMXRT_DMA_ADDRESS	0x400E8000
 #define IMXRT_DMA		(*(IMXRT_DMA_t *)IMXRT_DMA_ADDRESS)
 #define DMA_CR				(IMXRT_DMA.CR)
 #define DMA_ES				(IMXRT_DMA.ES)
@@ -2714,7 +2803,6 @@ typedef struct {
 } IMXRT_ENC_t;
 
 
-#define IMXRT_ENC1_ADDRESS	0x403C8000
 #define IMXRT_ENC1		(*(IMXRT_ENC_t *)IMXRT_ENC1_ADDRESS)
 #define ENC1_CTRL			(IMXRT_ENC1.CTRL)
 #define ENC1_FILT			(IMXRT_ENC1.FILT)
@@ -2736,7 +2824,6 @@ typedef struct {
 #define ENC1_LMOD			(IMXRT_ENC1.LMOD)
 #define ENC1_UCOMP			(IMXRT_ENC1.UCOMP)
 #define ENC1_LCOMP			(IMXRT_ENC1.LCOMP)
-#define IMXRT_ENC2_ADDRESS	0x403CC000
 #define IMXRT_ENC2		(*(IMXRT_ENC_t *)IMXRT_ENC2_ADDRESS)
 #define ENC2_CTRL			(IMXRT_ENC2.CTRL)
 #define ENC2_FILT			(IMXRT_ENC2.FILT)
@@ -2758,7 +2845,6 @@ typedef struct {
 #define ENC2_LMOD			(IMXRT_ENC2.LMOD)
 #define ENC2_UCOMP			(IMXRT_ENC2.UCOMP)
 #define ENC2_LCOMP			(IMXRT_ENC2.LCOMP)
-#define IMXRT_ENC3_ADDRESS	0x403D0000
 #define IMXRT_ENC3		(*(IMXRT_ENC_t *)IMXRT_ENC3_ADDRESS)
 #define ENC3_CTRL			(IMXRT_ENC3.CTRL)
 #define ENC3_FILT			(IMXRT_ENC3.FILT)
@@ -2780,7 +2866,6 @@ typedef struct {
 #define ENC3_LMOD			(IMXRT_ENC3.LMOD)
 #define ENC3_UCOMP			(IMXRT_ENC3.UCOMP)
 #define ENC3_LCOMP			(IMXRT_ENC3.LCOMP)
-#define IMXRT_ENC4_ADDRESS	0x403D4000
 #define IMXRT_ENC4		(*(IMXRT_ENC_t *)IMXRT_ENC4_ADDRESS)
 #define ENC4_CTRL			(IMXRT_ENC4.CTRL)
 #define ENC4_FILT			(IMXRT_ENC4.FILT)
@@ -2804,7 +2889,6 @@ typedef struct {
 #define ENC4_LCOMP			(IMXRT_ENC4.LCOMP)
 
 // 41.6: page 2068
-#define IMXRT_ENET_ADDRESS	0x402D8000
 #define IMXRT_ENET		(*(IMXRT_REGISTER32_t *)IMXRT_ENET_ADDRESS)
 #define IMXRT_ENET_TIMER	(*(IMXRT_REGISTER32_t *)(IMXRT_ENET_ADDRESS+0x400))
 #define ENET_EIR			(IMXRT_ENET.offset004)
@@ -3009,7 +3093,6 @@ typedef struct {
 #define ENET_RACC_IPDIS				((uint32_t)(1<<1))
 #define ENET_RACC_PADREM			((uint32_t)(1<<0))
 
-#define IMXRT_ENET2_ADDRESS	0x402D4000
 #define IMXRT_ENET2		(*(IMXRT_REGISTER32_t *)IMXRT_ENET2_ADDRESS)
 #define IMXRT_ENET2_TIMER	(*(IMXRT_REGISTER32_t *)(IMXRT_ENET2_ADDRESS+0x400))
 #define ENET2_EIR			(IMXRT_ENET2.offset004)
@@ -3118,7 +3201,6 @@ typedef struct {
 #define ENET2_TCCR3			(IMXRT_ENET2_TIMER.offset224)
 
 // 59.6.1.1: page 3221
-#define IMXRT_EWM_ADDRESS	0x400B4000
 #define IMXRT_EWM		(*(IMXRT_REGISTER8_t *)IMXRT_EWM_ADDRESS)
 #define EWM_CTRL			(IMXRT_EWM.offset00)
 #define EWM_SERV			(IMXRT_EWM.offset01)
@@ -3128,7 +3210,6 @@ typedef struct {
 #define EWM_CLKPRESCALER		(IMXRT_EWM.offset05)
 
 // 44.9: page 2555
-#define IMXRT_FLEXCAN1_ADDRESS	0x401D0000
 #define IMXRT_FLEXCAN1		(*(IMXRT_REGISTER32_t *)IMXRT_FLEXCAN1_ADDRESS)
 #define IMXRT_FLEXCAN1_MASK	(*(IMXRT_REGISTER32_t *)(IMXRT_FLEXCAN1_ADDRESS+0x800))
 #define FLEXCAN1_MCR			(IMXRT_FLEXCAN1.offset000)
@@ -3213,7 +3294,6 @@ typedef struct {
 #define FLEXCAN1_RXIMR62		(IMXRT_FLEXCAN1_MASK.offset178)
 #define FLEXCAN1_RXIMR63		(IMXRT_FLEXCAN1_MASK.offset17C)
 #define FLEXCAN1_GFWR			(IMXRT_FLEXCAN1_MASK.offset1E0)
-#define IMXRT_FLEXCAN2_ADDRESS	0x401D4000
 #define IMXRT_FLEXCAN2		(*(IMXRT_REGISTER32_t *)IMXRT_FLEXCAN2_ADDRESS)
 #define IMXRT_FLEXCAN2_MASK	(*(IMXRT_REGISTER32_t *)(IMXRT_FLEXCAN2_ADDRESS+0x800))
 #define FLEXCAN2_MCR			(IMXRT_FLEXCAN2.offset000)
@@ -3299,7 +3379,6 @@ typedef struct {
 #define FLEXCAN2_RXIMR63		(IMXRT_FLEXCAN2_MASK.offset17C)
 #define FLEXCAN2_GFWR			(IMXRT_FLEXCAN2_MASK.offset1E0)
 
-#define IMXRT_FLEXCAN3_ADDRESS	0x401D8000
 #define IMXRT_FLEXCAN3		(*(IMXRT_REGISTER32_t *)IMXRT_FLEXCAN3_ADDRESS0)
 #define IMXRT_FLEXCAN3_MASK	(*(IMXRT_REGISTER32_t *)(IMXRT_FLEXCAN3_ADDRESS+0x800))
 #define IMXRT_FLEXCAN3_EXT	(*(IMXRT_REGISTER32_t *)(IMXRT_FLEXCAN3_ADDRESS+0xB00))
@@ -3632,9 +3711,6 @@ typedef struct {
         volatile uint32_t SHIFTBUFNIS[4];       // 0x780
 } IMXRT_FLEXIO_t;
 
-#define IMXRT_FLEXIO1_ADDRESS		(*(IMXRT_REGISTER32_t *)0x401AC000)
-#define IMXRT_FLEXIO2_ADDRESS		(*(IMXRT_REGISTER32_t *)0x401B0000)
-#define IMXRT_FLEXIO3_ADDRESS		(*(IMXRT_REGISTER32_t *)0x42020000)
 
 #define IMXRT_FLEXIO1_S         (*(IMXRT_FLEXIO_t *)IMXRT_FLEXIO1_ADDRESS)
 #define IMXRT_FLEXIO2_S         (*(IMXRT_FLEXIO_t *)IMXRT_FLEXIO2_ADDRESS)
@@ -3921,10 +3997,6 @@ typedef struct {
 	volatile uint16_t FTST0;
 	volatile uint16_t FCTRL20;
 } IMXRT_FLEXPWM_t;
-#define IMXRT_FLEXPWM1_ADDRESS	0x403DC000
-#define IMXRT_FLEXPWM2_ADDRESS	0x403E0000
-#define IMXRT_FLEXPWM3_ADDRESS	0x403E4000
-#define IMXRT_FLEXPWM4_ADDRESS	0x403E8000
 #define IMXRT_FLEXPWM1		(*(IMXRT_FLEXPWM_t *)IMXRT_FLEXPWM1_ADDRESS)
 #define IMXRT_FLEXPWM2		(*(IMXRT_FLEXPWM_t *)IMXRT_FLEXPWM2_ADDRESS)
 #define IMXRT_FLEXPWM3		(*(IMXRT_FLEXPWM_t *)IMXRT_FLEXPWM3_ADDRESS)
@@ -4812,7 +4884,6 @@ typedef struct {
 #define FLEXPWM_FCTRL20_NOCOMB(n)		((uint16_t)(((n) & 0x0F) << 0))
 
 // 31.4.1.1: page 1766
-#define IMXRT_FLEXRAM_ADDRESS	0x400B0000
 #define IMXRT_FLEXRAM		(*(IMXRT_REGISTER32_t *)IMXRT_FLEXRAM_ADDRESS)
 #define FLEXRAM_TCM_CTRL		(IMXRT_FLEXRAM.offset000)
 #define FLEXRAM_INT_STATUS		(IMXRT_FLEXRAM.offset010)
@@ -4832,7 +4903,6 @@ typedef struct {
 #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN	((uint32_t)(1<<3))
 
 // 27.7.2.1: page 1695
-#define IMXRT_FLEXSPI_ADDRESS	0x402A8000
 #define IMXRT_FLEXSPI		(*(IMXRT_REGISTER32_t *)IMXRT_FLEXSPI_ADDRESS)
 #define FLEXSPI_MCR0			(IMXRT_FLEXSPI.offset000)
 #define FLEXSPI_MCR0_AHBGRANTWAIT(n)		((uint32_t)(((n) & 0xFF) << 24))
@@ -5161,7 +5231,6 @@ typedef struct {
 #define FLEXSPI_LUT_NUM_PADS_4			0x02
 #define FLEXSPI_LUT_NUM_PADS_8			0x03
 
-#define IMXRT_FLEXSPI2_ADDRESS	0x402A4000
 #define IMXRT_FLEXSPI2		(*(IMXRT_REGISTER32_t *)IMXRT_FLEXSPI2_ADDRESS)
 #define FLEXSPI2_MCR0			(IMXRT_FLEXSPI2.offset000)
 #define FLEXSPI2_MCR1			(IMXRT_FLEXSPI2.offset004)
@@ -5331,7 +5400,6 @@ typedef struct {
 #define FLEXSPI2_LUT63			(IMXRT_FLEXSPI2.offset2FC)
 
 // 17.6: page 1190
-#define IMXRT_GPC_ADDRESS	0x400F4000
 #define IMXRT_GPC		(*(IMXRT_REGISTER32_t *)IMXRT_GPC_ADDRESS)
 #define GPC_CNTR			(IMXRT_GPC.offset000)
 #define GPC_IMR1			(IMXRT_GPC.offset008)
@@ -5386,7 +5454,6 @@ typedef struct {
 
 } IMXRT_GPIO_t;
 
-#define IMXRT_GPIO1_ADDRESS	0x401B8000
 #define IMXRT_GPIO1		(*(IMXRT_GPIO_t *)IMXRT_GPIO1_ADDRESS)
 #define GPIO1_DR			(IMXRT_GPIO1.DR)
 #define GPIO1_GDIR			(IMXRT_GPIO1.GDIR)
@@ -5399,7 +5466,6 @@ typedef struct {
 #define GPIO1_DR_SET			(IMXRT_GPIO1.DR_SET)
 #define GPIO1_DR_CLEAR			(IMXRT_GPIO1.DR_CLEAR)
 #define GPIO1_DR_TOGGLE			(IMXRT_GPIO1.DR_TOGGLE)
-#define IMXRT_GPIO2_ADDRESS	0x401BC000
 #define IMXRT_GPIO2		(*(IMXRT_GPIO_t *)IMXRT_GPIO2_ADDRESS)
 #define GPIO2_DR			(IMXRT_GPIO2.DR)
 #define GPIO2_GDIR			(IMXRT_GPIO2.GDIR)
@@ -5412,7 +5478,6 @@ typedef struct {
 #define GPIO2_DR_SET			(IMXRT_GPIO2.DR_SET)
 #define GPIO2_DR_CLEAR			(IMXRT_GPIO2.DR_CLEAR)
 #define GPIO2_DR_TOGGLE			(IMXRT_GPIO2.DR_TOGGLE)
-#define IMXRT_GPIO3_ADDRESS	0x401C0000
 #define IMXRT_GPIO3		(*(IMXRT_GPIO_t *)IMXRT_GPIO3_ADDRESS)
 #define GPIO3_DR			(IMXRT_GPIO3.DR)
 #define GPIO3_GDIR			(IMXRT_GPIO3.GDIR)
@@ -5425,7 +5490,6 @@ typedef struct {
 #define GPIO3_DR_SET			(IMXRT_GPIO3.DR_SET)
 #define GPIO3_DR_CLEAR			(IMXRT_GPIO3.DR_CLEAR)
 #define GPIO3_DR_TOGGLE			(IMXRT_GPIO3.DR_TOGGLE)
-#define IMXRT_GPIO4_ADDRESS	0x401C4000
 #define IMXRT_GPIO4		(*(IMXRT_GPIO_t *)IMXRT_GPIO4_ADDRESS)
 #define GPIO4_DR			(IMXRT_GPIO4.DR)
 #define GPIO4_GDIR			(IMXRT_GPIO4.GDIR)
@@ -5438,7 +5502,6 @@ typedef struct {
 #define GPIO4_DR_SET			(IMXRT_GPIO4.DR_SET)
 #define GPIO4_DR_CLEAR			(IMXRT_GPIO4.DR_CLEAR)
 #define GPIO4_DR_TOGGLE			(IMXRT_GPIO4.DR_TOGGLE)
-#define IMXRT_GPIO5_ADDRESS	0x400C0000
 #define IMXRT_GPIO5		(*(IMXRT_GPIO_t *)IMXRT_GPIO5_ADDRESS)
 #define GPIO5_DR			(IMXRT_GPIO5.DR)
 #define GPIO5_GDIR			(IMXRT_GPIO5.GDIR)
@@ -5451,7 +5514,6 @@ typedef struct {
 #define GPIO5_DR_SET			(IMXRT_GPIO5.DR_SET)
 #define GPIO5_DR_CLEAR			(IMXRT_GPIO5.DR_CLEAR)
 #define GPIO5_DR_TOGGLE			(IMXRT_GPIO5.DR_TOGGLE)
-#define IMXRT_GPIO6_ADDRESS	0x42000000
 #define IMXRT_GPIO6		(*(IMXRT_GPIO_t *)IMXRT_GPIO6_ADDRESS)
 #define GPIO6_DR			(IMXRT_GPIO6.DR)
 #define GPIO6_GDIR			(IMXRT_GPIO6.GDIR)
@@ -5464,7 +5526,6 @@ typedef struct {
 #define GPIO6_DR_SET			(IMXRT_GPIO6.DR_SET)
 #define GPIO6_DR_CLEAR			(IMXRT_GPIO6.DR_CLEAR)
 #define GPIO6_DR_TOGGLE			(IMXRT_GPIO6.DR_TOGGLE)
-#define IMXRT_GPIO7_ADDRESS	0x42004000
 #define IMXRT_GPIO7		(*(IMXRT_GPIO_t *)IMXRT_GPIO7_ADDRESS)
 #define GPIO7_DR			(IMXRT_GPIO7.DR)
 #define GPIO7_GDIR			(IMXRT_GPIO7.GDIR)
@@ -5477,7 +5538,6 @@ typedef struct {
 #define GPIO7_DR_SET			(IMXRT_GPIO7.DR_SET)
 #define GPIO7_DR_CLEAR			(IMXRT_GPIO7.DR_CLEAR)
 #define GPIO7_DR_TOGGLE			(IMXRT_GPIO7.DR_TOGGLE)
-#define IMXRT_GPIO8_ADDRESS	0x42008000
 #define IMXRT_GPIO8		(*(IMXRT_GPIO_t *)IMXRT_GPIO8_ADDRESS)
 #define GPIO8_DR			(IMXRT_GPIO8.DR)
 #define GPIO8_GDIR			(IMXRT_GPIO8.GDIR)
@@ -5490,7 +5550,6 @@ typedef struct {
 #define GPIO8_DR_SET			(IMXRT_GPIO8.DR_SET)
 #define GPIO8_DR_CLEAR			(IMXRT_GPIO8.DR_CLEAR)
 #define GPIO8_DR_TOGGLE			(IMXRT_GPIO8.DR_TOGGLE)
-#define IMXRT_GPIO9_ADDRESS	0x4200C000
 #define IMXRT_GPIO9		(*(IMXRT_GPIO_t *)IMXRT_GPIO9_ADDRESS)
 #define GPIO9_DR			(IMXRT_GPIO9.DR)
 #define GPIO9_GDIR			(IMXRT_GPIO9.GDIR)
@@ -5505,7 +5564,6 @@ typedef struct {
 #define GPIO9_DR_TOGGLE			(IMXRT_GPIO9.DR_TOGGLE)
 
 // 52.7: page 2957
-#define IMXRT_GPT1_ADDRESS	0x401EC000
 #define IMXRT_GPT1		(*(IMXRT_REGISTER32_t *)IMXRT_GPT1_ADDRESS)
 #define GPT1_CR				(IMXRT_GPT1.offset000)
 #define GPT1_PR				(IMXRT_GPT1.offset004)
@@ -5517,7 +5575,6 @@ typedef struct {
 #define GPT1_ICR1			(IMXRT_GPT1.offset01C)
 #define GPT1_ICR2			(IMXRT_GPT1.offset020)
 #define GPT1_CNT			(IMXRT_GPT1.offset024)
-#define IMXRT_GPT2_ADDRESS	0x401F0000
 #define IMXRT_GPT2		(*(IMXRT_REGISTER32_t *)IMXRT_GPT2_ADDRESS)
 #define GPT2_CR				(IMXRT_GPT2.offset000)
 #define GPT2_PR				(IMXRT_GPT2.offset004)
@@ -5563,7 +5620,6 @@ typedef struct {
 #define GPT_IR_OF1IE				((uint32_t)(1<<0))
 
 // 11.4: page 327
-#define IMXRT_IOMUXC_GPR_ADDRESS 0x400AC000
 #define IMXRT_IOMUXC_GPR	(*(IMXRT_REGISTER32_t *)IMXRT_IOMUXC_GPR_ADDRESS)
 #define IOMUXC_GPR_GPR0			(IMXRT_IOMUXC_GPR.offset000)
 #define IOMUXC_GPR_GPR1			(IMXRT_IOMUXC_GPR.offset004)
@@ -5859,7 +5915,6 @@ typedef struct {
 #define IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL(n) ((uint32_t)(((n) & 0xFF) << 0))
 
 // 11.5: page 380
-#define IMXRT_IOMUXC_SNVS_ADDRESS 0x400A8000
 #define IMXRT_IOMUXC_SNVS	(*(IMXRT_REGISTER32_t *)IMXRT_IOMUXC_SNVS_ADDRESS)
 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP		(IMXRT_IOMUXC_SNVS.offset000)
 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ		(IMXRT_IOMUXC_SNVS.offset004)
@@ -5872,7 +5927,6 @@ typedef struct {
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ	(IMXRT_IOMUXC_SNVS.offset020)
 
 // 11.6: page 399
-#define IMXRT_IOMUXC_SNVS_GPR_ADDRESS 0x400A4000
 #define IMXRT_IOMUXC_SNVS_GPR	(*(IMXRT_REGISTER32_t *)IMXRT_IOMUXC_SNVS_GPR_ADDRESS)
 #define IOMUXC_SNVS_GPR_GPR0		(IMXRT_IOMUXC_SNVS_GPR.offset000)
 #define IOMUXC_SNVS_GPR_GPR1		(IMXRT_IOMUXC_SNVS_GPR.offset004)
@@ -5880,9 +5934,8 @@ typedef struct {
 #define IOMUXC_SNVS_GPR_GPR3		(IMXRT_IOMUXC_SNVS_GPR.offset00C)
 
 // 11.7: page 403
-#define IMXRT_IOMUXC_ADDRESS	0x401F8000
-#define IMXRT_IOMUXC		(*(IMXRT_REGISTER32_t *)0x401F8000)
-#define IMXRT_IOMUXC_b		(*(IMXRT_REGISTER32_t *)(0x401F8000+0x400))
+#define IMXRT_IOMUXC		(*(IMXRT_REGISTER32_t *)IMXRT_IOMUXC_ADDRESS)
+#define IMXRT_IOMUXC_b		(*(IMXRT_REGISTER32_t *)(IMXRT_IOMUXC_ADDRESS+0x400))
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00	(IMXRT_IOMUXC.offset014)
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01	(IMXRT_IOMUXC.offset018)
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02	(IMXRT_IOMUXC.offset01C)
@@ -6372,7 +6425,6 @@ typedef struct {
 #define IOMUXC_PAD_HYS					((uint32_t)(1<<16))
 
 // 46.7: page 2732
-#define IMXRT_KPP_ADDRESS	0x401FC000
 #define IMXRT_KPP		(*(IMXRT_REGISTER16_t *)IMXRT_KPP_ADDRESS)
 #define KPP_KPCR			(IMXRT_KPP.offset000)
 #define KPP_KPSR			(IMXRT_KPP.offset002)
@@ -6380,7 +6432,6 @@ typedef struct {
 #define KPP_KPDR			(IMXRT_KPP.offset006)
 
 // 35.7: page 1860
-#define IMXRT_LCDIF_ADDRESS	0x402B8000
 #define IMXRT_LCDIF		(*(IMXRT_REGISTER32_t *)IMXRT_LCDIF_ADDRESS)
 #define LCDIF_CTRL			(IMXRT_LCDIF.offset000)
 #define LCDIF_CTRL_SET			(IMXRT_LCDIF.offset004)
@@ -6509,7 +6560,6 @@ typedef struct {
 	volatile uint32_t unused14[3];
 	volatile uint32_t SRDR;			// 170
 } IMXRT_LPI2C_t;
-#define IMXRT_LPI2C1_ADDRESS	0x403F0000
 #define IMXRT_LPI2C1		(*(IMXRT_LPI2C_t *)IMXRT_LPI2C1_ADDRESS)
 #define LPI2C1_VERID			(IMXRT_LPI2C1.VERID)
 #define LPI2C1_PARAM			(IMXRT_LPI2C1.PARAM)
@@ -6539,7 +6589,6 @@ typedef struct {
 #define LPI2C1_STAR			(IMXRT_LPI2C1.STAR)
 #define LPI2C1_STDR			(IMXRT_LPI2C1.STDR)
 #define LPI2C1_SRDR			(IMXRT_LPI2C1.SRDR)
-#define IMXRT_LPI2C2_ADDRESS	0x403F4000
 #define IMXRT_LPI2C2		(*(IMXRT_LPI2C_t *)IMXRT_LPI2C2_ADDRESS)
 #define LPI2C2_VERID			(IMXRT_LPI2C2.VERID)
 #define LPI2C2_PARAM			(IMXRT_LPI2C2.PARAM)
@@ -6569,7 +6618,6 @@ typedef struct {
 #define LPI2C2_STAR			(IMXRT_LPI2C2.STAR)
 #define LPI2C2_STDR			(IMXRT_LPI2C2.STDR)
 #define LPI2C2_SRDR			(IMXRT_LPI2C2.SRDR)
-#define IMXRT_LPI2C3_ADDRESS	0x403F8000
 #define IMXRT_LPI2C3		(*(IMXRT_LPI2C_t *)IMXRT_LPI2C3_ADDRESS)
 #define LPI2C3_VERID			(IMXRT_LPI2C3.VERID)
 #define LPI2C3_PARAM			(IMXRT_LPI2C3.PARAM)
@@ -6599,7 +6647,6 @@ typedef struct {
 #define LPI2C3_STAR			(IMXRT_LPI2C3.STAR)
 #define LPI2C3_STDR			(IMXRT_LPI2C3.STDR)
 #define LPI2C3_SRDR			(IMXRT_LPI2C3.SRDR)
-#define IMXRT_LPI2C4_ADDRESS	0x403FC000
 #define IMXRT_LPI2C4		(*(IMXRT_LPI2C_t *)IMXRT_LPI2C4_ADDRESS)
 #define LPI2C4_VERID			(IMXRT_LPI2C4.VERID)
 #define LPI2C4_PARAM			(IMXRT_LPI2C4.PARAM)
@@ -6792,7 +6839,6 @@ typedef struct {
         volatile uint32_t RDR;          // 0x74
 } IMXRT_LPSPI_t;
 
-#define IMXRT_LPSPI1_ADDRESS	0x40394000
 #define IMXRT_LPSPI1		(*(IMXRT_REGISTER32_t *)IMXRT_LPSPI1_ADDRESS)
 #define IMXRT_LPSPI1_S          (*(IMXRT_LPSPI_t *)IMXRT_LPSPI1_ADDRESS)
 #define LPSPI1_VERID			(IMXRT_LPSPI1.offset000)
@@ -6812,7 +6858,6 @@ typedef struct {
 #define LPSPI1_TDR			(IMXRT_LPSPI1.offset064)
 #define LPSPI1_RSR			(IMXRT_LPSPI1.offset070)
 #define LPSPI1_RDR			(IMXRT_LPSPI1.offset074)
-#define IMXRT_LPSPI2_ADDRESS	0x40398000
 #define IMXRT_LPSPI2		(*(IMXRT_REGISTER32_t *)IMXRT_LPSPI2_ADDRESS)
 #define IMXRT_LPSPI2_S          (*(IMXRT_LPSPI_t *)IMXRT_LPSPI2_ADDRESS)
 #define LPSPI2_VERID			(IMXRT_LPSPI2.offset000)
@@ -6832,7 +6877,6 @@ typedef struct {
 #define LPSPI2_TDR			(IMXRT_LPSPI2.offset064)
 #define LPSPI2_RSR			(IMXRT_LPSPI2.offset070)
 #define LPSPI2_RDR			(IMXRT_LPSPI2.offset074)
-#define IMXRT_LPSPI3_ADDRESS	0x4039C000
 #define IMXRT_LPSPI3		(*(IMXRT_REGISTER32_t *)IMXRT_LPSPI3_ADDRESS)
 #define IMXRT_LPSPI3_S          (*(IMXRT_LPSPI_t *)IMXRT_LPSPI3_ADDRESS)
 #define LPSPI3_VERID			(IMXRT_LPSPI3.offset000)
@@ -6852,7 +6896,6 @@ typedef struct {
 #define LPSPI3_TDR			(IMXRT_LPSPI3.offset064)
 #define LPSPI3_RSR			(IMXRT_LPSPI3.offset070)
 #define LPSPI3_RDR			(IMXRT_LPSPI3.offset074)
-#define IMXRT_LPSPI4_ADDRESS	0x403A0000
 #define IMXRT_LPSPI4		(*(IMXRT_REGISTER32_t *)IMXRT_LPSPI4_ADDRESS)
 #define IMXRT_LPSPI4_S          (*(IMXRT_LPSPI_t *)IMXRT_LPSPI4_ADDRESS)
 #define LPSPI4_VERID			(IMXRT_LPSPI4.offset000)
@@ -6949,7 +6992,6 @@ typedef struct {
 	volatile uint32_t FIFO;
 	volatile uint32_t WATER;
 } IMXRT_LPUART_t;
-#define IMXRT_LPUART1_ADDRESS	0x40184000
 #define IMXRT_LPUART1		(*(IMXRT_LPUART_t *)IMXRT_LPUART1_ADDRESS)
 #define LPUART1_VERID			(IMXRT_LPUART1.VERID)
 #define LPUART1_PARAM			(IMXRT_LPUART1.PARAM)
@@ -6963,7 +7005,6 @@ typedef struct {
 #define LPUART1_MODIR			(IMXRT_LPUART1.MODIR)
 #define LPUART1_FIFO			(IMXRT_LPUART1.FIFO)
 #define LPUART1_WATER			(IMXRT_LPUART1.WATER)
-#define IMXRT_LPUART2_ADDRESS	0x40188000
 #define IMXRT_LPUART2		(*(IMXRT_LPUART_t *)IMXRT_LPUART2_ADDRESS)
 #define LPUART2_VERID			(IMXRT_LPUART2.VERID)
 #define LPUART2_PARAM			(IMXRT_LPUART2.PARAM)
@@ -6977,7 +7018,6 @@ typedef struct {
 #define LPUART2_MODIR			(IMXRT_LPUART2.MODIR)
 #define LPUART2_FIFO			(IMXRT_LPUART2.FIFO)
 #define LPUART2_WATER			(IMXRT_LPUART2.WATER)
-#define IMXRT_LPUART3_ADDRESS	0x4018C000
 #define IMXRT_LPUART3		(*(IMXRT_LPUART_t *)IMXRT_LPUART3_ADDRESS)
 #define LPUART3_VERID			(IMXRT_LPUART3.VERID)
 #define LPUART3_PARAM			(IMXRT_LPUART3.PARAM)
@@ -6991,7 +7031,6 @@ typedef struct {
 #define LPUART3_MODIR			(IMXRT_LPUART3.MODIR)
 #define LPUART3_FIFO			(IMXRT_LPUART3.FIFO)
 #define LPUART3_WATER			(IMXRT_LPUART3.WATER)
-#define IMXRT_LPUART4_ADDRESS	0x40190000
 #define IMXRT_LPUART4		(*(IMXRT_LPUART_t *)IMXRT_LPUART4_ADDRESS)
 #define LPUART4_VERID			(IMXRT_LPUART4.VERID)
 #define LPUART4_PARAM			(IMXRT_LPUART4.PARAM)
@@ -7005,7 +7044,6 @@ typedef struct {
 #define LPUART4_MODIR			(IMXRT_LPUART4.MODIR)
 #define LPUART4_FIFO			(IMXRT_LPUART4.FIFO)
 #define LPUART4_WATER			(IMXRT_LPUART4.WATER)
-#define IMXRT_LPUART5_ADDRESS	0x40194000
 #define IMXRT_LPUART5		(*(IMXRT_LPUART_t *)IMXRT_LPUART5_ADDRESS)
 #define LPUART5_VERID			(IMXRT_LPUART5.VERID)
 #define LPUART5_PARAM			(IMXRT_LPUART5.PARAM)
@@ -7019,7 +7057,6 @@ typedef struct {
 #define LPUART5_MODIR			(IMXRT_LPUART5.MODIR)
 #define LPUART5_FIFO			(IMXRT_LPUART5.FIFO)
 #define LPUART5_WATER			(IMXRT_LPUART5.WATER)
-#define IMXRT_LPUART6_ADDRESS	0x40198000
 #define IMXRT_LPUART6		(*(IMXRT_LPUART_t *)IMXRT_LPUART6_ADDRESS)
 #define LPUART6_VERID			(IMXRT_LPUART6.VERID)
 #define LPUART6_PARAM			(IMXRT_LPUART6.PARAM)
@@ -7033,7 +7070,6 @@ typedef struct {
 #define LPUART6_MODIR			(IMXRT_LPUART6.MODIR)
 #define LPUART6_FIFO			(IMXRT_LPUART6.FIFO)
 #define LPUART6_WATER			(IMXRT_LPUART6.WATER)
-#define IMXRT_LPUART7_ADDRESS	0x4019C000
 #define IMXRT_LPUART7		(*(IMXRT_LPUART_t *)IMXRT_LPUART7_ADDRESS)
 #define LPUART7_VERID			(IMXRT_LPUART7.VERID)
 #define LPUART7_PARAM			(IMXRT_LPUART7.PARAM)
@@ -7047,7 +7083,6 @@ typedef struct {
 #define LPUART7_MODIR			(IMXRT_LPUART7.MODIR)
 #define LPUART7_FIFO			(IMXRT_LPUART7.FIFO)
 #define LPUART7_WATER			(IMXRT_LPUART7.WATER)
-#define IMXRT_LPUART8_ADDRESS	0x401A0000
 #define IMXRT_LPUART8		(*(IMXRT_LPUART_t *)IMXRT_LPUART8_ADDRESS)
 #define LPUART8_VERID			(IMXRT_LPUART8.VERID)
 #define LPUART8_PARAM			(IMXRT_LPUART8.PARAM)
@@ -7163,7 +7198,6 @@ typedef struct {
 
 
 // 23.6.1.1: page 1331
-#define IMXRT_OCOTP_ADDRESS	0x401F4000
 #define IMXRT_OCOTP		(*(IMXRT_REGISTER32_t *)IMXRT_OCOTP_ADDRESS)
 #define HW_OCOTP_CTRL			(IMXRT_OCOTP.offset000)
 #define HW_OCOTP_CTRL_SET		(IMXRT_OCOTP.offset004)
@@ -7271,7 +7305,6 @@ typedef struct {
 #endif
 
 // 53.9.1: page 2978
-#define IMXRT_PIT_ADDRESS	0x40084000
 #define IMXRT_PIT		(*(IMXRT_REGISTER32_t *)IMXRT_PIT_ADDRESS)
 #define PIT_MCR				(IMXRT_PIT.offset000)
 #define PIT_LTMR64H			(IMXRT_PIT.offset0E0)
@@ -7307,7 +7340,6 @@ typedef struct {
 #define PIT_TFLG_TIF				((uint32_t)(1<<0))
 
 // 16.6: page 1160
-#define IMXRT_PMU_ADDRESS	0x400D8000
 #define IMXRT_PMU		(*(IMXRT_REGISTER32_t *)IMXRT_PMU_ADDRESS)
 #define PMU_REG_1P1			(IMXRT_PMU.offset110)
 #define PMU_REG_1P1_SET			(IMXRT_PMU.offset114)
@@ -7492,7 +7524,6 @@ typedef struct
     volatile uint32_t unused27[15];
     volatile uint32_t PORTER_DUFF_CTRL;
 } IMXRT_PXP_t;
-#define IMXRT_PXP_ADDRESS 0x402B4000
 #define IMXRT_PXP        (*(IMXRT_PXP_t *)IMXRT_PXP_ADDRESS)
 #define PXP_CTRL            (IMXRT_PXP.CTRL)
 #define PXP_CTRL_SET            (IMXRT_PXP.CTRL_SET)
@@ -7685,7 +7716,6 @@ typedef struct
       };
    };
 } IMXRT_TMR_t;
-#define IMXRT_TMR1_ADDRESS	0x401DC000
 #define IMXRT_TMR1		(*(IMXRT_TMR_t *)IMXRT_TMR1_ADDRESS)
 #define TMR1_COMP10			(IMXRT_TMR1.CH[0].COMP1)
 #define TMR1_COMP20			(IMXRT_TMR1.CH[0].COMP2)
@@ -7740,7 +7770,6 @@ typedef struct
 #define TMR1_CSCTRL3			(IMXRT_TMR1.CH[3].CSCTRL)
 #define TMR1_FILT3			(IMXRT_TMR1.CH[3].FILT)
 #define TMR1_DMA3			(IMXRT_TMR1.CH[3].DMA)
-#define IMXRT_TMR2_ADDRESS	0x401E0000
 #define IMXRT_TMR2		(*(IMXRT_TMR_t *)IMXRT_TMR2_ADDRESS)
 #define TMR2_COMP10			(IMXRT_TMR2.CH[0].COMP1)
 #define TMR2_COMP20			(IMXRT_TMR2.CH[0].COMP2)
@@ -7795,7 +7824,6 @@ typedef struct
 #define TMR2_CSCTRL3			(IMXRT_TMR2.CH[3].CSCTRL)
 #define TMR2_FILT3			(IMXRT_TMR2.CH[3].FILT)
 #define TMR2_DMA3			(IMXRT_TMR2.CH[3].DMA)
-#define IMXRT_TMR3_ADDRESS	0x401E4000
 #define IMXRT_TMR3		(*(IMXRT_TMR_t *)IMXRT_TMR3_ADDRESS)
 #define TMR3_COMP10			(IMXRT_TMR3.CH[0].COMP1)
 #define TMR3_COMP20			(IMXRT_TMR3.CH[0].COMP2)
@@ -7850,7 +7878,6 @@ typedef struct
 #define TMR3_CSCTRL3			(IMXRT_TMR3.CH[3].CSCTRL)
 #define TMR3_FILT3			(IMXRT_TMR3.CH[3].FILT)
 #define TMR3_DMA3			(IMXRT_TMR3.CH[3].DMA)
-#define IMXRT_TMR4_ADDRESS	0x401E8000
 #define IMXRT_TMR4		(*(IMXRT_TMR_t *)IMXRT_TMR4_ADDRESS)
 #define TMR4_COMP10			(IMXRT_TMR4.CH[0].COMP1)
 #define TMR4_COMP20			(IMXRT_TMR4.CH[0].COMP2)
@@ -7947,7 +7974,6 @@ typedef struct
 #define TMR_DMA_IEFDE				((uint16_t)(1<<0))
 
 // 38.5.1.1: page 1981
-#define IMXRT_I2S1_ADDRESS	0x40384000
 #define IMXRT_I2S1		(*(IMXRT_REGISTER32_t *)IMXRT_I2S1_ADDRESS)
 #define I2S1_VERID			(IMXRT_I2S1.offset000)
 #define I2S1_PARAM			(IMXRT_I2S1.offset004)
@@ -7981,7 +8007,6 @@ typedef struct
 #define I2S1_RFR2			(IMXRT_I2S1.offset0C8)
 #define I2S1_RFR3			(IMXRT_I2S1.offset0CC)
 #define I2S1_RMR			(IMXRT_I2S1.offset0E0)
-#define IMXRT_I2S2_ADDRESS	0x40388000
 #define IMXRT_I2S2		(*(IMXRT_REGISTER32_t *)IMXRT_I2S2_ADDRESS)
 #define I2S2_VERID			(IMXRT_I2S2.offset000)
 #define I2S2_PARAM			(IMXRT_I2S2.offset004)
@@ -8015,7 +8040,6 @@ typedef struct
 #define I2S2_RFR2			(IMXRT_I2S2.offset0C8)
 #define I2S2_RFR3			(IMXRT_I2S2.offset0CC)
 #define I2S2_RMR			(IMXRT_I2S2.offset0E0)
-#define IMXRT_I2S3_ADDRESS	0x4038C000
 #define IMXRT_I2S3		(*(IMXRT_REGISTER32_t *)IMXRT_I2S3_ADDRESS)
 #define I2S3_VERID			(IMXRT_I2S3.offset000)
 #define I2S3_PARAM			(IMXRT_I2S3.offset004)
@@ -8104,7 +8128,6 @@ typedef struct
 
 
 // 25.4.1.1: page 1385
-#define IMXRT_SEMC_ADDRESS	0x402F0000
 #define IMXRT_SEMC		(*(IMXRT_REGISTER32_t *)IMXRT_SEMC_ADDRESS)
 #define SEMC_MCR			(IMXRT_SEMC.offset000)
 #define SEMC_IOCR			(IMXRT_SEMC.offset004)
@@ -8163,7 +8186,6 @@ typedef struct
 #define SEMC_STS15			(IMXRT_SEMC.offset0FC)
 
 // 20.6.1: page 1242
-#define IMXRT_SNVS_ADDRESS	0x400D4000
 #define IMXRT_SNVS		(*(IMXRT_REGISTER32_t *)IMXRT_SNVS_ADDRESS)
 #define SNVS_HPLR			(IMXRT_SNVS.offset000)
 #define SNVS_HPCOMR			(IMXRT_SNVS.offset004)
@@ -8195,7 +8217,7 @@ typedef struct
 #define SNVS_LPGPR1                     (IMXRT_SNVS.offset104)
 #define SNVS_LPGPR2                     (IMXRT_SNVS.offset108)
 #define SNVS_LPGPR3                     (IMXRT_SNVS.offset10C)
-#define IMXRT_SNVS_b		(*(IMXRT_REGISTER32_t *)0x400D4800)
+#define IMXRT_SNVS_b		(*(IMXRT_REGISTER32_t *)(IMXRT_SNVS_ADDRESS+0x800))
 #define SNVS_HPVIDR1			(IMXRT_SNVS_b.offset3F8)
 #define SNVS_HPVIDR2			(IMXRT_SNVS_b.offset3FC)
 #define SNVS_HPCR_BTN_MASK		((uint32_t)(1 << 27))
@@ -8223,7 +8245,6 @@ typedef struct
 #define SNVS_LPCR_GPR_Z_DIS             ((uint32_t)(1 << 24))
 
 // 40.6: page 2035
-#define IMXRT_SPDIF_ADDRESS	0x40380000
 #define IMXRT_SPDIF		(*(IMXRT_REGISTER32_t *)IMXRT_SPDIF_ADDRESS)
 #define SPDIF_SCR			(IMXRT_SPDIF.offset000)
 #define SPDIF_SRCD			(IMXRT_SPDIF.offset004)
@@ -8319,7 +8340,6 @@ typedef struct
 #define SPDIF_STC_TXCLK_DF(n)		((uint32_t)(((n) & 0x7f) << 0))
 
 // 21.8: page 1284
-#define IMXRT_SRC_ADDRESS	0x400F8000
 #define IMXRT_SRC		(*(IMXRT_REGISTER32_t *)IMXRT_SRC_ADDRESS)
 #define SRC_SCR				(IMXRT_SRC.offset000)
 #define SRC_SBMR1			(IMXRT_SRC.offset004)
@@ -8362,7 +8382,6 @@ These register are used by the ROM code and should not be used by application so
 #define SRC_SBMR2_SEC_CONFIG(n)		((uint32_t)(((n) & 0x03) << 0))
 
 // 19.4: page 1224
-#define IMXRT_TEMPMON_ADDRESS	0x400D8180
 #define IMXRT_TEMPMON		(*(IMXRT_REGISTER32_t *)IMXRT_TEMPMON_ADDRESS)
 #define TEMPMON_TEMPSENSE0          (IMXRT_TEMPMON.offset000)
 #define TEMPMON_TEMPSENSE0_SET		(IMXRT_TEMPMON.offset004)
@@ -8385,7 +8404,6 @@ These register are used by the ROM code and should not be used by application so
 #define TEMPMON_CTRL2_PANIC_ALARM_VALUE(n)	((uint32_t)(((n) & 0x0fff) << 16))
 #define TEMPMON_CTRL2_LOW_ALARM_VALUE(n)	((uint32_t)(((n) & 0x0fff) << 0))
 
-#define IMXRT_TRNG_ADDRESS	0x400CC000
 #define IMXRT_TRNG		(*(IMXRT_REGISTER32_t *)IMXRT_TRNG_ADDRESS)
 #define TRNG_MCTL			(IMXRT_TRNG.offset000)
 #define TRNG_SCMISC			(IMXRT_TRNG.offset004)
@@ -8500,7 +8518,6 @@ These register are used by the ROM code and should not be used by application so
 
 
 // 68.4: page 3406
-#define IMXRT_TSC_ADDRESS	0x400E0000
 #define IMXRT_TSC		(*(IMXRT_REGISTER32_t *)IMXRT_TSC_ADDRESS)
 #define TSC_BASIC_SETTING		(IMXRT_TSC.offset000)
 #define TSC_PS_INPUT_BUFFER_ADDR	(IMXRT_TSC.offset010)
@@ -8513,7 +8530,6 @@ These register are used by the ROM code and should not be used by application so
 #define TSC_DEBUG_MODE2			(IMXRT_TSC.offset080)
 
 // 42.5.1.1: page 2212
-#define IMXRT_USB1_ADDRESS	0x402E0000
 #define IMXRT_USB1		(*(IMXRT_REGISTER32_t *)IMXRT_USB1_ADDRESS)
 #define USB1_ID				(IMXRT_USB1.offset000)
 #define USB1_HWGENERAL			(IMXRT_USB1.offset004)
@@ -8560,7 +8576,6 @@ These register are used by the ROM code and should not be used by application so
 #define USB1_ENDPTCTRL5			(IMXRT_USB1.offset1D4)
 #define USB1_ENDPTCTRL6			(IMXRT_USB1.offset1D8)
 #define USB1_ENDPTCTRL7			(IMXRT_USB1.offset1DC)
-#define IMXRT_USB2_ADDRESS	0x402E0200
 #define IMXRT_USB2		(*(IMXRT_REGISTER32_t *)IMXRT_USB2_ADDRESS)
 #define USB2_ID				(IMXRT_USB2.offset000)
 #define USB2_HWGENERAL			(IMXRT_USB2.offset004)
@@ -8701,7 +8716,6 @@ These register are used by the ROM code and should not be used by application so
 #define USB_GPTIMERCTRL_GPTCNT(n)		((uint32_t)(((n) & 0xFFFFFF) << 0))
 
 // 43.3: page 2474
-#define IMXRT_USBPHY1_ADDRESS	0x400D9000
 #define IMXRT_USBPHY1		(*(IMXRT_REGISTER32_t *)IMXRT_USBPHY1_ADDRESS)
 #define USBPHY1_PWD			(IMXRT_USBPHY1.offset000)
 #define USBPHY1_PWD_SET			(IMXRT_USBPHY1.offset004)
@@ -8730,7 +8744,6 @@ These register are used by the ROM code and should not be used by application so
 #define USBPHY1_DEBUG1_CLR		(IMXRT_USBPHY1.offset078)
 #define USBPHY1_DEBUG1_TOG		(IMXRT_USBPHY1.offset07C)
 #define USBPHY1_VERSION			(IMXRT_USBPHY1.offset080)
-#define IMXRT_USBPHY2_ADDRESS	0x400DA000
 #define IMXRT_USBPHY2		(*(IMXRT_REGISTER32_t *)IMXRT_USBPHY2_ADDRESS)
 #define USBPHY2_PWD			(IMXRT_USBPHY2.offset000)
 #define USBPHY2_PWD_SET			(IMXRT_USBPHY2.offset004)
@@ -8805,7 +8818,6 @@ These register are used by the ROM code and should not be used by application so
 #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ		((uint32_t)(1<<0))
 
 // 26.9.1.1: page 1553
-#define IMXRT_USDHC1_ADDRESS	0x402C0000
 #define IMXRT_USDHC1		(*(IMXRT_REGISTER32_t *)IMXRT_USDHC1_ADDRESS)
 #define USDHC1_DS_ADDR			(IMXRT_USDHC1.offset000)
 #define USDHC1_BLK_ATT			(IMXRT_USDHC1.offset004)
@@ -8836,7 +8848,6 @@ These register are used by the ROM code and should not be used by application so
 #define USDHC1_MMC_BOOT			(IMXRT_USDHC1.offset0C4)
 #define USDHC1_VEND_SPEC2		(IMXRT_USDHC1.offset0C8)
 #define USDHC1_TUNING_CTRL		(IMXRT_USDHC1.offset0CC)
-#define IMXRT_USDHC2_ADDRESS	0x402C4000
 #define IMXRT_USDHC2		(*(IMXRT_REGISTER32_t *)IMXRT_USDHC2_ADDRESS)
 #define USDHC2_DS_ADDR			(IMXRT_USDHC2.offset000)
 #define USDHC2_BLK_ATT			(IMXRT_USDHC2.offset004)
@@ -8869,15 +8880,13 @@ These register are used by the ROM code and should not be used by application so
 #define USDHC2_TUNING_CTRL		(IMXRT_USDHC2.offset0CC)
 
 // 57.8.1.1: page 3187
-#define IMXRT_WDOG1_ADDRESS	0x400B8000
 #define IMXRT_WDOG1		(*(IMXRT_REGISTER16_t *)IMXRT_WDOG1_ADDRESS)
 #define WDOG1_WCR			(IMXRT_WDOG1.offset000)
 #define WDOG1_WSR			(IMXRT_WDOG1.offset002)
 #define WDOG1_WRSR			(IMXRT_WDOG1.offset004)
 #define WDOG1_WICR			(IMXRT_WDOG1.offset006)
 #define WDOG1_WMCR			(IMXRT_WDOG1.offset008)
-#define IMXRT_WDOG2_ADDRESS	0x400D0000
-#define IMXRT_WDOG2		(*(IMXRT_REGISTER16_t *)0x400D0000)
+#define IMXRT_WDOG2		(*(IMXRT_REGISTER16_t *)IMXRT_WDOG2_ADDRESS)
 #define WDOG2_WCR			(IMXRT_WDOG2.offset000)
 #define WDOG2_WSR			(IMXRT_WDOG2.offset002)
 #define WDOG2_WRSR			(IMXRT_WDOG2.offset004)
@@ -8897,7 +8906,6 @@ These register are used by the ROM code and should not be used by application so
 #define WDOG_WRSR_POR				((uint16_t)(1<<4))
 
 // 58.5.1.1: page 3205
-#define IMXRT_WDOG3_ADDRESS	0x400BC000
 #define IMXRT_WDOG3		(*(IMXRT_REGISTER32_t *)IMXRT_WDOG3_ADDRESS)
 #define WDOG3_CS			(IMXRT_WDOG3.offset000)
 #define WDOG3_CNT			(IMXRT_WDOG3.offset004)
@@ -8919,7 +8927,6 @@ These register are used by the ROM code and should not be used by application so
 #define WDOG_CS_WIN				((uint16_t)(1<<15))
 
 // 61.4: page 3235
-#define IMXRT_XBARA1_ADDRESS	0x403BC000
 #define IMXRT_XBARA1		(*(IMXRT_REGISTER16_t *)IMXRT_XBARA1_ADDRESS)
 #define XBARA1_SEL0			(IMXRT_XBARA1.offset000)
 #define XBARA1_SEL1			(IMXRT_XBARA1.offset002)
@@ -8999,7 +9006,6 @@ These register are used by the ROM code and should not be used by application so
 #define XBARA_CTRL_DEN0				((uint16_t)(1<<0))
 
 // 62.3: page 3278
-#define IMXRT_XBARB2_ADDRESS	0x403C0000
 #define IMXRT_XBARB2		(*(IMXRT_REGISTER16_t *)IMXRT_XBARB2_ADDRESS)
 #define XBARB2_SEL0			(IMXRT_XBARB2.offset000)
 #define XBARB2_SEL1			(IMXRT_XBARB2.offset002)
@@ -9009,7 +9015,6 @@ These register are used by the ROM code and should not be used by application so
 #define XBARB2_SEL5			(IMXRT_XBARB2.offset00A)
 #define XBARB2_SEL6			(IMXRT_XBARB2.offset00C)
 #define XBARB2_SEL7			(IMXRT_XBARB2.offset00E)
-#define IMXRT_XBARB3_ADDRESS	0x403C4000
 #define IMXRT_XBARB3		(*(IMXRT_REGISTER16_t *)IMXRT_XBARB3_ADDRESS)
 #define XBARB3_SEL0			(IMXRT_XBARB3.offset000)
 #define XBARB3_SEL1			(IMXRT_XBARB3.offset002)
@@ -9446,7 +9451,6 @@ These register are used by the ROM code and should not be used by application so
 
 
 // 15.6: page 1142
-#define IMXRT_XTALOSC24M_ADDRESS 0x400D8000
 #define IMXRT_XTALOSC24M	(*(IMXRT_REGISTER32_t *)IMXRT_XTALOSC24M_ADDRESS)
 #define XTALOSC24M_MISC0		(IMXRT_XTALOSC24M.offset150)
 #define XTALOSC24M_LOWPWR_CTRL		(IMXRT_XTALOSC24M.offset270)