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Add support for pins 26 and 27

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Kurt Eckhardt 8 years ago
parent
commit
491e1e21ca
1 changed files with 15 additions and 3 deletions
  1. +15
    -3
      teensy3/serial1.c

+ 15
- 3
teensy3/serial1.c View File

* permit persons to whom the Software is furnished to do so, subject to * permit persons to whom the Software is furnished to do so, subject to
* the following conditions: * the following conditions:
* *
* 1. The above copyright notice and this permission notice shall be
* 1. The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software. * included in all copies or substantial portions of the Software.
* *
* 2. If the Software is incorporated into a build system that allows
* 2. If the Software is incorporated into a build system that allows
* selection among a list of target devices, then similar target * selection among a list of target devices, then similar target
* devices manufactured by PJRC.COM must be included in the list of * devices manufactured by PJRC.COM must be included in the list of
* target devices and selectable in the same manner. * target devices and selectable in the same manner.
case 4: CORE_PIN4_CONFIG = 0; break; // PTA2 case 4: CORE_PIN4_CONFIG = 0; break; // PTA2
case 24: CORE_PIN24_CONFIG = 0; break; // PTE20 case 24: CORE_PIN24_CONFIG = 0; break; // PTE20
#endif #endif
#if defined(__MK64FX512__) || defined(__MK66FX1M0__)
case 26: CORE_PIN26_CONFIG = 0; break; //PTA14
#endif
} }
if (opendrain) { if (opendrain) {
cfg = PORT_PCR_DSE | PORT_PCR_ODE; cfg = PORT_PCR_DSE | PORT_PCR_ODE;
case 4: CORE_PIN4_CONFIG = cfg | PORT_PCR_MUX(2); break; case 4: CORE_PIN4_CONFIG = cfg | PORT_PCR_MUX(2); break;
case 24: CORE_PIN24_CONFIG = cfg | PORT_PCR_MUX(4); break; case 24: CORE_PIN24_CONFIG = cfg | PORT_PCR_MUX(4); break;
#endif #endif
#if defined(__MK64FX512__) || defined(__MK66FX1M0__)
case 26: CORE_PIN26_CONFIG = cfg | PORT_PCR_MUX(3); break;
#endif
} }
} }
tx_pin_num = pin; tx_pin_num = pin;
case 3: CORE_PIN3_CONFIG = 0; break; // PTA1 case 3: CORE_PIN3_CONFIG = 0; break; // PTA1
case 25: CORE_PIN25_CONFIG = 0; break; // PTE21 case 25: CORE_PIN25_CONFIG = 0; break; // PTE21
#endif #endif
#if defined(__MK64FX512__) || defined(__MK66FX1M0__)
case 27: CORE_PIN27_CONFIG = 0; break; // PTA15
#endif
} }
switch (pin) { switch (pin) {
case 0: CORE_PIN0_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break; case 0: CORE_PIN0_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
case 3: CORE_PIN3_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(2); break; case 3: CORE_PIN3_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(2); break;
case 25: CORE_PIN25_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(4); break; case 25: CORE_PIN25_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(4); break;
#endif #endif
#if defined(__MK64FX512__) || defined(__MK66FX1M0__)
case 27: CORE_PIN27_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
#endif
} }
} }
rx_pin_num = pin; rx_pin_num = pin;
if (rts_pin) rts_assert(); if (rts_pin) rts_assert();
} }


// status interrupt combines
// status interrupt combines
// Transmit data below watermark UART_S1_TDRE // Transmit data below watermark UART_S1_TDRE
// Transmit complete UART_S1_TC // Transmit complete UART_S1_TC
// Idle line UART_S1_IDLE // Idle line UART_S1_IDLE

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