Add defs for ethernet register bits

teensy3/kinetis.h

@@ -3628,22 +3628,22 @@ typedef struct {
 #define ENET_EIR_TS_AVAIL		((uint32_t)0x00010000)		// Transmit Timestamp Available
 #define ENET_EIR_TS_TIMER		((uint32_t)0x00008000)		// Timestamp Timer
 #define ENET_EIMR		(*(volatile uint32_t *)0x400C0008) // Interrupt Mask Register
-#define ENET_EIRM_BABR			((uint32_t)0x40000000)		// Babbling Receive Error Mask
-#define ENET_EIRM_BABT			((uint32_t)0x20000000)		// Babbling Transmit Error Mask
-#define ENET_EIRM_GRA			((uint32_t)0x10000000)		// Graceful Stop Complete Mask
-#define ENET_EIRM_TXF			((uint32_t)0x08000000)		// Transmit Frame Interrupt Mask
-#define ENET_EIRM_TXB			((uint32_t)0x04000000)		// Transmit Buffer Interrupt Mask
-#define ENET_EIRM_RXF			((uint32_t)0x02000000)		// Receive Frame Interrupt Mask
-#define ENET_EIRM_RXB			((uint32_t)0x01000000)		// Receive Buffer Interrupt Mask
-#define ENET_EIRM_MII			((uint32_t)0x00800000)		// MII Interrupt Mask
-#define ENET_EIRM_EBERR			((uint32_t)0x00400000)		// Ethernet Bus Error Mask
-#define ENET_EIRM_LC			((uint32_t)0x00200000)		// Late Collision Mask
-#define ENET_EIRM_RL			((uint32_t)0x00100000)		// Collision Retry Limit Mask
-#define ENET_EIRM_UN			((uint32_t)0x00080000)		// Transmit FIFO Underrun Mask
-#define ENET_EIRM_PLR			((uint32_t)0x00040000)		// Payload Receive Error Mask
-#define ENET_EIRM_WAKEUP		((uint32_t)0x00020000)		// Node Wakeup Request Indication Mask
-#define ENET_EIRM_TS_AVAIL		((uint32_t)0x00010000)		// Transmit Timestamp Available Mask
-#define ENET_EIRM_TS_TIMER		((uint32_t)0x00008000)		// Timestamp Timer Mask
+#define ENET_EIMR_BABR			((uint32_t)0x40000000)		// Babbling Receive Error Mask
+#define ENET_EIMR_BABT			((uint32_t)0x20000000)		// Babbling Transmit Error Mask
+#define ENET_EIMR_GRA			((uint32_t)0x10000000)		// Graceful Stop Complete Mask
+#define ENET_EIMR_TXF			((uint32_t)0x08000000)		// Transmit Frame Interrupt Mask
+#define ENET_EIMR_TXB			((uint32_t)0x04000000)		// Transmit Buffer Interrupt Mask
+#define ENET_EIMR_RXF			((uint32_t)0x02000000)		// Receive Frame Interrupt Mask
+#define ENET_EIMR_RXB			((uint32_t)0x01000000)		// Receive Buffer Interrupt Mask
+#define ENET_EIMR_MII			((uint32_t)0x00800000)		// MII Interrupt Mask
+#define ENET_EIMR_EBERR			((uint32_t)0x00400000)		// Ethernet Bus Error Mask
+#define ENET_EIMR_LC			((uint32_t)0x00200000)		// Late Collision Mask
+#define ENET_EIMR_RL			((uint32_t)0x00100000)		// Collision Retry Limit Mask
+#define ENET_EIMR_UN			((uint32_t)0x00080000)		// Transmit FIFO Underrun Mask
+#define ENET_EIMR_PLR			((uint32_t)0x00040000)		// Payload Receive Error Mask
+#define ENET_EIMR_WAKEUP		((uint32_t)0x00020000)		// Node Wakeup Request Indication Mask
+#define ENET_EIMR_TS_AVAIL		((uint32_t)0x00010000)		// Transmit Timestamp Available Mask
+#define ENET_EIMR_TS_TIMER		((uint32_t)0x00008000)		// Timestamp Timer Mask
 #define ENET_RDAR		(*(volatile uint32_t *)0x400C0010) // Receive Descriptor Active Register
 #define ENET_RDAR_RDAR			((uint32_t)0x01000000)
 #define ENET_TDAR		(*(volatile uint32_t *)0x400C0014) // Transmit Descriptor Active Register

teensy4/imxrt.h

@@ -1573,10 +1573,66 @@ typedef struct {
 #define CCM_ANALOG_PLL_AUDIO_ENABLE		((uint32_t)(1<<13)) 
 #define CCM_ANALOG_PLL_AUDIO_POWERDOWN		((uint32_t)(1<<12)) 
 #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(n)	((uint32_t)((n) & ((1<<6)-1)))
-
+#define CCM_ANALOG_PLL_VIDEO_LOCK		((uint32_t)(1<<31))
+#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(n)	((uint32_t)(((n) & 0x03) << 19))
+#define CCM_ANALOG_PLL_VIDEO_BYPASS		((uint32_t)(1<<16))
+#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(n)	((uint32_t)(((n) & 0x03) << 14))
+#define CCM_ANALOG_PLL_VIDEO_ENABLE		((uint32_t)(1<<13))
+#define CCM_ANALOG_PLL_VIDEO_POWERDOWN		((uint32_t)(1<<12))
+#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(n)	((uint32_t)(((n) & 0x7F) << 0))
+#define CCM_ANALOG_PLL_ENET_LOCK		((uint32_t)(1<<31))
+#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN	((uint32_t)(1<<21))
+#define CCM_ANALOG_PLL_ENET_ENET2_REF_EN	((uint32_t)(1<<20))
+#define CCM_ANALOG_PLL_ENET_BYPASS		((uint32_t)(1<<16))
+#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(n)	((uint32_t)(((n) & 0x03) << 14))
+#define CCM_ANALOG_PLL_ENET_ENABLE		((uint32_t)(1<<13))
+#define CCM_ANALOG_PLL_ENET_POWERDOWN		((uint32_t)(1<<12))
+#define CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(n)	((uint32_t)(((n) & 0x03) << 2))
+#define CCM_ANALOG_PLL_ENET_DIV_SELECT(n)	((uint32_t)(((n) & 0x03) << 0))
+#define CCM_ANALOG_MISC0_XTAL_24M_PWD		((uint32_t)(1<<30))
+#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE	((uint32_t)(1<<29))
+#define CCM_ANALOG_MISC0_CLKGATE_DELAY(n)	((uint32_t)(((n) & 0x07) << 26))
+#define CCM_ANALOG_MISC0_CLKGATE_CTRL		((uint32_t)(1<<25))
+#define CCM_ANALOG_MISC0_OSC_XTALOK_EN		((uint32_t)(1<<16))
+#define CCM_ANALOG_MISC0_OSC_XTALOK		((uint32_t)(1<<15))
+#define CCM_ANALOG_MISC0_OSC_I(n)		((uint32_t)(((n) & 0x03) << 13))
+#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS	((uint32_t)(1<<12))
+#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(n)	((uint32_t)(((n) & 0x03) << 10))
+#define CCM_ANALOG_MISC0_REFTOP_VBGUP		((uint32_t)(1<<7))
+#define CCM_ANALOG_MISC0_REFTOP_VBGADJ(n)	((uint32_t)(((n) & 0x07) << 4))
+#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF	((uint32_t)(1<<3))
+#define CCM_ANALOG_MISC0_REFTOP_PWD		((uint32_t)(1<<0))
+#define CCM_ANALOG_MISC1_IRQ_DIG_BO		((uint32_t)(1<<31))
+#define CCM_ANALOG_MISC1_IRQ_ANA_BO		((uint32_t)(1<<30))
+#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH		((uint32_t)(1<<29))
+#define CCM_ANALOG_MISC1_IRQ_TEMPLOW		((uint32_t)(1<<28))
+#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC		((uint32_t)(1<<27))
+#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN	((uint32_t)(1<<17))
+#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN	((uint32_t)(1<<16))
+#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN		((uint32_t)(1<<12))
+#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN		((uint32_t)(1<<10))
+#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL(n)	((uint32_t)(((n) & 0x1F) << 0))
+#define CCM_ANALOG_MISC2_VIDEO_DIV(n)		((uint32_t)(((n) & 0x03) << 30))
+#define CCM_ANALOG_MISC2_REG2_STEP_TIME(n)	((uint32_t)(((n) & 0x03) << 28))
+#define CCM_ANALOG_MISC2_REG1_STEP_TIME(n)	((uint32_t)(((n) & 0x03) << 26))
+#define CCM_ANALOG_MISC2_REG0_STEP_TIME(n)	((uint32_t)(((n) & 0x03) << 24))
 #define CCM_ANALOG_MISC2_DIV_MSB		((uint32_t)(1<<23))
+#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB		((uint32_t)(1<<23))
+#define CCM_ANALOG_MISC2_REG2_OK		((uint32_t)(1<<22))
+#define CCM_ANALOG_MISC2_REG2_ENABLE_BO		((uint32_t)(1<<21))
+#define CCM_ANALOG_MISC2_REG2_BO_STATUS		((uint32_t)(1<<19))
+#define CCM_ANALOG_MISC2_REG2_BO_OFFSET(n)	((uint32_t)(((n) & 0x07) << 16))
 #define CCM_ANALOG_MISC2_DIV_LSB		((uint32_t)(1<<15))
-
+#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB		((uint32_t)(1<<15))
+#define CCM_ANALOG_MISC2_REG1_OK		((uint32_t)(1<<14))
+#define CCM_ANALOG_MISC2_REG1_ENABLE_BO		((uint32_t)(1<<13))
+#define CCM_ANALOG_MISC2_REG1_BO_STATUS		((uint32_t)(1<<11))
+#define CCM_ANALOG_MISC2_REG1_BO_OFFSET(n)	((uint32_t)(((n) & 0x07) << 8))
+#define CCM_ANALOG_MISC2_PLL3_DISABLE		((uint32_t)(1<<7))
+#define CCM_ANALOG_MISC2_REG0_OK		((uint32_t)(1<<6))
+#define CCM_ANALOG_MISC2_REG0_ENABLE_BO		((uint32_t)(1<<5))
+#define CCM_ANALOG_MISC2_REG0_BO_STATUS		((uint32_t)(1<<3))
+#define CCM_ANALOG_MISC2_REG0_BO_OFFSET(n)	((uint32_t)(((n) & 0x07) << 0))
 #define CCM_ANALOG_PLL_AUDIO_NUM_MASK		(((1<<29)-1))
 #define CCM_ANALOG_PLL_AUDIO_DENOM_MASK		(((1<<29)-1))
 #define CCM_ANALOG_PLL_AUDIO_LOCK		((uint32_t)(1<<31))
@@ -2735,6 +2791,103 @@ typedef struct {
 #define ENET_TCCR2			(IMXRT_ENET_TIMER.offset21C)
 #define ENET_TCSR3			(IMXRT_ENET_TIMER.offset220)
 #define ENET_TCCR3			(IMXRT_ENET_TIMER.offset224)
+#define ENET_EIR_BABR				((uint32_t)(1<<30))
+#define ENET_EIR_BABT				((uint32_t)(1<<29))
+#define ENET_EIR_GRA				((uint32_t)(1<<28))
+#define ENET_EIR_TXF				((uint32_t)(1<<27))
+#define ENET_EIR_TXB				((uint32_t)(1<<26))
+#define ENET_EIR_RXF				((uint32_t)(1<<25))
+#define ENET_EIR_RXB				((uint32_t)(1<<24))
+#define ENET_EIR_MII				((uint32_t)(1<<23))
+#define ENET_EIR_EBERR				((uint32_t)(1<<22))
+#define ENET_EIR_LC				((uint32_t)(1<<21))
+#define ENET_EIR_RL				((uint32_t)(1<<20))
+#define ENET_EIR_UN				((uint32_t)(1<<19))
+#define ENET_EIR_PLR				((uint32_t)(1<<18))
+#define ENET_EIR_WAKEUP				((uint32_t)(1<<17))
+#define ENET_EIR_TS_AVAIL			((uint32_t)(1<<16))
+#define ENET_EIR_TS_TIMER			((uint32_t)(1<<15))
+#define ENET_EIMR_BABR				((uint32_t)(1<<30))
+#define ENET_EIMR_BABT				((uint32_t)(1<<29))
+#define ENET_EIMR_GRA				((uint32_t)(1<<28))
+#define ENET_EIMR_TXF				((uint32_t)(1<<27))
+#define ENET_EIMR_TXB				((uint32_t)(1<<26))
+#define ENET_EIMR_RXF				((uint32_t)(1<<25))
+#define ENET_EIMR_RXB				((uint32_t)(1<<24))
+#define ENET_EIMR_MII				((uint32_t)(1<<23))
+#define ENET_EIMR_EBERR				((uint32_t)(1<<22))
+#define ENET_EIMR_LC				((uint32_t)(1<<21))
+#define ENET_EIMR_RL				((uint32_t)(1<<20))
+#define ENET_EIMR_UN				((uint32_t)(1<<19))
+#define ENET_EIMR_PLR				((uint32_t)(1<<18))
+#define ENET_EIMR_WAKEUP			((uint32_t)(1<<17))
+#define ENET_EIMR_TS_AVAIL			((uint32_t)(1<<16))
+#define ENET_EIMR_TS_TIMER			((uint32_t)(1<<15))
+#define ENET_RDAR_RDAR				((uint32_t)(1<<24))
+#define ENET_TDAR_TDAR				((uint32_t)(1<<24))
+#define ENET_ECR_DBSWP				((uint32_t)(1<<8))
+#define ENET_ECR_DBGEN				((uint32_t)(1<<6))
+#define ENET_ECR_EN1588				((uint32_t)(1<<4))
+#define ENET_ECR_SLEEP				((uint32_t)(1<<3))
+#define ENET_ECR_MAGICEN			((uint32_t)(1<<2))
+#define ENET_ECR_ETHEREN			((uint32_t)(1<<1))
+#define ENET_ECR_RESET				((uint32_t)(1<<0))
+#define ENET_MMFR_ST(n)				((uint32_t)(((n) & 0x03) << 30))
+#define ENET_MMFR_OP(n)				((uint32_t)(((n) & 0x03) << 28))
+#define ENET_MMFR_PA(n)				((uint32_t)(((n) & 0x1F) << 23))
+#define ENET_MMFR_RA(n)				((uint32_t)(((n) & 0x1F) << 18))
+#define ENET_MMFR_TA(n)				((uint32_t)(((n) & 0x03) << 16))
+#define ENET_MMFR_DATA(n)			((uint32_t)(((n) & 0xFFFF) << 0))
+#define ENET_MSCR_HOLDTIME(n)			((uint32_t)(((n) & 0x07) << 8))
+#define ENET_MSCR_DIS_PRE			((uint32_t)(1<<7))
+#define ENET_MSCR_MII_SPEED(n)			((uint32_t)(((n) & 0x3F) << 1))
+#define ENET_MIBC_MIB_DIS			((uint32_t)(1<<31))
+#define ENET_MIBC_MIB_IDLE			((uint32_t)(1<<30))
+#define ENET_MIBC_MIB_CLEAR			((uint32_t)(1<<29))
+#define ENET_RCR_GRS				((uint32_t)(1<<31))
+#define ENET_RCR_NLC				((uint32_t)(1<<30))
+#define ENET_RCR_MAX_FL(n)			((uint32_t)(((n) & 0x3FFF) << 16))
+#define ENET_RCR_CFEN				((uint32_t)(1<<15))
+#define ENET_RCR_CRCFWD				((uint32_t)(1<<14))
+#define ENET_RCR_PAUFWD				((uint32_t)(1<<13))
+#define ENET_RCR_PADEN				((uint32_t)(1<<12))
+#define ENET_RCR_RMII_10T			((uint32_t)(1<<9))
+#define ENET_RCR_RMII_MODE			((uint32_t)(1<<8))
+#define ENET_RCR_FCE				((uint32_t)(1<<5))
+#define ENET_RCR_BC_REJ				((uint32_t)(1<<4))
+#define ENET_RCR_PROM				((uint32_t)(1<<3))
+#define ENET_RCR_MII_MODE			((uint32_t)(1<<2))
+#define ENET_RCR_DRT				((uint32_t)(1<<1))
+#define ENET_RCR_LOOP				((uint32_t)(1<<0))
+#define ENET_TCR_CRCFWD				((uint32_t)(1<<9))
+#define ENET_TCR_ADDINS				((uint32_t)(1<<8))
+#define ENET_TCR_ADDSEL(n)			((uint32_t)(((n) & 0x07) << 5))
+#define ENET_TCR_RFC_PAUSE			((uint32_t)(1<<4))
+#define ENET_TCR_TFC_PAUSE			((uint32_t)(1<<3))
+#define ENET_TCR_FDEN				((uint32_t)(1<<2))
+#define ENET_TCR_GTS				((uint32_t)(1<<0))
+#define ENET_PAUR_PADDR2(n)			((uint32_t)(((n) & 0xFFFF) << 16))
+#define ENET_PAUR_TYPE(n)			((uint32_t)(((n) & 0xFFFF) << 0))
+#define ENET_OPD_OPCODE(n)			((uint32_t)(((n) & 0xFFFF) << 16))
+#define ENET_OPD_PAUSE_DUR(n)			((uint32_t)(((n) & 0xFFFF) << 0))
+#define ENET_TXIC_ICEN				((uint32_t)(1<<31))
+#define ENET_TXIC_ICCS				((uint32_t)(1<<30))
+#define ENET_TXIC_ICFT(n)			((uint32_t)(((n) & 0xFF) << 20))
+#define ENET_TXIC_ICTT(n)			((uint32_t)(((n) & 0xFFFF) << 0))
+#define ENET_RXIC_ICEN				((uint32_t)(1<<31))
+#define ENET_RXIC_ICCS				((uint32_t)(1<<30))
+#define ENET_RXIC_ICFT(n)			((uint32_t)(((n) & 0xFF) << 20))
+#define ENET_RXIC_ICTT(n)			((uint32_t)(((n) & 0xFFFF) << 0))
+#define ENET_TFWR_STRFWD			((uint32_t)(1<<8))
+#define ENET_TFWR_TFWR(n)			((uint32_t)(((n) & 0x3F) << 0))
+#define ENET_TACC_PROCHK			((uint32_t)(1<<4))
+#define ENET_TACC_IPCHK				((uint32_t)(1<<3))
+#define ENET_TACC_SHIFT16			((uint32_t)(1<<0))
+#define ENET_RACC_SHIFT16			((uint32_t)(1<<7))
+#define ENET_RACC_LINEDIS			((uint32_t)(1<<6))
+#define ENET_RACC_PRODIS			((uint32_t)(1<<2))
+#define ENET_RACC_IPDIS				((uint32_t)(1<<1))
+#define ENET_RACC_PADREM			((uint32_t)(1<<0))
 
 #define IMXRT_ENET2		(*(IMXRT_REGISTER32_t *)0x402D4000)
 #define IMXRT_ENET2_TIMER	(*(IMXRT_REGISTER32_t *)0x402D4400)