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@@ -1389,6 +1389,86 @@ |
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#endif |
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#if defined(__MK20DX128__) |
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#define CORE_FTM0_CH0_PIN 22 |
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#define CORE_FTM0_CH1_PIN 23 |
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#define CORE_FTM0_CH2_PIN 9 |
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#define CORE_FTM0_CH3_PIN 10 |
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#define CORE_FTM0_CH4_PIN 6 |
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#define CORE_FTM0_CH5_PIN 20 |
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#define CORE_FTM0_CH6_PIN 21 |
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#define CORE_FTM0_CH7_PIN 5 |
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#define CORE_FTM1_CH0_PIN 3 |
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#define CORE_FTM1_CH1_PIN 4 |
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#elif defined(__MK20DX256__) |
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#define CORE_FTM0_CH0_PIN 22 |
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#define CORE_FTM0_CH1_PIN 23 |
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#define CORE_FTM0_CH2_PIN 9 |
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#define CORE_FTM0_CH3_PIN 10 |
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#define CORE_FTM0_CH4_PIN 6 |
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#define CORE_FTM0_CH5_PIN 20 |
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#define CORE_FTM0_CH6_PIN 21 |
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#define CORE_FTM0_CH7_PIN 5 |
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#define CORE_FTM1_CH0_PIN 3 |
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#define CORE_FTM1_CH1_PIN 4 |
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#define CORE_FTM2_CH0_PIN 32 |
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#define CORE_FTM2_CH1_PIN 25 |
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#elif defined(__MKL26Z64__) |
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#define CORE_TPM0_CH0_PIN 22 |
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#define CORE_TPM0_CH1_PIN 23 |
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#define CORE_TPM0_CH2_PIN 9 |
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#define CORE_TPM0_CH3_PIN 10 |
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#define CORE_TPM0_CH4_PIN 6 |
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#define CORE_TPM0_CH5_PIN 20 |
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#define CORE_TPM1_CH0_PIN 16 |
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#define CORE_TPM1_CH1_PIN 17 |
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#define CORE_TPM2_CH0_PIN 3 |
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#define CORE_TPM2_CH1_PIN 4 |
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#elif defined(__MK64FX512__) |
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#define CORE_FTM0_CH0_PIN 22 |
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#define CORE_FTM0_CH1_PIN 23 |
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#define CORE_FTM0_CH2_PIN 9 |
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#define CORE_FTM0_CH3_PIN 10 |
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#define CORE_FTM0_CH4_PIN 6 |
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#define CORE_FTM0_CH5_PIN 20 |
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#define CORE_FTM0_CH6_PIN 21 |
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#define CORE_FTM0_CH7_PIN 5 |
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#define CORE_FTM1_CH0_PIN 3 |
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#define CORE_FTM1_CH1_PIN 4 |
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#define CORE_FTM2_CH0_PIN 29 |
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#define CORE_FTM2_CH1_PIN 30 |
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#define CORE_FTM3_CH0_PIN 2 |
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#define CORE_FTM3_CH1_PIN 14 |
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#define CORE_FTM3_CH2_PIN 7 |
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#define CORE_FTM3_CH3_PIN 8 |
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#define CORE_FTM3_CH4_PIN 35 |
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#define CORE_FTM3_CH5_PIN 36 |
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#define CORE_FTM3_CH6_PIN 37 |
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#define CORE_FTM3_CH7_PIN 38 |
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#elif defined(__MK66FX1M0__) |
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#define CORE_FTM0_CH0_PIN 22 |
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#define CORE_FTM0_CH1_PIN 23 |
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#define CORE_FTM0_CH2_PIN 9 |
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#define CORE_FTM0_CH3_PIN 10 |
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#define CORE_FTM0_CH4_PIN 6 |
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#define CORE_FTM0_CH5_PIN 20 |
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#define CORE_FTM0_CH6_PIN 21 |
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#define CORE_FTM0_CH7_PIN 5 |
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#define CORE_FTM1_CH0_PIN 3 |
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#define CORE_FTM1_CH1_PIN 4 |
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#define CORE_FTM2_CH0_PIN 29 |
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#define CORE_FTM2_CH1_PIN 30 |
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#define CORE_FTM3_CH0_PIN 2 |
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#define CORE_FTM3_CH1_PIN 14 |
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#define CORE_FTM3_CH2_PIN 7 |
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#define CORE_FTM3_CH3_PIN 8 |
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#define CORE_FTM3_CH4_PIN 35 |
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#define CORE_FTM3_CH5_PIN 36 |
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#define CORE_FTM3_CH6_PIN 37 |
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#define CORE_FTM3_CH7_PIN 38 |
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#define CORE_TPM1_CH0_PIN 16 |
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#define CORE_TPM1_CH1_PIN 17 |
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#endif |
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#ifdef __cplusplus |