|
|
|
|
|
|
|
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if (len == 4) { |
|
|
if (len == 4) { |
|
|
CFG->DCR = dcr | DMA_DCR_DSIZE(0) | DMA_DCR_DSIZE(0); |
|
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CFG->DCR = dcr | DMA_DCR_DSIZE(0) | DMA_DCR_DSIZE(0); |
|
|
} else if (len == 2) { |
|
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} else if (len == 2) { |
|
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CFG->DCR = dcr | DMA_DCR_DSIZE(0) | DMA_DCR_DSIZE(0); |
|
|
|
|
|
|
|
|
CFG->DCR = dcr | DMA_DCR_DSIZE(2) | DMA_DCR_DSIZE(2); |
|
|
} else { |
|
|
} else { |
|
|
CFG->DCR = dcr | DMA_DCR_DSIZE(0) | DMA_DCR_DSIZE(0); |
|
|
|
|
|
|
|
|
CFG->DCR = dcr | DMA_DCR_DSIZE(1) | DMA_DCR_DSIZE(1); |
|
|
} |
|
|
} |
|
|
} |
|
|
} |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// Use a hardware trigger to make the DMA channel run |
|
|
// Use a hardware trigger to make the DMA channel run |
|
|
void triggerAtHardwareEvent(uint8_t source) { |
|
|
void triggerAtHardwareEvent(uint8_t source) { |
|
|
volatile uint8_t *mux; |
|
|
volatile uint8_t *mux; |
|
|
|
|
|
CFG->DCR |= DMA_DCR_CS; |
|
|
mux = (volatile uint8_t *)&(DMAMUX0_CHCFG0) + channel; |
|
|
mux = (volatile uint8_t *)&(DMAMUX0_CHCFG0) + channel; |
|
|
*mux = 0; |
|
|
*mux = 0; |
|
|
*mux = (source & 63) | DMAMUX_ENABLE; |
|
|
*mux = (source & 63) | DMAMUX_ENABLE; |
|
|
CFG->DCR |= (DMA_DCR_ERQ | DMA_DCR_CS); |
|
|
|
|
|
} |
|
|
} |
|
|
|
|
|
|
|
|
// Use another DMA channel as the trigger, causing this |
|
|
// Use another DMA channel as the trigger, causing this |
|
|
|
|
|
|
|
|
/***************************************/ |
|
|
/***************************************/ |
|
|
|
|
|
|
|
|
void enable(void) { |
|
|
void enable(void) { |
|
|
|
|
|
CFG->DCR |= DMA_DCR_ERQ; |
|
|
} |
|
|
} |
|
|
void disable(void) { |
|
|
void disable(void) { |
|
|
|
|
|
CFG->DCR &= ~DMA_DCR_ERQ; |
|
|
} |
|
|
} |
|
|
|
|
|
|
|
|
/***************************************/ |
|
|
/***************************************/ |