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FLEXSPI_LUTCR = FLEXSPI_LUTCR_UNLOCK; |
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FLEXSPI_LUTCR = FLEXSPI_LUTCR_UNLOCK; |
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FLEXSPI_IPCR0 = 0; |
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FLEXSPI_IPCR0 = 0; |
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FLEXSPI_LUT60 = LUT0(CMD_SDR, PINS1, 0x06); // 06 = write enable |
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FLEXSPI_LUT60 = LUT0(CMD_SDR, PINS1, 0x06); // 06 = write enable |
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FLEXSPI_LUT61 = 0; |
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FLEXSPI_LUT62 = 0; |
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FLEXSPI_LUT63 = 0; |
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FLEXSPI_IPCR1 = FLEXSPI_IPCR1_ISEQID(15); |
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FLEXSPI_IPCR1 = FLEXSPI_IPCR1_ISEQID(15); |
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FLEXSPI_IPCMD = FLEXSPI_IPCMD_TRG; |
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FLEXSPI_IPCMD = FLEXSPI_IPCMD_TRG; |
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arm_dcache_delete(addr, len); // purge old data from ARM's cache |
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arm_dcache_delete(addr, len); // purge old data from ARM's cache |
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FLEXSPI_LUTKEY = FLEXSPI_LUTKEY_VALUE; |
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FLEXSPI_LUTKEY = FLEXSPI_LUTKEY_VALUE; |
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FLEXSPI_LUTCR = FLEXSPI_LUTCR_UNLOCK; |
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FLEXSPI_LUTCR = FLEXSPI_LUTCR_UNLOCK; |
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FLEXSPI_LUT60 = LUT0(CMD_SDR, PINS1, 0x06); // 06 = write enable |
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FLEXSPI_LUT60 = LUT0(CMD_SDR, PINS1, 0x06); // 06 = write enable |
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FLEXSPI_LUT61 = 0; |
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FLEXSPI_LUT62 = 0; |
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FLEXSPI_LUT63 = 0; |
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FLEXSPI_IPCR0 = 0; |
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FLEXSPI_IPCR0 = 0; |
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FLEXSPI_IPCR1 = FLEXSPI_IPCR1_ISEQID(15); |
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FLEXSPI_IPCR1 = FLEXSPI_IPCR1_ISEQID(15); |
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FLEXSPI_IPCMD = FLEXSPI_IPCMD_TRG; |
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FLEXSPI_IPCMD = FLEXSPI_IPCMD_TRG; |
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while (!(FLEXSPI_INTR & FLEXSPI_INTR_IPCMDDONE)) ; // wait |
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while (!(FLEXSPI_INTR & FLEXSPI_INTR_IPCMDDONE)) ; // wait |
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FLEXSPI_INTR = FLEXSPI_INTR_IPCMDDONE; |
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FLEXSPI_INTR = FLEXSPI_INTR_IPCMDDONE; |
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FLEXSPI_LUT60 = LUT0(CMD_SDR, PINS1, 0x20) | LUT1(ADDR_SDR, PINS1, 24); // 20 = sector erase |
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FLEXSPI_LUT60 = LUT0(CMD_SDR, PINS1, 0x20) | LUT1(ADDR_SDR, PINS1, 24); // 20 = sector erase |
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FLEXSPI_LUT61 = 0; |
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FLEXSPI_IPCR0 = (uint32_t)addr & 0x001FF000; |
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FLEXSPI_IPCR0 = (uint32_t)addr & 0x001FF000; |
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FLEXSPI_IPCR1 = FLEXSPI_IPCR1_ISEQID(15); |
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FLEXSPI_IPCR1 = FLEXSPI_IPCR1_ISEQID(15); |
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FLEXSPI_IPCMD = FLEXSPI_IPCMD_TRG; |
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FLEXSPI_IPCMD = FLEXSPI_IPCMD_TRG; |