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#define CORE_PIN38_PORTCLEAR GPIO8_DR_CLEAR |
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#define CORE_PIN38_PORTCLEAR GPIO8_DR_CLEAR |
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#define CORE_PIN39_PORTCLEAR GPIO8_DR_CLEAR |
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#define CORE_PIN39_PORTCLEAR GPIO8_DR_CLEAR |
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#define CORE_PIN0_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN1_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN2_PORTTOGGLE GPIO9_DR_TOGGLE |
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#define CORE_PIN3_PORTTOGGLE GPIO9_DR_TOGGLE |
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#define CORE_PIN4_PORTTOGGLE GPIO9_DR_TOGGLE |
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#define CORE_PIN5_PORTTOGGLE GPIO9_DR_TOGGLE |
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#define CORE_PIN6_PORTTOGGLE GPIO7_DR_TOGGLE |
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#define CORE_PIN7_PORTTOGGLE GPIO7_DR_TOGGLE |
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#define CORE_PIN8_PORTTOGGLE GPIO7_DR_TOGGLE |
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#define CORE_PIN9_PORTTOGGLE GPIO7_DR_TOGGLE |
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#define CORE_PIN10_PORTTOGGLE GPIO7_DR_TOGGLE |
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#define CORE_PIN11_PORTTOGGLE GPIO7_DR_TOGGLE |
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#define CORE_PIN12_PORTTOGGLE GPIO7_DR_TOGGLE |
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#define CORE_PIN13_PORTTOGGLE GPIO7_DR_TOGGLE |
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#define CORE_PIN14_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN15_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN16_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN17_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN18_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN19_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN20_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN21_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN22_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN23_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN24_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN25_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN26_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN27_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN28_PORTTOGGLE GPIO8_DR_TOGGLE |
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#define CORE_PIN29_PORTTOGGLE GPIO9_DR_TOGGLE |
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#define CORE_PIN30_PORTTOGGLE GPIO8_DR_TOGGLE |
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#define CORE_PIN31_PORTTOGGLE GPIO8_DR_TOGGLE |
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#define CORE_PIN32_PORTTOGGLE GPIO7_DR_TOGGLE |
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#define CORE_PIN33_PORTTOGGLE GPIO9_DR_TOGGLE |
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#define CORE_PIN34_PORTTOGGLE GPIO8_DR_TOGGLE |
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#define CORE_PIN35_PORTTOGGLE GPIO8_DR_TOGGLE |
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#define CORE_PIN36_PORTTOGGLE GPIO8_DR_TOGGLE |
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#define CORE_PIN37_PORTTOGGLE GPIO8_DR_TOGGLE |
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#define CORE_PIN38_PORTTOGGLE GPIO8_DR_TOGGLE |
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#define CORE_PIN39_PORTTOGGLE GPIO8_DR_TOGGLE |
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#define CORE_PIN0_DDRREG GPIO6_GDIR |
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#define CORE_PIN0_DDRREG GPIO6_GDIR |
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#define CORE_PIN1_DDRREG GPIO6_GDIR |
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#define CORE_PIN1_DDRREG GPIO6_GDIR |
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#define CORE_PIN2_DDRREG GPIO9_GDIR |
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#define CORE_PIN2_DDRREG GPIO9_GDIR |
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#define CORE_PIN53_PORTCLEAR GPIO9_DR_CLEAR |
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#define CORE_PIN53_PORTCLEAR GPIO9_DR_CLEAR |
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#define CORE_PIN54_PORTCLEAR GPIO9_DR_CLEAR |
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#define CORE_PIN54_PORTCLEAR GPIO9_DR_CLEAR |
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#define CORE_PIN0_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN1_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN2_PORTTOGGLE GPIO9_DR_TOGGLE |
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#define CORE_PIN3_PORTTOGGLE GPIO9_DR_TOGGLE |
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#define CORE_PIN4_PORTTOGGLE GPIO9_DR_TOGGLE |
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#define CORE_PIN5_PORTTOGGLE GPIO9_DR_TOGGLE |
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#define CORE_PIN6_PORTTOGGLE GPIO7_DR_TOGGLE |
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#define CORE_PIN7_PORTTOGGLE GPIO7_DR_TOGGLE |
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#define CORE_PIN8_PORTTOGGLE GPIO7_DR_TOGGLE |
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#define CORE_PIN9_PORTTOGGLE GPIO7_DR_TOGGLE |
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#define CORE_PIN10_PORTTOGGLE GPIO7_DR_TOGGLE |
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#define CORE_PIN11_PORTTOGGLE GPIO7_DR_TOGGLE |
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#define CORE_PIN12_PORTTOGGLE GPIO7_DR_TOGGLE |
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#define CORE_PIN13_PORTTOGGLE GPIO7_DR_TOGGLE |
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#define CORE_PIN14_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN15_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN16_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN17_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN18_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN19_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN20_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN21_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN22_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN23_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN24_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN25_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN26_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN27_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN28_PORTTOGGLE GPIO8_DR_TOGGLE |
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#define CORE_PIN29_PORTTOGGLE GPIO9_DR_TOGGLE |
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#define CORE_PIN30_PORTTOGGLE GPIO8_DR_TOGGLE |
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#define CORE_PIN31_PORTTOGGLE GPIO8_DR_TOGGLE |
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#define CORE_PIN32_PORTTOGGLE GPIO7_DR_TOGGLE |
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#define CORE_PIN33_PORTTOGGLE GPIO9_DR_TOGGLE |
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#define CORE_PIN34_PORTTOGGLE GPIO7_DR_TOGGLE |
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#define CORE_PIN35_PORTTOGGLE GPIO7_DR_TOGGLE |
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#define CORE_PIN36_PORTTOGGLE GPIO7_DR_TOGGLE |
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#define CORE_PIN37_PORTTOGGLE GPIO7_DR_TOGGLE |
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#define CORE_PIN38_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN39_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN40_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN41_PORTTOGGLE GPIO6_DR_TOGGLE |
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#define CORE_PIN42_PORTTOGGLE GPIO8_DR_TOGGLE |
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#define CORE_PIN43_PORTTOGGLE GPIO8_DR_TOGGLE |
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#define CORE_PIN44_PORTTOGGLE GPIO8_DR_TOGGLE |
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#define CORE_PIN45_PORTTOGGLE GPIO8_DR_TOGGLE |
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#define CORE_PIN46_PORTTOGGLE GPIO8_DR_TOGGLE |
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#define CORE_PIN47_PORTTOGGLE GPIO8_DR_TOGGLE |
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#define CORE_PIN48_PORTTOGGLE GPIO9_DR_TOGGLE |
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#define CORE_PIN49_PORTTOGGLE GPIO9_DR_TOGGLE |
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#define CORE_PIN50_PORTTOGGLE GPIO9_DR_TOGGLE |
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#define CORE_PIN51_PORTTOGGLE GPIO9_DR_TOGGLE |
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#define CORE_PIN52_PORTTOGGLE GPIO9_DR_TOGGLE |
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#define CORE_PIN53_PORTTOGGLE GPIO9_DR_TOGGLE |
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#define CORE_PIN54_PORTTOGGLE GPIO9_DR_TOGGLE |
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#define CORE_PIN0_DDRREG GPIO6_GDIR |
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#define CORE_PIN0_DDRREG GPIO6_GDIR |
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#define CORE_PIN1_DDRREG GPIO6_GDIR |
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#define CORE_PIN1_DDRREG GPIO6_GDIR |
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#define CORE_PIN2_DDRREG GPIO9_GDIR |
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#define CORE_PIN2_DDRREG GPIO9_GDIR |
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} |
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} |
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} |
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} |
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void digitalToggle(uint8_t pin); |
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static inline void digitalToggleFast(uint8_t pin) __attribute__((always_inline, unused)); |
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static inline void digitalToggleFast(uint8_t pin) |
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{ |
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if (__builtin_constant_p(pin)) { |
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if (pin == 0) { |
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CORE_PIN0_PORTTOGGLE = CORE_PIN0_BITMASK; |
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} else if (pin == 1) { |
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CORE_PIN1_PORTTOGGLE = CORE_PIN1_BITMASK; |
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} else if (pin == 2) { |
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CORE_PIN2_PORTTOGGLE = CORE_PIN2_BITMASK; |
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} else if (pin == 3) { |
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CORE_PIN3_PORTTOGGLE = CORE_PIN3_BITMASK; |
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} else if (pin == 4) { |
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CORE_PIN4_PORTTOGGLE = CORE_PIN4_BITMASK; |
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} else if (pin == 5) { |
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CORE_PIN5_PORTTOGGLE = CORE_PIN5_BITMASK; |
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} else if (pin == 6) { |
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CORE_PIN6_PORTTOGGLE = CORE_PIN6_BITMASK; |
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} else if (pin == 7) { |
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CORE_PIN7_PORTTOGGLE = CORE_PIN7_BITMASK; |
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} else if (pin == 8) { |
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CORE_PIN8_PORTTOGGLE = CORE_PIN8_BITMASK; |
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} else if (pin == 9) { |
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CORE_PIN9_PORTTOGGLE = CORE_PIN9_BITMASK; |
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} else if (pin == 10) { |
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CORE_PIN10_PORTTOGGLE = CORE_PIN10_BITMASK; |
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} else if (pin == 11) { |
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CORE_PIN11_PORTTOGGLE = CORE_PIN11_BITMASK; |
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} else if (pin == 12) { |
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CORE_PIN12_PORTTOGGLE = CORE_PIN12_BITMASK; |
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} else if (pin == 13) { |
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CORE_PIN13_PORTTOGGLE = CORE_PIN13_BITMASK; |
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} else if (pin == 14) { |
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CORE_PIN14_PORTTOGGLE = CORE_PIN14_BITMASK; |
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} else if (pin == 15) { |
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CORE_PIN15_PORTTOGGLE = CORE_PIN15_BITMASK; |
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} else if (pin == 16) { |
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CORE_PIN16_PORTTOGGLE = CORE_PIN16_BITMASK; |
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} else if (pin == 17) { |
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CORE_PIN17_PORTTOGGLE = CORE_PIN17_BITMASK; |
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} else if (pin == 18) { |
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CORE_PIN18_PORTTOGGLE = CORE_PIN18_BITMASK; |
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} else if (pin == 19) { |
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CORE_PIN19_PORTTOGGLE = CORE_PIN19_BITMASK; |
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} else if (pin == 20) { |
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CORE_PIN20_PORTTOGGLE = CORE_PIN20_BITMASK; |
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} else if (pin == 21) { |
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CORE_PIN21_PORTTOGGLE = CORE_PIN21_BITMASK; |
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} else if (pin == 22) { |
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CORE_PIN22_PORTTOGGLE = CORE_PIN22_BITMASK; |
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} else if (pin == 23) { |
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CORE_PIN23_PORTTOGGLE = CORE_PIN23_BITMASK; |
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} else if (pin == 24) { |
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CORE_PIN24_PORTTOGGLE = CORE_PIN24_BITMASK; |
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} else if (pin == 25) { |
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CORE_PIN25_PORTTOGGLE = CORE_PIN25_BITMASK; |
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} else if (pin == 26) { |
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CORE_PIN26_PORTTOGGLE = CORE_PIN26_BITMASK; |
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} else if (pin == 27) { |
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CORE_PIN27_PORTTOGGLE = CORE_PIN27_BITMASK; |
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} else if (pin == 28) { |
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CORE_PIN28_PORTTOGGLE = CORE_PIN28_BITMASK; |
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} else if (pin == 29) { |
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CORE_PIN29_PORTTOGGLE = CORE_PIN29_BITMASK; |
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} else if (pin == 30) { |
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CORE_PIN30_PORTTOGGLE = CORE_PIN30_BITMASK; |
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} else if (pin == 31) { |
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CORE_PIN31_PORTTOGGLE = CORE_PIN31_BITMASK; |
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} else if (pin == 32) { |
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CORE_PIN32_PORTTOGGLE = CORE_PIN32_BITMASK; |
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} else if (pin == 33) { |
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CORE_PIN33_PORTTOGGLE = CORE_PIN33_BITMASK; |
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} else if (pin == 34) { |
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CORE_PIN34_PORTTOGGLE = CORE_PIN34_BITMASK; |
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} else if (pin == 35) { |
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CORE_PIN35_PORTTOGGLE = CORE_PIN35_BITMASK; |
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} else if (pin == 36) { |
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CORE_PIN36_PORTTOGGLE = CORE_PIN36_BITMASK; |
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} else if (pin == 37) { |
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CORE_PIN37_PORTTOGGLE = CORE_PIN37_BITMASK; |
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} else if (pin == 38) { |
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CORE_PIN38_PORTTOGGLE = CORE_PIN38_BITMASK; |
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} else if (pin == 39) { |
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CORE_PIN39_PORTTOGGLE = CORE_PIN39_BITMASK; |
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#if CORE_NUM_DIGITAL >= 55 |
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} else if (pin == 40) { |
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CORE_PIN40_PORTTOGGLE = CORE_PIN40_BITMASK; |
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} else if (pin == 41) { |
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CORE_PIN41_PORTTOGGLE = CORE_PIN41_BITMASK; |
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} else if (pin == 42) { |
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CORE_PIN42_PORTTOGGLE = CORE_PIN42_BITMASK; |
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} else if (pin == 43) { |
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CORE_PIN43_PORTTOGGLE = CORE_PIN43_BITMASK; |
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} else if (pin == 44) { |
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CORE_PIN44_PORTTOGGLE = CORE_PIN44_BITMASK; |
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} else if (pin == 45) { |
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CORE_PIN45_PORTTOGGLE = CORE_PIN45_BITMASK; |
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} else if (pin == 46) { |
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CORE_PIN46_PORTTOGGLE = CORE_PIN46_BITMASK; |
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} else if (pin == 47) { |
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CORE_PIN47_PORTTOGGLE = CORE_PIN47_BITMASK; |
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} else if (pin == 48) { |
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CORE_PIN48_PORTTOGGLE = CORE_PIN48_BITMASK; |
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} else if (pin == 49) { |
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CORE_PIN49_PORTTOGGLE = CORE_PIN49_BITMASK; |
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} else if (pin == 50) { |
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CORE_PIN50_PORTTOGGLE = CORE_PIN50_BITMASK; |
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} else if (pin == 51) { |
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CORE_PIN51_PORTTOGGLE = CORE_PIN51_BITMASK; |
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} else if (pin == 52) { |
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CORE_PIN52_PORTTOGGLE = CORE_PIN52_BITMASK; |
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} else if (pin == 53) { |
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CORE_PIN53_PORTTOGGLE = CORE_PIN53_BITMASK; |
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} else if (pin == 54) { |
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CORE_PIN54_PORTTOGGLE = CORE_PIN54_BITMASK; |
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} |
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#endif |
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} else { |
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digitalToggle(pin); |
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} |
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} |
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void pinMode(uint8_t pin, uint8_t mode); |
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void pinMode(uint8_t pin, uint8_t mode); |
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void init_pins(void); |
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void init_pins(void); |