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#define CSI_CSICR18 (IMXRT_CSI.offset048) |
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#define CSI_CSICR18 (IMXRT_CSI.offset048) |
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#define CSI_CSICR19 (IMXRT_CSI.offset04C) |
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#define CSI_CSICR19 (IMXRT_CSI.offset04C) |
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#define CSI_CSICR1_SWAP16_EN ((uint32_t)(1<<31)) |
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#define CSI_CSICR1_EXT_VSYNC ((uint32_t)(1<<30)) |
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#define CSI_CSICR1_EOF_INT_EN ((uint32_t)(1<<29)) |
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#define CSI_CSICR1_PrP_IF_EN ((uint32_t)(1<<28)) |
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#define CSI_CSICR1_CCIR_MODE ((uint32_t)(1<<27)) |
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#define CSI_CSICR1_COF_INT_EN ((uint32_t)(1<<26)) |
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#define CSI_CSICR1_SF_OR_INTEN ((uint32_t)(1<<25)) |
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#define CSI_CSICR1_RF_OR_INTEN ((uint32_t)(1<<24)) |
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#define CSI_CSICR1_SFF_DMA_DONE_INTEN ((uint32_t)(1<<22)) |
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#define CSI_CSICR1_STATFF_INTEN ((uint32_t)(1<<21)) |
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#define CSI_CSICR1_FB2_DMA_DONE_INTEN ((uint32_t)(1<<20)) |
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#define CSI_CSICR1_FB1_DMA_DONE_INTEN ((uint32_t)(1<<19)) |
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#define CSI_CSICR1_RXFF_INTEN ((uint32_t)(1<<18)) |
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#define CSI_CSICR1_SOF_POL ((uint32_t)(1<<17)) |
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#define CSI_CSICR1_SOF_INTEN ((uint32_t)(1<<16)) |
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#define CSI_CSICR1_HSYNC_POL ((uint32_t)(1<<11)) |
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#define CSI_CSICR1_CCIR_EN ((uint32_t)(1<<10)) |
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#define CSI_CSICR1_FCC ((uint32_t)(1<<8)) |
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#define CSI_CSICR1_PACK_DIR ((uint32_t)(1<<7)) |
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#define CSI_CSICR1_CLR_STATFIFO ((uint32_t)(1<<6)) |
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#define CSI_CSICR1_CLR_RXFIFO ((uint32_t)(1<<5)) |
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#define CSI_CSICR1_GCLK_MODE ((uint32_t)(1<<4)) |
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#define CSI_CSICR1_INV_DATA ((uint32_t)(1<<3)) |
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#define CSI_CSICR1_INV_PCLK ((uint32_t)(1<<2)) |
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#define CSI_CSICR1_REDGE ((uint32_t)(1<<1)) |
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#define CSI_CSICR1_PIXEL_BIT ((uint32_t)(1<<0)) |
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#define CSI_CSICR2_DMA_BURST_TYPE_RFF(n) ((uint32_t)(((n) & 0x3)<<30)) |
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#define CSI_CSICR2_DMA_BURST_TYPE_SFF(n) ((uint32_t)(((n) & 0x3)<<28)) |
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#define CSI_CSICR2_DRM ((uint32_t)(1<<26)) |
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#define CSI_CSICR2_AFS(n) ((uint32_t)(((n) & 0x3)<<24)) |
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#define CSI_CSICR2_SCE ((uint32_t)(1<<23)) |
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#define CSI_CSICR2_BTS(n) ((uint32_t)(((n) & 0x3)<<19)) |
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#define CSI_CSICR2_LVRM(n) ((uint32_t)(((n) & 0x7)<<16)) |
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#define CSI_CSICR2_VSC(n) ((uint32_t)(((n) & 0xff)<<8)) |
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#define CSI_CSICR2_HSC(n) ((uint32_t)(((n) & 0xff)<<0)) |
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#define CSI_CSICR3_FRMCNT(n) ((uint32_t)(((n) & 0xffff)<<16)) |
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#define CSI_CSICR3_FRMCNT_RST ((uint32_t)(1<<15)) |
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#define CSI_CSICR3_DMA_REFLASH_RFF ((uint32_t)(1<<14)) |
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#define CSI_CSICR3_DMA_REFLASH_SFF ((uint32_t)(1<<13)) |
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#define CSI_CSICR3_DMA_REQ_EN_RFF ((uint32_t)(1<<12)) |
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#define CSI_CSICR3_DMA_REQ_EN_SFF ((uint32_t)(1<<11)) |
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#define CSI_CSICR3_STATFF_LEVEL(n) ((uint32_t)(((n) & 0x7)<<8)) |
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#define CSI_CSICR3_HRESP_ERR_EN ((uint32_t)(1<<7)) |
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#define CSI_CSICR3_RxFF_LEVEL(n) ((uint32_t)(((n) & 0x7)<<4)) |
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#define CSI_CSICR3_TWO_8BIT_SENSOR ((uint32_t)(1<<3)) |
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#define CSI_CSICR3_ZERO_PACK_EN ((uint32_t)(1<<2)) |
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#define CSI_CSICR3_ECC_INT_EN ((uint32_t)(1<<1)) |
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#define CSI_CSICR3_ECC_AUTO_EN ((uint32_t)(1<<0)) |
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#define CSI_CSISR_BASEADDR_CHHANGE_ERROR ((uint32_t)(1<<28)) |
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#define CSI_CSISR_DMA_FIELD0_DONE ((uint32_t)(1<<27)) |
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#define CSI_CSISR_DMA_FIELD1_DONE ((uint32_t)(1<<26)) |
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#define CSI_CSISR_SF_OR_INT ((uint32_t)(1<<25)) |
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#define CSI_CSISR_RF_OR_INT ((uint32_t)(1<<24)) |
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#define CSI_CSISR_DMA_TSF_DONE_SFF ((uint32_t)(1<<22)) |
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#define CSI_CSISR_STATFF_INT ((uint32_t)(1<<21)) |
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#define CSI_CSISR_DMA_TSF_DONE_FB2 ((uint32_t)(1<<20)) |
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#define CSI_CSISR_DMA_TSF_DONE_FB1 ((uint32_t)(1<<19)) |
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#define CSI_CSISR_RxFF_INT ((uint32_t)(1<<18)) |
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#define CSI_CSISR_EOF_INT ((uint32_t)(1<<17)) |
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#define CSI_CSISR_SOF_INT ((uint32_t)(1<<16)) |
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#define CSI_CSISR_F2_INT ((uint32_t)(1<<15)) |
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#define CSI_CSISR_F1_INT ((uint32_t)(1<<14)) |
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#define CSI_CSISR_COF_INT ((uint32_t)(1<<13)) |
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#define CSI_CSISR_HRESP_ERR_INT ((uint32_t)(1<<7)) |
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#define CSI_CSISR_ECC_INT ((uint32_t)(1<<1)) |
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#define CSI_CSISR_DRDY ((uint32_t)(1<<0)) |
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#define CSI_CSICR3_CSI_ENABLE ((uint32_t)(1<<31)) |
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#define CSI_CSICR18_MASK_OPTION(n) ((uint32_t)(((n) & 0x3)<<18)) |
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#define CSI_CSICR18_AHB_HPROT(n) ((uint32_t)(((n) & 0xf)<<12)) |
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#define CSI_CSICR18_RGB888A_FORMAT_SEL ((uint32_t)(1<<10)) |
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#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE ((uint32_t)(1<<9)) |
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#define CSI_CSICR18_LAST_DMA_REQ_SEL ((uint32_t)(1<<8)) |
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#define CSI_CSICR18_DMA_FIELD1_DONE_IE ((uint32_t)(1<<7)) |
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#define CSI_CSICR18_FIELD0_DONE_IE ((uint32_t)(1<<6)) |
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#define CSI_CSICR18_BASEADDR_SWITCH_SEL ((uint32_t)(1<<5)) |
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#define CSI_CSICR18_BASEADDR_SWITCH_EN ((uint32_t)(1<<4)) |
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#define CSI_CSICR18_PARALLEL24_EN ((uint32_t)(1<<3)) |
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#define CSI_CSICR18_DEINTERLACE_EN ((uint32_t)(1<<2)) |
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#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(n) ((uint32_t)(((n) & 0xf)<<12)) |
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// 18.7.1.1: page 1209 |
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// 18.7.1.1: page 1209 |
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#define IMXRT_DCDC (*(IMXRT_REGISTER32_t *)0x40080000) |
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#define IMXRT_DCDC (*(IMXRT_REGISTER32_t *)0x40080000) |
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#define DCDC_REG0 (IMXRT_DCDC.offset000) |
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#define DCDC_REG0 (IMXRT_DCDC.offset000) |