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#define SCB_VTOR (*(volatile uint32_t *)0xE000ED08) // Vector Table Offset |
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#define SCB_VTOR (*(volatile uint32_t *)0xE000ED08) // Vector Table Offset |
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#define SCB_AIRCR (*(volatile uint32_t *)0xE000ED0C) // Application Interrupt and Reset Control |
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#define SCB_AIRCR (*(volatile uint32_t *)0xE000ED0C) // Application Interrupt and Reset Control |
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#define SCB_SCR (*(volatile uint32_t *)0xE000ED10) // System Control Register |
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#define SCB_SCR (*(volatile uint32_t *)0xE000ED10) // System Control Register |
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#define SCB_SCR_SEVONPEND ((uint8_t)0x10) // Send Event on Pending bit |
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#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) // Sleep or Deep Sleep |
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#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) // Sleep-on-exit |
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#define SCB_CCR (*(volatile uint32_t *)0xE000ED14) // Configuration and Control |
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#define SCB_CCR (*(volatile uint32_t *)0xE000ED14) // Configuration and Control |
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#define SCB_SHPR1 (*(volatile uint32_t *)0xE000ED18) // System Handler Priority Register 1 |
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#define SCB_SHPR1 (*(volatile uint32_t *)0xE000ED18) // System Handler Priority Register 1 |
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#define SCB_SHPR2 (*(volatile uint32_t *)0xE000ED1C) // System Handler Priority Register 2 |
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#define SCB_SHPR2 (*(volatile uint32_t *)0xE000ED1C) // System Handler Priority Register 2 |