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Use IRC48M clock for USB when F_CPU is 180 or 216 MHz

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PaulStoffregen преди 8 години
родител
ревизия
7a2c0037b8
променени са 2 файла, в които са добавени 10 реда и са изтрити 6 реда
  1. +1
    -0
      teensy3/kinetis.h
  2. +9
    -6
      teensy3/mk20dx128.c

+ 1
- 0
teensy3/kinetis.h Целия файл

@@ -1035,6 +1035,7 @@ enum IRQ_NUMBER_t {
#define SIM_SOPT2_RMIISRC ((uint32_t)0x00080000) // 0=external, 1=external 1588
#define SIM_SOPT2_USBSRC ((uint32_t)0x00040000) // 0=USB_CLKIN, 1=FFL/PLL
#define SIM_SOPT2_PLLFLLSEL ((uint32_t)0x00010000) // 0=FLL, 1=PLL
#define SIM_SOPT2_IRC48SEL ((uint32_t)0x00030000) // 0=FLL, 1=PLL
#define SIM_SOPT2_TRACECLKSEL ((uint32_t)0x00001000) // 0=MCGOUTCLK, 1=CPU
#define SIM_SOPT2_PTD7PAD ((uint32_t)0x00000800) // 0=normal, 1=double drive PTD7
#define SIM_SOPT2_FBSL(n) ((uint32_t)(((n) & 3) << 8)) // FlexBus security level

+ 9
- 6
teensy3/mk20dx128.c Целия файл

@@ -891,19 +891,19 @@ void ResetHandler(void)
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(3) | SIM_CLKDIV1_OUTDIV4(7);
SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(4);
#elif F_CPU == 216000000
// config divisors: 216 MHz core, 54 MHz bus, 27 MHz flash, USB = not feasible
// config divisors: 216 MHz core, 54 MHz bus, 27 MHz flash, USB = IRC48M
// TODO: gradual ramp-up for HSRUN mode
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(3) | SIM_CLKDIV1_OUTDIV4(7);
SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(8) | SIM_CLKDIV2_USBFRAC;
SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(0);
#elif F_CPU == 192000000
// config divisors: 192 MHz core, 48 MHz bus, 27.4 MHz flash, USB = 192 / 4
// TODO: gradual ramp-up for HSRUN mode
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(3) | SIM_CLKDIV1_OUTDIV4(6);
SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(3);
#elif F_CPU == 180000000
// config divisors: 180 MHz core, 60 MHz bus, 25.7 MHz flash, USB = not feasible
// config divisors: 180 MHz core, 60 MHz bus, 25.7 MHz flash, USB = IRC48M
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(2) | SIM_CLKDIV1_OUTDIV4(6);
SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(6) | SIM_CLKDIV2_USBFRAC;
SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(0);
#elif F_CPU == 168000000
// config divisors: 168 MHz core, 56 MHz bus, 28 MHz flash, USB = 168 * 2 / 7
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(2) | SIM_CLKDIV1_OUTDIV4(5);
@@ -988,8 +988,11 @@ void ResetHandler(void)
// now we're in PEE mode
// USB uses PLL clock, trace is CPU clock, CLKOUT=OSCERCLK0
#if defined(KINETISK)
SIM_SOPT2 = SIM_SOPT2_USBSRC | SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_TRACECLKSEL
| SIM_SOPT2_CLKOUTSEL(6);
#if F_CPU == 216000000 || F_CPU == 180000000
SIM_SOPT2 = SIM_SOPT2_USBSRC | SIM_SOPT2_IRC48SEL | SIM_SOPT2_TRACECLKSEL | SIM_SOPT2_CLKOUTSEL(6);
#else
SIM_SOPT2 = SIM_SOPT2_USBSRC | SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_TRACECLKSEL | SIM_SOPT2_CLKOUTSEL(6);
#endif
#elif defined(KINETISL)
SIM_SOPT2 = SIM_SOPT2_USBSRC | SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_CLKOUTSEL(6)
| SIM_SOPT2_UART0SRC(1) | SIM_SOPT2_TPMSRC(1);

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