Add extra K66 pin defines

teensy3/core_pins.h

 #define CORE_NUM_ANALOG         13
 #define CORE_NUM_PWM            10
 #elif defined(__MK64FX512__) || defined(__MK66FX1M0__)
-#define CORE_NUM_TOTAL_PINS     40
-#define CORE_NUM_DIGITAL        40
-#define CORE_NUM_INTERRUPT      40
+#define CORE_NUM_TOTAL_PINS     58
+#define CORE_NUM_DIGITAL        58
+#define CORE_NUM_INTERRUPT      58
 #define CORE_NUM_ANALOG         23
 #define CORE_NUM_PWM            20
 #endif
 #define CORE_PIN37_BIT		10
 #define CORE_PIN38_BIT		11
 #define CORE_PIN39_BIT		17
+#define CORE_PIN40_BIT		28
+#define CORE_PIN41_BIT		29
+#define CORE_PIN42_BIT		26
+#define CORE_PIN43_BIT		20
+#define CORE_PIN44_BIT		22
+#define CORE_PIN45_BIT		23
+#define CORE_PIN46_BIT		21
+#define CORE_PIN47_BIT		8
+#define CORE_PIN48_BIT		9
+#define CORE_PIN49_BIT		4
+#define CORE_PIN50_BIT		5
+#define CORE_PIN51_BIT		14
+#define CORE_PIN52_BIT		13
+#define CORE_PIN53_BIT		12
+#define CORE_PIN54_BIT		15
+#define CORE_PIN55_BIT		11
+#define CORE_PIN56_BIT		10
+#define CORE_PIN57_BIT		11
 
 #define CORE_PIN0_BITMASK	(1<<(CORE_PIN0_BIT))
 #define CORE_PIN1_BITMASK	(1<<(CORE_PIN1_BIT))
 #define CORE_PIN37_BITMASK	(1<<(CORE_PIN37_BIT))
 #define CORE_PIN38_BITMASK	(1<<(CORE_PIN38_BIT))
 #define CORE_PIN39_BITMASK	(1<<(CORE_PIN39_BIT))
+#define CORE_PIN40_BITMASK	(1<<(CORE_PIN40_BIT))
+#define CORE_PIN41_BITMASK	(1<<(CORE_PIN41_BIT))
+#define CORE_PIN42_BITMASK	(1<<(CORE_PIN42_BIT))
+#define CORE_PIN43_BITMASK	(1<<(CORE_PIN43_BIT))
+#define CORE_PIN44_BITMASK	(1<<(CORE_PIN44_BIT))
+#define CORE_PIN45_BITMASK	(1<<(CORE_PIN45_BIT))
+#define CORE_PIN46_BITMASK	(1<<(CORE_PIN46_BIT))
+#define CORE_PIN47_BITMASK	(1<<(CORE_PIN47_BIT))
+#define CORE_PIN48_BITMASK	(1<<(CORE_PIN48_BIT))
+#define CORE_PIN49_BITMASK	(1<<(CORE_PIN49_BIT))
+#define CORE_PIN50_BITMASK	(1<<(CORE_PIN50_BIT))
+#define CORE_PIN51_BITMASK	(1<<(CORE_PIN51_BIT))
+#define CORE_PIN52_BITMASK	(1<<(CORE_PIN52_BIT))
+#define CORE_PIN53_BITMASK	(1<<(CORE_PIN53_BIT))
+#define CORE_PIN54_BITMASK	(1<<(CORE_PIN54_BIT))
+#define CORE_PIN55_BITMASK	(1<<(CORE_PIN55_BIT))
+#define CORE_PIN56_BITMASK	(1<<(CORE_PIN56_BIT))
+#define CORE_PIN57_BITMASK	(1<<(CORE_PIN57_BIT))
 
 #define CORE_PIN0_PORTREG	GPIOB_PDOR
 #define CORE_PIN1_PORTREG	GPIOB_PDOR
 #define CORE_PIN37_PORTREG	GPIOC_PDOR
 #define CORE_PIN38_PORTREG	GPIOC_PDOR
 #define CORE_PIN39_PORTREG	GPIOA_PDOR
+#define CORE_PIN40_PORTREG	GPIOA_PDOR
+#define CORE_PIN41_PORTREG	GPIOA_PDOR
+#define CORE_PIN42_PORTREG	GPIOA_PDOR
+#define CORE_PIN43_PORTREG	GPIOB_PDOR
+#define CORE_PIN44_PORTREG	GPIOB_PDOR
+#define CORE_PIN45_PORTREG	GPIOB_PDOR
+#define CORE_PIN46_PORTREG	GPIOB_PDOR
+#define CORE_PIN47_PORTREG	GPIOD_PDOR
+#define CORE_PIN48_PORTREG	GPIOD_PDOR
+#define CORE_PIN49_PORTREG	GPIOB_PDOR
+#define CORE_PIN50_PORTREG	GPIOB_PDOR
+#define CORE_PIN51_PORTREG	GPIOD_PDOR
+#define CORE_PIN52_PORTREG	GPIOD_PDOR
+#define CORE_PIN53_PORTREG	GPIOD_PDOR
+#define CORE_PIN54_PORTREG	GPIOD_PDOR
+#define CORE_PIN55_PORTREG	GPIOD_PDOR
+#define CORE_PIN56_PORTREG	GPIOE_PDOR
+#define CORE_PIN57_PORTREG	GPIOE_PDOR
 
 #define CORE_PIN0_PORTSET	GPIOB_PSOR
 #define CORE_PIN1_PORTSET	GPIOB_PSOR
 #define CORE_PIN37_PORTSET	GPIOC_PSOR
 #define CORE_PIN38_PORTSET	GPIOC_PSOR
 #define CORE_PIN39_PORTSET	GPIOA_PSOR
+#define CORE_PIN40_PORTSET	GPIOA_PSOR
+#define CORE_PIN41_PORTSET	GPIOA_PSOR
+#define CORE_PIN42_PORTSET	GPIOA_PSOR
+#define CORE_PIN43_PORTSET	GPIOB_PSOR
+#define CORE_PIN44_PORTSET	GPIOB_PSOR
+#define CORE_PIN45_PORTSET	GPIOB_PSOR
+#define CORE_PIN46_PORTSET	GPIOB_PSOR
+#define CORE_PIN47_PORTSET	GPIOD_PSOR
+#define CORE_PIN48_PORTSET	GPIOD_PSOR
+#define CORE_PIN49_PORTSET	GPIOB_PSOR
+#define CORE_PIN50_PORTSET	GPIOB_PSOR
+#define CORE_PIN51_PORTSET	GPIOD_PSOR
+#define CORE_PIN52_PORTSET	GPIOD_PSOR
+#define CORE_PIN53_PORTSET	GPIOD_PSOR
+#define CORE_PIN54_PORTSET	GPIOD_PSOR
+#define CORE_PIN55_PORTSET	GPIOD_PSOR
+#define CORE_PIN56_PORTSET	GPIOE_PSOR
+#define CORE_PIN57_PORTSET	GPIOE_PSOR
 
 #define CORE_PIN0_PORTCLEAR	GPIOB_PCOR
 #define CORE_PIN1_PORTCLEAR	GPIOB_PCOR
 #define CORE_PIN37_PORTCLEAR	GPIOC_PCOR
 #define CORE_PIN38_PORTCLEAR	GPIOC_PCOR
 #define CORE_PIN39_PORTCLEAR	GPIOA_PCOR
+#define CORE_PIN40_PORTCLEAR	GPIOA_PCOR
+#define CORE_PIN41_PORTCLEAR	GPIOA_PCOR
+#define CORE_PIN42_PORTCLEAR	GPIOA_PCOR
+#define CORE_PIN43_PORTCLEAR	GPIOB_PCOR
+#define CORE_PIN44_PORTCLEAR	GPIOB_PCOR
+#define CORE_PIN45_PORTCLEAR	GPIOB_PCOR
+#define CORE_PIN46_PORTCLEAR	GPIOB_PCOR
+#define CORE_PIN47_PORTCLEAR	GPIOD_PCOR
+#define CORE_PIN48_PORTCLEAR	GPIOD_PCOR
+#define CORE_PIN49_PORTCLEAR	GPIOB_PCOR
+#define CORE_PIN50_PORTCLEAR	GPIOB_PCOR
+#define CORE_PIN51_PORTCLEAR	GPIOD_PCOR
+#define CORE_PIN52_PORTCLEAR	GPIOD_PCOR
+#define CORE_PIN53_PORTCLEAR	GPIOD_PCOR
+#define CORE_PIN54_PORTCLEAR	GPIOD_PCOR
+#define CORE_PIN55_PORTCLEAR	GPIOD_PCOR
+#define CORE_PIN56_PORTCLEAR	GPIOE_PCOR
+#define CORE_PIN57_PORTCLEAR	GPIOE_PCOR
 
 #define CORE_PIN0_DDRREG	GPIOB_PDDR
 #define CORE_PIN1_DDRREG	GPIOB_PDDR
 #define CORE_PIN37_DDRREG	GPIOC_PDDR
 #define CORE_PIN38_DDRREG	GPIOC_PDDR
 #define CORE_PIN39_DDRREG	GPIOA_PDDR
+#define CORE_PIN40_DDRREG	GPIOA_PDDR
+#define CORE_PIN41_DDRREG	GPIOA_PDDR
+#define CORE_PIN42_DDRREG	GPIOA_PDDR
+#define CORE_PIN43_DDRREG	GPIOB_PDDR
+#define CORE_PIN44_DDRREG	GPIOB_PDDR
+#define CORE_PIN45_DDRREG	GPIOB_PDDR
+#define CORE_PIN46_DDRREG	GPIOB_PDDR
+#define CORE_PIN47_DDRREG	GPIOD_PDDR
+#define CORE_PIN48_DDRREG	GPIOD_PDDR
+#define CORE_PIN49_DDRREG	GPIOB_PDDR
+#define CORE_PIN50_DDRREG	GPIOB_PDDR
+#define CORE_PIN51_DDRREG	GPIOD_PDDR
+#define CORE_PIN52_DDRREG	GPIOD_PDDR
+#define CORE_PIN53_DDRREG	GPIOD_PDDR
+#define CORE_PIN54_DDRREG	GPIOD_PDDR
+#define CORE_PIN55_DDRREG	GPIOD_PDDR
+#define CORE_PIN56_DDRREG	GPIOE_PDDR
+#define CORE_PIN57_DDRREG	GPIOE_PDDR
 
 #define CORE_PIN0_PINREG	GPIOB_PDIR
 #define CORE_PIN1_PINREG	GPIOB_PDIR
 #define CORE_PIN37_PINREG	GPIOC_PDIR
 #define CORE_PIN38_PINREG	GPIOC_PDIR
 #define CORE_PIN39_PINREG	GPIOA_PDIR
+#define CORE_PIN40_PINREG	GPIOA_PDIR
+#define CORE_PIN41_PINREG	GPIOA_PDIR
+#define CORE_PIN42_PINREG	GPIOA_PDIR
+#define CORE_PIN43_PINREG	GPIOB_PDIR
+#define CORE_PIN44_PINREG	GPIOB_PDIR
+#define CORE_PIN45_PINREG	GPIOB_PDIR
+#define CORE_PIN46_PINREG	GPIOB_PDIR
+#define CORE_PIN47_PINREG	GPIOD_PDIR
+#define CORE_PIN48_PINREG	GPIOD_PDIR
+#define CORE_PIN49_PINREG	GPIOB_PDIR
+#define CORE_PIN50_PINREG	GPIOB_PDIR
+#define CORE_PIN51_PINREG	GPIOD_PDIR
+#define CORE_PIN52_PINREG	GPIOD_PDIR
+#define CORE_PIN53_PINREG	GPIOD_PDIR
+#define CORE_PIN54_PINREG	GPIOD_PDIR
+#define CORE_PIN55_PINREG	GPIOD_PDIR
+#define CORE_PIN56_PINREG	GPIOE_PDIR
+#define CORE_PIN57_PINREG	GPIOE_PDIR
 
 #define CORE_PIN0_CONFIG	PORTB_PCR16
 #define CORE_PIN1_CONFIG	PORTB_PCR17
 #define CORE_PIN37_CONFIG	PORTC_PCR10
 #define CORE_PIN38_CONFIG	PORTC_PCR11
 #define CORE_PIN39_CONFIG	PORTA_PCR17
+#define CORE_PIN40_CONFIG	PORTA_PCR28
+#define CORE_PIN41_CONFIG	PORTA_PCR29
+#define CORE_PIN42_CONFIG	PORTA_PCR26
+#define CORE_PIN43_CONFIG	PORTB_PCR20
+#define CORE_PIN44_CONFIG	PORTB_PCR22
+#define CORE_PIN45_CONFIG	PORTB_PCR23
+#define CORE_PIN46_CONFIG	PORTB_PCR21
+#define CORE_PIN47_CONFIG	PORTD_PCR8
+#define CORE_PIN48_CONFIG	PORTD_PCR9
+#define CORE_PIN49_CONFIG	PORTB_PCR4
+#define CORE_PIN50_CONFIG	PORTB_PCR5
+#define CORE_PIN51_CONFIG	PORTD_PCR14
+#define CORE_PIN52_CONFIG	PORTD_PCR13
+#define CORE_PIN53_CONFIG	PORTD_PCR12
+#define CORE_PIN54_CONFIG	PORTD_PCR15
+#define CORE_PIN55_CONFIG	PORTD_PCR11
+#define CORE_PIN56_CONFIG	PORTE_PCR10
+#define CORE_PIN57_CONFIG	PORTE_PCR11
 
 #define CORE_ADC0_PIN		14
 #define CORE_ADC1_PIN		15
 #define CORE_INT37_PIN		37
 #define CORE_INT38_PIN		38
 #define CORE_INT39_PIN		39
+#define CORE_INT40_PIN		40
+#define CORE_INT41_PIN		41
+#define CORE_INT42_PIN		42
+#define CORE_INT43_PIN		43
+#define CORE_INT44_PIN		44
+#define CORE_INT45_PIN		45
+#define CORE_INT46_PIN		46
+#define CORE_INT47_PIN		47
+#define CORE_INT48_PIN		48
+#define CORE_INT49_PIN		49
+#define CORE_INT50_PIN		50
+#define CORE_INT51_PIN		51
+#define CORE_INT52_PIN		52
+#define CORE_INT53_PIN		53
+#define CORE_INT54_PIN		54
+#define CORE_INT55_PIN		55
+#define CORE_INT56_PIN		56
+#define CORE_INT57_PIN		57
 #define CORE_INT_EVERY_PIN	1
 
 #endif
 				CORE_PIN38_PORTSET = CORE_PIN38_BITMASK;
 			} else if (pin == 39) {
 				CORE_PIN39_PORTSET = CORE_PIN39_BITMASK;
+			} else if (pin == 40) {
+				CORE_PIN40_PORTSET = CORE_PIN40_BITMASK;
+			} else if (pin == 41) {
+				CORE_PIN41_PORTSET = CORE_PIN41_BITMASK;
+			} else if (pin == 42) {
+				CORE_PIN42_PORTSET = CORE_PIN42_BITMASK;
+			} else if (pin == 43) {
+				CORE_PIN43_PORTSET = CORE_PIN43_BITMASK;
+			} else if (pin == 44) {
+				CORE_PIN44_PORTSET = CORE_PIN44_BITMASK;
+			} else if (pin == 45) {
+				CORE_PIN45_PORTSET = CORE_PIN45_BITMASK;
+			} else if (pin == 46) {
+				CORE_PIN46_PORTSET = CORE_PIN46_BITMASK;
+			} else if (pin == 47) {
+				CORE_PIN47_PORTSET = CORE_PIN47_BITMASK;
+			} else if (pin == 48) {
+				CORE_PIN48_PORTSET = CORE_PIN48_BITMASK;
+			} else if (pin == 49) {
+				CORE_PIN49_PORTSET = CORE_PIN49_BITMASK;
+			} else if (pin == 50) {
+				CORE_PIN50_PORTSET = CORE_PIN50_BITMASK;
+			} else if (pin == 51) {
+				CORE_PIN51_PORTSET = CORE_PIN51_BITMASK;
+			} else if (pin == 52) {
+				CORE_PIN52_PORTSET = CORE_PIN52_BITMASK;
+			} else if (pin == 53) {
+				CORE_PIN53_PORTSET = CORE_PIN53_BITMASK;
+			} else if (pin == 54) {
+				CORE_PIN54_PORTSET = CORE_PIN54_BITMASK;
+			} else if (pin == 55) {
+				CORE_PIN55_PORTSET = CORE_PIN55_BITMASK;
+			} else if (pin == 56) {
+				CORE_PIN56_PORTSET = CORE_PIN56_BITMASK;
+			} else if (pin == 57) {
+				CORE_PIN57_PORTSET = CORE_PIN57_BITMASK;
 			}
 			#endif
 		} else {
 				CORE_PIN38_PORTCLEAR = CORE_PIN38_BITMASK;
 			} else if (pin == 39) {
 				CORE_PIN39_PORTCLEAR = CORE_PIN39_BITMASK;
+			} else if (pin == 40) {
+				CORE_PIN40_PORTCLEAR = CORE_PIN40_BITMASK;
+			} else if (pin == 41) {
+				CORE_PIN41_PORTCLEAR = CORE_PIN41_BITMASK;
+			} else if (pin == 42) {
+				CORE_PIN42_PORTCLEAR = CORE_PIN42_BITMASK;
+			} else if (pin == 43) {
+				CORE_PIN43_PORTCLEAR = CORE_PIN43_BITMASK;
+			} else if (pin == 44) {
+				CORE_PIN44_PORTCLEAR = CORE_PIN44_BITMASK;
+			} else if (pin == 45) {
+				CORE_PIN45_PORTCLEAR = CORE_PIN45_BITMASK;
+			} else if (pin == 46) {
+				CORE_PIN46_PORTCLEAR = CORE_PIN46_BITMASK;
+			} else if (pin == 47) {
+				CORE_PIN47_PORTCLEAR = CORE_PIN47_BITMASK;
+			} else if (pin == 48) {
+				CORE_PIN48_PORTCLEAR = CORE_PIN48_BITMASK;
+			} else if (pin == 49) {
+				CORE_PIN49_PORTCLEAR = CORE_PIN49_BITMASK;
+			} else if (pin == 50) {
+				CORE_PIN50_PORTCLEAR = CORE_PIN50_BITMASK;
+			} else if (pin == 51) {
+				CORE_PIN51_PORTCLEAR = CORE_PIN51_BITMASK;
+			} else if (pin == 52) {
+				CORE_PIN52_PORTCLEAR = CORE_PIN52_BITMASK;
+			} else if (pin == 53) {
+				CORE_PIN53_PORTCLEAR = CORE_PIN53_BITMASK;
+			} else if (pin == 54) {
+				CORE_PIN54_PORTCLEAR = CORE_PIN54_BITMASK;
+			} else if (pin == 55) {
+				CORE_PIN55_PORTCLEAR = CORE_PIN55_BITMASK;
+			} else if (pin == 56) {
+				CORE_PIN56_PORTCLEAR = CORE_PIN56_BITMASK;
+			} else if (pin == 57) {
+				CORE_PIN57_PORTCLEAR = CORE_PIN57_BITMASK;
 			}
 			#endif
 		}
 			return (CORE_PIN38_PINREG & CORE_PIN38_BITMASK) ? 1 : 0;
 		} else if (pin == 39) {
 			return (CORE_PIN39_PINREG & CORE_PIN39_BITMASK) ? 1 : 0;
+		} else if (pin == 40) {
+			return (CORE_PIN40_PINREG & CORE_PIN40_BITMASK) ? 1 : 0;
+		} else if (pin == 41) {
+			return (CORE_PIN41_PINREG & CORE_PIN41_BITMASK) ? 1 : 0;
+		} else if (pin == 42) {
+			return (CORE_PIN42_PINREG & CORE_PIN42_BITMASK) ? 1 : 0;
+		} else if (pin == 43) {
+			return (CORE_PIN43_PINREG & CORE_PIN43_BITMASK) ? 1 : 0;
+		} else if (pin == 44) {
+			return (CORE_PIN44_PINREG & CORE_PIN44_BITMASK) ? 1 : 0;
+		} else if (pin == 45) {
+			return (CORE_PIN45_PINREG & CORE_PIN45_BITMASK) ? 1 : 0;
+		} else if (pin == 46) {
+			return (CORE_PIN46_PINREG & CORE_PIN46_BITMASK) ? 1 : 0;
+		} else if (pin == 47) {
+			return (CORE_PIN47_PINREG & CORE_PIN47_BITMASK) ? 1 : 0;
+		} else if (pin == 48) {
+			return (CORE_PIN48_PINREG & CORE_PIN48_BITMASK) ? 1 : 0;
+		} else if (pin == 49) {
+			return (CORE_PIN49_PINREG & CORE_PIN49_BITMASK) ? 1 : 0;
+		} else if (pin == 50) {
+			return (CORE_PIN50_PINREG & CORE_PIN50_BITMASK) ? 1 : 0;
+		} else if (pin == 51) {
+			return (CORE_PIN51_PINREG & CORE_PIN51_BITMASK) ? 1 : 0;
+		} else if (pin == 52) {
+			return (CORE_PIN52_PINREG & CORE_PIN52_BITMASK) ? 1 : 0;
+		} else if (pin == 53) {
+			return (CORE_PIN53_PINREG & CORE_PIN53_BITMASK) ? 1 : 0;
+		} else if (pin == 54) {
+			return (CORE_PIN54_PINREG & CORE_PIN54_BITMASK) ? 1 : 0;
+		} else if (pin == 55) {
+			return (CORE_PIN55_PINREG & CORE_PIN55_BITMASK) ? 1 : 0;
+		} else if (pin == 56) {
+			return (CORE_PIN56_PINREG & CORE_PIN56_BITMASK) ? 1 : 0;
+		} else if (pin == 57) {
+			return (CORE_PIN57_PINREG & CORE_PIN57_BITMASK) ? 1 : 0;
 		}
 		#endif
 		  else {

teensy3/pins_teensy.c

 	{GPIO_BITBAND_PTR(CORE_PIN37_PORTREG, CORE_PIN37_BIT), &CORE_PIN37_CONFIG},
 	{GPIO_BITBAND_PTR(CORE_PIN38_PORTREG, CORE_PIN38_BIT), &CORE_PIN38_CONFIG},
 	{GPIO_BITBAND_PTR(CORE_PIN39_PORTREG, CORE_PIN39_BIT), &CORE_PIN39_CONFIG},
+	{GPIO_BITBAND_PTR(CORE_PIN40_PORTREG, CORE_PIN40_BIT), &CORE_PIN40_CONFIG},
+	{GPIO_BITBAND_PTR(CORE_PIN41_PORTREG, CORE_PIN41_BIT), &CORE_PIN41_CONFIG},
+	{GPIO_BITBAND_PTR(CORE_PIN42_PORTREG, CORE_PIN42_BIT), &CORE_PIN42_CONFIG},
+	{GPIO_BITBAND_PTR(CORE_PIN43_PORTREG, CORE_PIN43_BIT), &CORE_PIN43_CONFIG},
+	{GPIO_BITBAND_PTR(CORE_PIN44_PORTREG, CORE_PIN44_BIT), &CORE_PIN44_CONFIG},
+	{GPIO_BITBAND_PTR(CORE_PIN45_PORTREG, CORE_PIN45_BIT), &CORE_PIN45_CONFIG},
+	{GPIO_BITBAND_PTR(CORE_PIN46_PORTREG, CORE_PIN46_BIT), &CORE_PIN46_CONFIG},
+	{GPIO_BITBAND_PTR(CORE_PIN47_PORTREG, CORE_PIN47_BIT), &CORE_PIN47_CONFIG},
+	{GPIO_BITBAND_PTR(CORE_PIN48_PORTREG, CORE_PIN48_BIT), &CORE_PIN48_CONFIG},
+	{GPIO_BITBAND_PTR(CORE_PIN49_PORTREG, CORE_PIN49_BIT), &CORE_PIN49_CONFIG},
+	{GPIO_BITBAND_PTR(CORE_PIN50_PORTREG, CORE_PIN50_BIT), &CORE_PIN50_CONFIG},
+	{GPIO_BITBAND_PTR(CORE_PIN51_PORTREG, CORE_PIN51_BIT), &CORE_PIN51_CONFIG},
+	{GPIO_BITBAND_PTR(CORE_PIN52_PORTREG, CORE_PIN52_BIT), &CORE_PIN52_CONFIG},
+	{GPIO_BITBAND_PTR(CORE_PIN53_PORTREG, CORE_PIN53_BIT), &CORE_PIN53_CONFIG},
+	{GPIO_BITBAND_PTR(CORE_PIN54_PORTREG, CORE_PIN54_BIT), &CORE_PIN54_CONFIG},
+	{GPIO_BITBAND_PTR(CORE_PIN55_PORTREG, CORE_PIN55_BIT), &CORE_PIN55_CONFIG},
+	{GPIO_BITBAND_PTR(CORE_PIN56_PORTREG, CORE_PIN56_BIT), &CORE_PIN56_CONFIG},
+	{GPIO_BITBAND_PTR(CORE_PIN57_PORTREG, CORE_PIN57_BIT), &CORE_PIN57_CONFIG},
 #endif
 };
 
 	if ((isfr & CORE_PIN27_BITMASK) && intFunc[27]) intFunc[27]();
 	if ((isfr & CORE_PIN28_BITMASK) && intFunc[28]) intFunc[28]();
 	if ((isfr & CORE_PIN39_BITMASK) && intFunc[39]) intFunc[39]();
+	if ((isfr & CORE_PIN40_BITMASK) && intFunc[40]) intFunc[40]();
+	if ((isfr & CORE_PIN41_BITMASK) && intFunc[41]) intFunc[41]();
+	if ((isfr & CORE_PIN42_BITMASK) && intFunc[42]) intFunc[42]();
 }
 
 static void portb_interrupt(void)
 	if ((isfr & CORE_PIN30_BITMASK) && intFunc[30]) intFunc[30]();
 	if ((isfr & CORE_PIN31_BITMASK) && intFunc[31]) intFunc[31]();
 	if ((isfr & CORE_PIN32_BITMASK) && intFunc[32]) intFunc[32]();
+	if ((isfr & CORE_PIN43_BITMASK) && intFunc[43]) intFunc[43]();
+	if ((isfr & CORE_PIN44_BITMASK) && intFunc[44]) intFunc[44]();
+	if ((isfr & CORE_PIN45_BITMASK) && intFunc[45]) intFunc[45]();
+	if ((isfr & CORE_PIN46_BITMASK) && intFunc[46]) intFunc[46]();
+	if ((isfr & CORE_PIN49_BITMASK) && intFunc[49]) intFunc[49]();
+	if ((isfr & CORE_PIN50_BITMASK) && intFunc[50]) intFunc[50]();
 }
 
 static void portc_interrupt(void)
 	if ((isfr & CORE_PIN14_BITMASK) && intFunc[14]) intFunc[14]();
 	if ((isfr & CORE_PIN20_BITMASK) && intFunc[20]) intFunc[20]();
 	if ((isfr & CORE_PIN21_BITMASK) && intFunc[21]) intFunc[21]();
+	if ((isfr & CORE_PIN47_BITMASK) && intFunc[47]) intFunc[47]();
+	if ((isfr & CORE_PIN48_BITMASK) && intFunc[48]) intFunc[48]();
+	if ((isfr & CORE_PIN51_BITMASK) && intFunc[51]) intFunc[51]();
+	if ((isfr & CORE_PIN52_BITMASK) && intFunc[52]) intFunc[52]();
+	if ((isfr & CORE_PIN53_BITMASK) && intFunc[53]) intFunc[53]();
+	if ((isfr & CORE_PIN54_BITMASK) && intFunc[54]) intFunc[54]();
+	if ((isfr & CORE_PIN55_BITMASK) && intFunc[55]) intFunc[55]();
 }
 
 static void porte_interrupt(void)
 	if ((isfr & CORE_PIN24_BITMASK) && intFunc[24]) intFunc[24]();
 	if ((isfr & CORE_PIN33_BITMASK) && intFunc[33]) intFunc[33]();
 	if ((isfr & CORE_PIN34_BITMASK) && intFunc[34]) intFunc[34]();
+	if ((isfr & CORE_PIN56_BITMASK) && intFunc[56]) intFunc[56]();
+	if ((isfr & CORE_PIN57_BITMASK) && intFunc[57]) intFunc[57]();
 }
 
 #endif