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} |
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} |
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__attribute__((weak)) |
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__attribute__((weak)) |
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void HardFault_HandlerC(unsigned int *hardfault_args) { |
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void HardFault_HandlerC(unsigned int *hardfault_args) |
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{ |
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volatile unsigned int nn ; |
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#ifdef PRINT_DEBUG_STUFF |
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volatile unsigned int stacked_r0 ; |
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volatile unsigned int stacked_r0 ; |
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volatile unsigned int stacked_r1 ; |
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volatile unsigned int stacked_r1 ; |
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volatile unsigned int stacked_r2 ; |
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volatile unsigned int stacked_r2 ; |
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volatile unsigned int _BFAR ; |
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volatile unsigned int _BFAR ; |
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volatile unsigned int _MMAR ; |
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volatile unsigned int _MMAR ; |
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volatile unsigned int addr ; |
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volatile unsigned int addr ; |
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volatile unsigned int nn ; |
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stacked_r0 = ((unsigned int)hardfault_args[0]) ; |
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stacked_r0 = ((unsigned int)hardfault_args[0]) ; |
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stacked_r1 = ((unsigned int)hardfault_args[1]) ; |
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stacked_r1 = ((unsigned int)hardfault_args[1]) ; |
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printf(" _AFSR :: %x\n", _AFSR); |
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printf(" _AFSR :: %x\n", _AFSR); |
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printf(" _BFAR :: %x\n", _BFAR); |
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printf(" _BFAR :: %x\n", _BFAR); |
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printf(" _MMAR :: %x\n", _MMAR); |
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printf(" _MMAR :: %x\n", _MMAR); |
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#endif |
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IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 5; // pin 13 |
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IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 5; // pin 13 |
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IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = IOMUXC_PAD_DSE(7); |
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IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = IOMUXC_PAD_DSE(7); |