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@@ -0,0 +1,111 @@ |
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#include "avr_emulation.h" |
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#if F_BUS == 48000000 |
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#define SPI_CLOCK_24MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(48 / 2) * ((1+1)/2) |
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#define SPI_CLOCK_16MHz (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(48 / 3) * ((1+1)/2) 33% duty cycle |
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#define SPI_CLOCK_12MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0)) //(48 / 2) * ((1+0)/2) |
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#define SPI_CLOCK_8MHz (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0)) //(48 / 3) * ((1+0)/2) |
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#define SPI_CLOCK_6MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1)) //(48 / 2) * ((1+0)/4) |
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#define SPI_CLOCK_4MHz (SPI_CTAR_PBR(1) | SPI_CTAR_BR(1)) //(48 / 3) * ((1+0)/4) |
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#elif F_BUS == 24000000 |
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#define SPI_CLOCK_24MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(24 / 2) * ((1+1)/2) 12 MHz |
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#define SPI_CLOCK_16MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(24 / 2) * ((1+1)/2) 12 MHz |
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#define SPI_CLOCK_12MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(24 / 2) * ((1+1)/2) |
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#define SPI_CLOCK_8MHz (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(24 / 3) * ((1+1)/2) 33% duty cycle |
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#define SPI_CLOCK_6MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0)) //(24 / 2) * ((1+0)/2) |
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#define SPI_CLOCK_4MHz (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0)) //(24 / 3) * ((1+0)/2) |
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#endif |
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// sck = F_BUS / PBR * ((1+DBR)/BR) |
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// PBR = 2, 3, 5, 7 |
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// DBR = 0, 1 -- zero preferred |
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// BR = 2, 4, 6, 8, 16, 32, 64, 128, 256, 512 |
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#ifndef SPI_MODE0 |
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#define SPI_MODE0 0x00 // CPOL = 0, CPHA = 0 |
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#define SPI_MODE1 0x04 // CPOL = 0, CPHA = 1 |
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#define SPI_MODE2 0x08 // CPOL = 1, CPHA = 0 |
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#define SPI_MODE3 0x0C // CPOL = 1, CPHA = 1 |
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#endif |
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#define SPI_CONTINUE 1 |
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static uint8_t pcs=0; |
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class SPIFIFOclass |
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{ |
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public: |
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inline bool begin(uint8_t pin, uint32_t speed, uint32_t mode=SPI_MODE0) __attribute__((always_inline)) { |
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uint32_t p, ctar = speed; |
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SIM_SCGC6 |= SIM_SCGC6_SPI0; |
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SPI0_MCR = SPI_MCR_MSTR | SPI_MCR_MDIS | SPI_MCR_HALT | SPI_MCR_PCSIS(0x1F); |
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if (mode & 0x08) ctar |= SPI_CTAR_CPOL; |
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if (mode & 0x04) { |
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ctar |= SPI_CTAR_CPHA; |
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ctar |= (ctar & 0x0F) << 8; |
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} else { |
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ctar |= (ctar & 0x0F) << 12; |
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} |
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SPI0_CTAR0 = ctar | SPI_CTAR_FMSZ(7); |
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SPI0_CTAR1 = ctar | SPI_CTAR_FMSZ(15); |
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if (pin == 10) { // PTC4 |
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CORE_PIN10_CONFIG = PORT_PCR_MUX(2); |
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p = 0x01; |
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} else if (pin == 2) { // PTD0 |
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CORE_PIN2_CONFIG = PORT_PCR_MUX(2); |
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p = 0x01; |
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} else if (pin == 9) { // PTC3 |
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CORE_PIN9_CONFIG = PORT_PCR_MUX(2); |
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p = 0x02; |
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} else if (pin == 6) { // PTD4 |
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CORE_PIN6_CONFIG = PORT_PCR_MUX(2); |
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p = 0x02; |
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} else if (pin == 20) { // PTD5 |
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CORE_PIN20_CONFIG = PORT_PCR_MUX(2); |
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p = 0x04; |
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} else if (pin == 23) { // PTC2 |
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CORE_PIN23_CONFIG = PORT_PCR_MUX(2); |
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p = 0x04; |
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} else if (pin == 21) { // PTD6 |
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CORE_PIN21_CONFIG = PORT_PCR_MUX(2); |
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p = 0x08; |
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} else if (pin == 22) { // PTC1 |
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CORE_PIN22_CONFIG = PORT_PCR_MUX(2); |
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p = 0x08; |
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} else if (pin == 15) { // PTC0 |
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CORE_PIN15_CONFIG = PORT_PCR_MUX(2); |
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p = 0x10; |
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} else { |
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return false; |
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} |
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pcs = p; |
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clear(); |
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SPCR.enable_pins(); |
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return true; |
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} |
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inline void write(uint32_t b, uint32_t cont=0) __attribute__((always_inline)) { |
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while (((SPI0_SR) & (15 << 12)) > (3 << 12)) ; // wait for space in the TX fifo |
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SPI0_PUSHR = (b & 0xFF) | (pcs << 16) | (cont ? SPI_PUSHR_CONT : 0); |
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} |
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inline void write16(uint32_t b, uint32_t cont=0) __attribute__((always_inline)) { |
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while (((SPI0_SR) & (15 << 12)) > (3 << 12)) ; // wait for space in the TX fifo |
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SPI0_PUSHR = (b & 0xFFFF) | (pcs << 16) | (cont ? SPI_PUSHR_CONT : 0) | SPI_PUSHR_CTAS(1); |
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} |
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inline uint32_t read(void) __attribute__((always_inline)) { |
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while ((SPI0_SR & (15 << 4)) == 0) ; // TODO, could wait forever |
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return SPI0_POPR; |
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} |
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inline void clear(void) __attribute__((always_inline)) { |
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SPI0_MCR = SPI_MCR_MSTR | SPI_MCR_PCSIS(0x1F) | SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF; |
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} |
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}; |
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extern SPIFIFOclass SPIFIFO; |
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