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@@ -934,9 +934,11 @@ public: |
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} |
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// Use another DMA channel as the trigger, causing this |
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// channel to trigger after each transfer is makes, except |
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// channel to trigger after each transfer is makes, including |
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// the its last transfer. This effectively makes the 2 |
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// channels run in parallel until the last transfer |
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// channels run in parallel. Note, on Teensy 3.0 & 3.1, |
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// this feature triggers on every transfer except the last. |
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// On Teensy-LC, it triggers on every one, including the last. |
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void triggerAtTransfersOf(DMABaseClass &ch) { |
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uint32_t dcr = ch.CFG->DCR; |
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uint32_t linkcc = (dcr >> 4) & 3; |