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* permit persons to whom the Software is furnished to do so, subject to |
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* permit persons to whom the Software is furnished to do so, subject to |
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* the following conditions: |
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* the following conditions: |
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* |
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* |
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* 1. The above copyright notice and this permission notice shall be |
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* 1. The above copyright notice and this permission notice shall be |
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* included in all copies or substantial portions of the Software. |
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* included in all copies or substantial portions of the Software. |
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* |
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* |
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* 2. If the Software is incorporated into a build system that allows |
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* 2. If the Software is incorporated into a build system that allows |
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* selection among a list of target devices, then similar target |
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* selection among a list of target devices, then similar target |
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* devices manufactured by PJRC.COM must be included in the list of |
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* devices manufactured by PJRC.COM must be included in the list of |
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* target devices and selectable in the same manner. |
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* target devices and selectable in the same manner. |
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if ((SIM_SCGC4 & SIM_SCGC4_UART2)) { |
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if ((SIM_SCGC4 & SIM_SCGC4_UART2)) { |
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switch (tx_pin_num & 127) { |
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switch (tx_pin_num & 127) { |
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case 10: CORE_PIN10_CONFIG = 0; break; // PTC4 |
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case 10: CORE_PIN10_CONFIG = 0; break; // PTC4 |
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#if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.4 or T3.5 |
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case 31: CORE_PIN31_CONFIG = 0; break; // PTE0 |
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case 31: CORE_PIN31_CONFIG = 0; break; // PTE0 |
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#endif |
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} |
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} |
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if (opendrain) { |
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if (opendrain) { |
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cfg = PORT_PCR_DSE | PORT_PCR_ODE; |
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cfg = PORT_PCR_DSE | PORT_PCR_ODE; |
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} |
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} |
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switch (pin & 127) { |
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switch (pin & 127) { |
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case 10: CORE_PIN10_CONFIG = cfg | PORT_PCR_MUX(3); break; |
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case 10: CORE_PIN10_CONFIG = cfg | PORT_PCR_MUX(3); break; |
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#if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.4 or T3.5 |
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case 31: CORE_PIN31_CONFIG = cfg | PORT_PCR_MUX(3); break; |
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case 31: CORE_PIN31_CONFIG = cfg | PORT_PCR_MUX(3); break; |
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#endif |
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} |
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} |
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} |
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} |
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tx_pin_num = pin; |
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tx_pin_num = pin; |
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if ((SIM_SCGC4 & SIM_SCGC4_UART2)) { |
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if ((SIM_SCGC4 & SIM_SCGC4_UART2)) { |
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switch (rx_pin_num) { |
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switch (rx_pin_num) { |
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case 9: CORE_PIN9_CONFIG = 0; break; // PTC3 |
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case 9: CORE_PIN9_CONFIG = 0; break; // PTC3 |
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#if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.4 or T3.5 |
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case 26: CORE_PIN26_CONFIG = 0; break; // PTE1 |
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case 26: CORE_PIN26_CONFIG = 0; break; // PTE1 |
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#endif |
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} |
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} |
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switch (pin) { |
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switch (pin) { |
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case 9: CORE_PIN9_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break; |
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case 9: CORE_PIN9_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break; |
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#if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.4 or T3.5 |
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case 26: CORE_PIN26_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break; |
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case 26: CORE_PIN26_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break; |
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#endif |
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} |
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} |
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} |
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} |
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rx_pin_num = pin; |
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rx_pin_num = pin; |
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if (rts_pin) rts_assert(); |
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if (rts_pin) rts_assert(); |
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} |
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} |
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// status interrupt combines |
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// status interrupt combines |
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// Transmit data below watermark UART_S1_TDRE |
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// Transmit data below watermark UART_S1_TDRE |
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// Transmit complete UART_S1_TC |
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// Transmit complete UART_S1_TC |
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// Idle line UART_S1_IDLE |
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// Idle line UART_S1_IDLE |
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if (head >= RX_BUFFER_SIZE) head = 0; |
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if (head >= RX_BUFFER_SIZE) head = 0; |
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if (head != rx_buffer_tail) { |
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if (head != rx_buffer_tail) { |
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rx_buffer[head] = n; |
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rx_buffer[head] = n; |
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rx_buffer_head = head; |
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rx_buffer_head = head; |
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} |
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} |
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} |
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} |
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c = UART1_C2; |
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c = UART1_C2; |