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Serial2 - !TX(31) !RX(26) on T3.5

Updated Serial2.
It had valid TX for T3.2 of 10 and 31, but 31 on T3.5 is RX4

Likewise RX for T3.2 of 9 and 26, but on T3.5 26 is RX1
main
Kurt Eckhardt 8 years ago
parent
commit
c9bec4c380
1 changed files with 12 additions and 4 deletions
  1. +12
    -4
      teensy3/serial2.c

+ 12
- 4
teensy3/serial2.c View File

* permit persons to whom the Software is furnished to do so, subject to * permit persons to whom the Software is furnished to do so, subject to
* the following conditions: * the following conditions:
* *
* 1. The above copyright notice and this permission notice shall be
* 1. The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software. * included in all copies or substantial portions of the Software.
* *
* 2. If the Software is incorporated into a build system that allows
* 2. If the Software is incorporated into a build system that allows
* selection among a list of target devices, then similar target * selection among a list of target devices, then similar target
* devices manufactured by PJRC.COM must be included in the list of * devices manufactured by PJRC.COM must be included in the list of
* target devices and selectable in the same manner. * target devices and selectable in the same manner.
if ((SIM_SCGC4 & SIM_SCGC4_UART2)) { if ((SIM_SCGC4 & SIM_SCGC4_UART2)) {
switch (tx_pin_num & 127) { switch (tx_pin_num & 127) {
case 10: CORE_PIN10_CONFIG = 0; break; // PTC4 case 10: CORE_PIN10_CONFIG = 0; break; // PTC4
#if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.4 or T3.5
case 31: CORE_PIN31_CONFIG = 0; break; // PTE0 case 31: CORE_PIN31_CONFIG = 0; break; // PTE0
#endif
} }
if (opendrain) { if (opendrain) {
cfg = PORT_PCR_DSE | PORT_PCR_ODE; cfg = PORT_PCR_DSE | PORT_PCR_ODE;
} }
switch (pin & 127) { switch (pin & 127) {
case 10: CORE_PIN10_CONFIG = cfg | PORT_PCR_MUX(3); break; case 10: CORE_PIN10_CONFIG = cfg | PORT_PCR_MUX(3); break;
#if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.4 or T3.5
case 31: CORE_PIN31_CONFIG = cfg | PORT_PCR_MUX(3); break; case 31: CORE_PIN31_CONFIG = cfg | PORT_PCR_MUX(3); break;
#endif
} }
} }
tx_pin_num = pin; tx_pin_num = pin;
if ((SIM_SCGC4 & SIM_SCGC4_UART2)) { if ((SIM_SCGC4 & SIM_SCGC4_UART2)) {
switch (rx_pin_num) { switch (rx_pin_num) {
case 9: CORE_PIN9_CONFIG = 0; break; // PTC3 case 9: CORE_PIN9_CONFIG = 0; break; // PTC3
#if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.4 or T3.5
case 26: CORE_PIN26_CONFIG = 0; break; // PTE1 case 26: CORE_PIN26_CONFIG = 0; break; // PTE1
#endif
} }
switch (pin) { switch (pin) {
case 9: CORE_PIN9_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break; case 9: CORE_PIN9_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
#if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.4 or T3.5
case 26: CORE_PIN26_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break; case 26: CORE_PIN26_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
#endif
} }
} }
rx_pin_num = pin; rx_pin_num = pin;
if (rts_pin) rts_assert(); if (rts_pin) rts_assert();
} }


// status interrupt combines
// status interrupt combines
// Transmit data below watermark UART_S1_TDRE // Transmit data below watermark UART_S1_TDRE
// Transmit complete UART_S1_TC // Transmit complete UART_S1_TC
// Idle line UART_S1_IDLE // Idle line UART_S1_IDLE
if (head >= RX_BUFFER_SIZE) head = 0; if (head >= RX_BUFFER_SIZE) head = 0;
if (head != rx_buffer_tail) { if (head != rx_buffer_tail) {
rx_buffer[head] = n; rx_buffer[head] = n;
rx_buffer_head = head;
rx_buffer_head = head;
} }
} }
c = UART1_C2; c = UART1_C2;

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