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Merge pull request #161 from KurtE/T35_USE_SDCARD_PINS 

T35 use sdcard pins
main
Paul Stoffregen 8 år sedan
förälder
77a27fecd8 eef956bb2d
incheckning
d267bc104f
5 ändrade filer med 293 tillägg och 2 borttagningar
Delad Vy Visa Diff Statistik
  1. +76
    -0
      teensy3/avr_emulation.h
  2. +126
    -0
      teensy3/core_pins.h
  3. +16
    -0
      teensy3/pins_teensy.c
  4. +28
    -0
      teensy3/serial2.c
  5. +47
    -2
      teensy3/serial4.c

+ 76
- 0
teensy3/avr_emulation.h Visa fil

@@ -1261,19 +1261,74 @@ public:
return ret;
}
inline void setMOSI(uint8_t pin) __attribute__((always_inline)) {
#ifdef USE_SDCARD_PINS
// More options, so 2 bits
pinout &= ~3;
switch (pin) {
case 0: break;
case 21: pinout |= 1; break;
case 61: pinout |= 2; break;
case 59: pinout |= 3; break;
}
#else
if (pin == 0) pinout &= ~1; // MOSI1 = 0 (PTB16)
if (pin == 21) pinout |= 1; // MOSI1 = 21 (PTD6)
#endif
}
inline void setMISO(uint8_t pin) __attribute__((always_inline)) {
#ifdef USE_SDCARD_PINS
// More options, so 2 bits
pinout &= ~0xc;
switch (pin) {
case 1: break;
case 5: pinout |= 0x4; break;
case 61: pinout |= 0x8; break;
case 59: pinout |= 0xc; break;
}
#else
if (pin == 1) pinout &= ~2; // MISO1 = 1 (PTB17)
if (pin == 5) pinout |= 2; // MISO1 = 5 (PTD7)
#endif
}
inline void setSCK(uint8_t pin) __attribute__((always_inline)) {
#ifdef USE_SDCARD_PINS
// More options, so 2 bits
pinout &= ~0x30;
switch (pin) {
case 20: break;
case 32: pinout |= 0x10; break;
case 60: pinout |= 0x20; break;
}
#else
if (pin == 20) pinout &= ~4; // SCK = 20 (PTD5)
if (pin == 32) pinout |= 4; // MISO1 = 32 (PTB11)
#endif
}
inline void enable_pins(void) __attribute__((always_inline)) {
//serial_print("enable_pins\n");
#ifdef USE_SDCARD_PINS
// MOSI (SOUT)
switch (pinout & 0x3) {
case 0: CORE_PIN0_CONFIG = PORT_PCR_MUX(2); break;
case 1: CORE_PIN21_CONFIG = PORT_PCR_MUX(7); break;
case 2: CORE_PIN61_CONFIG = PORT_PCR_MUX(7); break;
case 3: CORE_PIN59_CONFIG = PORT_PCR_MUX(2); break;
}
// MISO (SIN)
switch (pinout & 0xc) {
case 0x0: CORE_PIN1_CONFIG = PORT_PCR_MUX(2); break;
case 0x4: CORE_PIN5_CONFIG = PORT_PCR_MUX(7); break;
case 0x8: CORE_PIN61_CONFIG = PORT_PCR_MUX(2); break;
case 0xc: CORE_PIN59_CONFIG = PORT_PCR_MUX(7); break;
}
// SCK
switch (pinout & 0x30) {
case 0x0: CORE_PIN20_CONFIG = PORT_PCR_MUX(7); break;
case 0x10: CORE_PIN32_CONFIG = PORT_PCR_MUX(2); break;
case 0x20: CORE_PIN60_CONFIG = PORT_PCR_MUX(2); break;
}

#else
if ((pinout & 1) == 0) {
CORE_PIN0_CONFIG = PORT_PCR_MUX(2); // MOSI1 = 0 (PTB16)
} else {
@@ -1289,8 +1344,28 @@ public:
} else {
CORE_PIN32_CONFIG = PORT_PCR_MUX(2); // MISO1 = 5 (PTD7)
}
#endif
}
inline void disable_pins(void) __attribute__((always_inline)) {
#ifdef USE_SDCARD_PINS
switch (pinout & 0x3) {
case 0: CORE_PIN0_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1); break;
case 1: CORE_PIN21_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1); break;
case 2: CORE_PIN61_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1); break;
case 3: CORE_PIN59_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1); break;
}
switch (pinout & 0xc) {
case 0x0: CORE_PIN1_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1); break;
case 0x4: CORE_PIN5_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1); break;
case 0x8: CORE_PIN61_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1); break;
case 0xc: CORE_PIN59_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1); break;
}
switch (pinout & 0x30) {
case 0x0: CORE_PIN20_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1); break;
case 0x10: CORE_PIN32_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1); break;
case 0x20: CORE_PIN60_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1); break;
}
#else
//serial_print("disable_pins\n");
if ((pinout & 1) == 0) {
CORE_PIN0_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1);
@@ -1307,6 +1382,7 @@ public:
} else {
CORE_PIN32_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1); // MISO1 = 5 (PTD7)
}
#endif
}
friend class SPIFIFO1class;
private:

+ 126
- 0
teensy3/core_pins.h Visa fil

@@ -34,6 +34,8 @@
#include "kinetis.h"
#include "pins_arduino.h"

// TESTING: Use the SDCARD pins on T3.5 beta for other purposes.
#define USE_SDCARD_PINS

#define HIGH 1
#define LOW 0
@@ -114,9 +116,15 @@
#define CORE_NUM_ANALOG 13
#define CORE_NUM_PWM 10
#elif defined(__MK64FX512__) || defined(__MK66FX1M0__)
#ifdef USE_SDCARD_PINS
#define CORE_NUM_TOTAL_PINS 64
#define CORE_NUM_DIGITAL 64
#define CORE_NUM_INTERRUPT 64
#else
#define CORE_NUM_TOTAL_PINS 58
#define CORE_NUM_DIGITAL 58
#define CORE_NUM_INTERRUPT 58
#endif
#define CORE_NUM_ANALOG 23
#define CORE_NUM_PWM 20
#endif
@@ -789,6 +797,14 @@
#define CORE_PIN55_BIT 11
#define CORE_PIN56_BIT 10
#define CORE_PIN57_BIT 11
#ifdef USE_SDCARD_PINS
#define CORE_PIN58_BIT 0
#define CORE_PIN59_BIT 1
#define CORE_PIN60_BIT 2
#define CORE_PIN61_BIT 3
#define CORE_PIN62_BIT 4
#define CORE_PIN63_BIT 5
#endif

#define CORE_PIN0_BITMASK (1<<(CORE_PIN0_BIT))
#define CORE_PIN1_BITMASK (1<<(CORE_PIN1_BIT))
@@ -848,6 +864,15 @@
#define CORE_PIN55_BITMASK (1<<(CORE_PIN55_BIT))
#define CORE_PIN56_BITMASK (1<<(CORE_PIN56_BIT))
#define CORE_PIN57_BITMASK (1<<(CORE_PIN57_BIT))
#ifdef USE_SDCARD_PINS
#define CORE_PIN58_BITMASK (1<<(CORE_PIN58_BIT))
#define CORE_PIN59_BITMASK (1<<(CORE_PIN59_BIT))
#define CORE_PIN60_BITMASK (1<<(CORE_PIN60_BIT))
#define CORE_PIN61_BITMASK (1<<(CORE_PIN61_BIT))
#define CORE_PIN62_BITMASK (1<<(CORE_PIN62_BIT))
#define CORE_PIN63_BITMASK (1<<(CORE_PIN63_BIT))
#endif


#define CORE_PIN0_PORTREG GPIOB_PDOR
#define CORE_PIN1_PORTREG GPIOB_PDOR
@@ -907,6 +932,14 @@
#define CORE_PIN55_PORTREG GPIOD_PDOR
#define CORE_PIN56_PORTREG GPIOE_PDOR
#define CORE_PIN57_PORTREG GPIOE_PDOR
#ifdef USE_SDCARD_PINS
#define CORE_PIN58_PORTREG GPIOE_PDOR
#define CORE_PIN59_PORTREG GPIOE_PDOR
#define CORE_PIN60_PORTREG GPIOE_PDOR
#define CORE_PIN61_PORTREG GPIOE_PDOR
#define CORE_PIN62_PORTREG GPIOE_PDOR
#define CORE_PIN63_PORTREG GPIOE_PDOR
#endif

#define CORE_PIN0_PORTSET GPIOB_PSOR
#define CORE_PIN1_PORTSET GPIOB_PSOR
@@ -966,6 +999,14 @@
#define CORE_PIN55_PORTSET GPIOD_PSOR
#define CORE_PIN56_PORTSET GPIOE_PSOR
#define CORE_PIN57_PORTSET GPIOE_PSOR
#ifdef USE_SDCARD_PINS
#define CORE_PIN58_PORTSET GPIOE_PSOR
#define CORE_PIN59_PORTSET GPIOE_PSOR
#define CORE_PIN60_PORTSET GPIOE_PSOR
#define CORE_PIN61_PORTSET GPIOE_PSOR
#define CORE_PIN62_PORTSET GPIOE_PSOR
#define CORE_PIN63_PORTSET GPIOE_PSOR
#endif

#define CORE_PIN0_PORTCLEAR GPIOB_PCOR
#define CORE_PIN1_PORTCLEAR GPIOB_PCOR
@@ -1025,6 +1066,14 @@
#define CORE_PIN55_PORTCLEAR GPIOD_PCOR
#define CORE_PIN56_PORTCLEAR GPIOE_PCOR
#define CORE_PIN57_PORTCLEAR GPIOE_PCOR
#ifdef USE_SDCARD_PINS
#define CORE_PIN58_PORTCLEAR GPIOE_PCOR
#define CORE_PIN59_PORTCLEAR GPIOE_PCOR
#define CORE_PIN60_PORTCLEAR GPIOE_PCOR
#define CORE_PIN61_PORTCLEAR GPIOE_PCOR
#define CORE_PIN62_PORTCLEAR GPIOE_PCOR
#define CORE_PIN63_PORTCLEAR GPIOE_PCOR
#endif

#define CORE_PIN0_DDRREG GPIOB_PDDR
#define CORE_PIN1_DDRREG GPIOB_PDDR
@@ -1084,6 +1133,14 @@
#define CORE_PIN55_DDRREG GPIOD_PDDR
#define CORE_PIN56_DDRREG GPIOE_PDDR
#define CORE_PIN57_DDRREG GPIOE_PDDR
#ifdef USE_SDCARD_PINS
#define CORE_PIN58_DDRREG GPIOE_PDDR
#define CORE_PIN59_DDRREG GPIOE_PDDR
#define CORE_PIN60_DDRREG GPIOE_PDDR
#define CORE_PIN61_DDRREG GPIOE_PDDR
#define CORE_PIN62_DDRREG GPIOE_PDDR
#define CORE_PIN63_DDRREG GPIOE_PDDR
#endif

#define CORE_PIN0_PINREG GPIOB_PDIR
#define CORE_PIN1_PINREG GPIOB_PDIR
@@ -1143,6 +1200,14 @@
#define CORE_PIN55_PINREG GPIOD_PDIR
#define CORE_PIN56_PINREG GPIOE_PDIR
#define CORE_PIN57_PINREG GPIOE_PDIR
#ifdef USE_SDCARD_PINS
#define CORE_PIN58_PINREG GPIOE_PDIR
#define CORE_PIN59_PINREG GPIOE_PDIR
#define CORE_PIN60_PINREG GPIOE_PDIR
#define CORE_PIN61_PINREG GPIOE_PDIR
#define CORE_PIN62_PINREG GPIOE_PDIR
#define CORE_PIN63_PINREG GPIOE_PDIR
#endif

#define CORE_PIN0_CONFIG PORTB_PCR16
#define CORE_PIN1_CONFIG PORTB_PCR17
@@ -1202,6 +1267,14 @@
#define CORE_PIN55_CONFIG PORTD_PCR11
#define CORE_PIN56_CONFIG PORTE_PCR10
#define CORE_PIN57_CONFIG PORTE_PCR11
#ifdef USE_SDCARD_PINS
#define CORE_PIN58_CONFIG PORTE_PCR0
#define CORE_PIN59_CONFIG PORTE_PCR1
#define CORE_PIN60_CONFIG PORTE_PCR2
#define CORE_PIN61_CONFIG PORTE_PCR3
#define CORE_PIN62_CONFIG PORTE_PCR4
#define CORE_PIN63_CONFIG PORTE_PCR5
#endif

#define CORE_ADC0_PIN 14
#define CORE_ADC1_PIN 15
@@ -1294,6 +1367,14 @@
#define CORE_INT55_PIN 55
#define CORE_INT56_PIN 56
#define CORE_INT57_PIN 57
#ifdef USE_SDCARD_PINS
#define CORE_INT58_PIN 58
#define CORE_INT59_PIN 59
#define CORE_INT60_PIN 60
#define CORE_INT61_PIN 61
#define CORE_INT62_PIN 62
#define CORE_INT63_PIN 63
#endif
#define CORE_INT_EVERY_PIN 1

#endif
@@ -1432,6 +1513,21 @@ static inline void digitalWriteFast(uint8_t pin, uint8_t val)
CORE_PIN56_PORTSET = CORE_PIN56_BITMASK;
} else if (pin == 57) {
CORE_PIN57_PORTSET = CORE_PIN57_BITMASK;
#ifdef USE_SDCARD_PINS
} else if (pin == 58) {
CORE_PIN58_PORTSET = CORE_PIN58_BITMASK;
} else if (pin == 59) {
CORE_PIN59_PORTSET = CORE_PIN59_BITMASK;
} else if (pin == 60) {
CORE_PIN60_PORTSET = CORE_PIN60_BITMASK;
} else if (pin == 61) {
CORE_PIN61_PORTSET = CORE_PIN61_BITMASK;
} else if (pin == 62) {
CORE_PIN62_PORTSET = CORE_PIN62_BITMASK;
} else if (pin == 63) {
CORE_PIN63_PORTSET = CORE_PIN63_BITMASK;

#endif
}
#endif
} else {
@@ -1556,6 +1652,21 @@ static inline void digitalWriteFast(uint8_t pin, uint8_t val)
CORE_PIN56_PORTCLEAR = CORE_PIN56_BITMASK;
} else if (pin == 57) {
CORE_PIN57_PORTCLEAR = CORE_PIN57_BITMASK;
#ifdef USE_SDCARD_PINS
} else if (pin == 58) {
CORE_PIN58_PORTCLEAR = CORE_PIN58_BITMASK;
} else if (pin == 59) {
CORE_PIN59_PORTCLEAR = CORE_PIN59_BITMASK;
} else if (pin == 60) {
CORE_PIN60_PORTCLEAR = CORE_PIN60_BITMASK;
} else if (pin == 61) {
CORE_PIN61_PORTCLEAR = CORE_PIN61_BITMASK;
} else if (pin == 62) {
CORE_PIN62_PORTCLEAR = CORE_PIN62_BITMASK;
} else if (pin == 63) {
CORE_PIN63_PORTCLEAR = CORE_PIN63_BITMASK;

#endif
}
#endif
}
@@ -1694,6 +1805,21 @@ static inline uint8_t digitalReadFast(uint8_t pin)
return (CORE_PIN56_PINREG & CORE_PIN56_BITMASK) ? 1 : 0;
} else if (pin == 57) {
return (CORE_PIN57_PINREG & CORE_PIN57_BITMASK) ? 1 : 0;
#ifdef USE_SDCARD_PINS
} else if (pin == 58) {
return (CORE_PIN58_PINREG & CORE_PIN58_BITMASK) ? 1 : 0;
} else if (pin == 59) {
return (CORE_PIN59_PINREG & CORE_PIN59_BITMASK) ? 1 : 0;
} else if (pin == 60) {
return (CORE_PIN60_PINREG & CORE_PIN60_BITMASK) ? 1 : 0;
} else if (pin == 61) {
return (CORE_PIN61_PINREG & CORE_PIN61_BITMASK) ? 1 : 0;
} else if (pin == 62) {
return (CORE_PIN62_PINREG & CORE_PIN62_BITMASK) ? 1 : 0;
} else if (pin == 63) {
return (CORE_PIN63_PINREG & CORE_PIN63_BITMASK) ? 1 : 0;

#endif
}
#endif
else {

+ 16
- 0
teensy3/pins_teensy.c Visa fil

@@ -98,6 +98,14 @@ const struct digital_pin_bitband_and_config_table_struct digital_pin_to_info_PGM
{GPIO_BITBAND_PTR(CORE_PIN55_PORTREG, CORE_PIN55_BIT), &CORE_PIN55_CONFIG},
{GPIO_BITBAND_PTR(CORE_PIN56_PORTREG, CORE_PIN56_BIT), &CORE_PIN56_CONFIG},
{GPIO_BITBAND_PTR(CORE_PIN57_PORTREG, CORE_PIN57_BIT), &CORE_PIN57_CONFIG},
#ifdef USE_SDCARD_PINS
{GPIO_BITBAND_PTR(CORE_PIN58_PORTREG, CORE_PIN58_BIT), &CORE_PIN58_CONFIG},
{GPIO_BITBAND_PTR(CORE_PIN59_PORTREG, CORE_PIN59_BIT), &CORE_PIN59_CONFIG},
{GPIO_BITBAND_PTR(CORE_PIN60_PORTREG, CORE_PIN60_BIT), &CORE_PIN60_CONFIG},
{GPIO_BITBAND_PTR(CORE_PIN61_PORTREG, CORE_PIN61_BIT), &CORE_PIN61_CONFIG},
{GPIO_BITBAND_PTR(CORE_PIN62_PORTREG, CORE_PIN62_BIT), &CORE_PIN62_CONFIG},
{GPIO_BITBAND_PTR(CORE_PIN63_PORTREG, CORE_PIN63_BIT), &CORE_PIN63_CONFIG},
#endif
#endif
};

@@ -391,6 +399,14 @@ static void porte_interrupt(void)
if ((isfr & CORE_PIN34_BITMASK) && intFunc[34]) intFunc[34]();
if ((isfr & CORE_PIN56_BITMASK) && intFunc[56]) intFunc[56]();
if ((isfr & CORE_PIN57_BITMASK) && intFunc[57]) intFunc[57]();
#ifdef USE_SDCARD_PINS
if ((isfr & CORE_PIN58_BITMASK) && intFunc[58]) intFunc[58]();
if ((isfr & CORE_PIN59_BITMASK) && intFunc[59]) intFunc[59]();
if ((isfr & CORE_PIN60_BITMASK) && intFunc[60]) intFunc[60]();
if ((isfr & CORE_PIN61_BITMASK) && intFunc[61]) intFunc[61]();
if ((isfr & CORE_PIN62_BITMASK) && intFunc[62]) intFunc[62]();
if ((isfr & CORE_PIN63_BITMASK) && intFunc[63]) intFunc[63]();
#endif
}

#endif

+ 28
- 0
teensy3/serial2.c Visa fil

@@ -117,10 +117,16 @@ void serial2_begin(uint32_t divisor)
switch (rx_pin_num) {
case 9: CORE_PIN9_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
case 26: CORE_PIN26_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__)) // on T3.5 or T3.6
case 59: CORE_PIN59_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
#endif
}
switch (tx_pin_num) {
case 10: CORE_PIN10_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
case 31: CORE_PIN31_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__)) // on T3.5 or T3.6
case 58: CORE_PIN58_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
#endif
}
#elif defined(KINETISL)
CORE_PIN9_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3);
@@ -192,12 +198,18 @@ void serial2_end(void)
#if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.5 or T3.6
case 26: CORE_PIN26_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); break; // PTE1
#endif
#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__)) // on T3.5 or T3.6
case 59: CORE_PIN59_CONFIG = 0; break;
#endif
}
switch (tx_pin_num & 127) {
case 10: CORE_PIN10_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); break; // PTC4
#if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.5 or T3.6
case 31: CORE_PIN31_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); break; // PTE0
#endif
#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__)) // on T3.5 or T3.6
case 58: CORE_PIN58_CONFIG = 0; break;
#endif
}
#elif defined(KINETISL)
CORE_PIN9_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); // PTC3
@@ -232,6 +244,9 @@ void serial2_set_tx(uint8_t pin, uint8_t opendrain)
#if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.5 or T3.6
case 31: CORE_PIN31_CONFIG = 0; break; // PTE0
#endif
#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__)) // on T3.5 or T3.6
case 58: CORE_PIN58_CONFIG = 0; break;
#endif
}
if (opendrain) {
cfg = PORT_PCR_DSE | PORT_PCR_ODE;
@@ -243,6 +258,9 @@ void serial2_set_tx(uint8_t pin, uint8_t opendrain)
#if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.5 or T3.6
case 31: CORE_PIN31_CONFIG = cfg | PORT_PCR_MUX(3); break;
#endif
#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__)) // on T3.5 or T3.6
case 58: CORE_PIN58_CONFIG = cfg | PORT_PCR_MUX(3); break;
#endif
}
}
tx_pin_num = pin;
@@ -259,12 +277,18 @@ void serial2_set_rx(uint8_t pin)
#if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.5 or T3.6
case 26: CORE_PIN26_CONFIG = 0; break; // PTE1
#endif
#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__)) // on T3.5 or T3.6
case 59: CORE_PIN59_CONFIG = 0; break;
#endif
}
switch (pin) {
case 9: CORE_PIN9_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
#if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.5 or T3.6
case 26: CORE_PIN26_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
#endif
#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__)) // on T3.5 or T3.6
case 59: CORE_PIN59_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
#endif
}
}
rx_pin_num = pin;
@@ -304,6 +328,10 @@ int serial2_set_cts(uint8_t pin)
if (!(SIM_SCGC4 & SIM_SCGC4_UART1)) return 0;
if (pin == 23) {
CORE_PIN23_CONFIG = PORT_PCR_MUX(3) | PORT_PCR_PE; // weak pulldown
#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__)) // on T3.5 or T3.6
} else if (pin == 60) {
CORE_PIN60_CONFIG = PORT_PCR_MUX(3) | PORT_PCR_PE; // weak pulldown
#endif
} else {
UART1_MODEM &= ~UART_MODEM_TXCTSE;
return 0;

+ 47
- 2
teensy3/serial4.c Visa fil

@@ -81,6 +81,7 @@ static volatile uint8_t rx_buffer_head = 0;
static volatile uint8_t rx_buffer_tail = 0;
#endif

static uint8_t rx_pin_num = 31;
static uint8_t tx_pin_num = 32;

// UART0 and UART1 are clocked by F_CPU, UART2 is clocked by F_BUS
@@ -99,8 +100,18 @@ void serial4_begin(uint32_t divisor)
tx_buffer_head = 0;
tx_buffer_tail = 0;
transmitting = 0;
CORE_PIN31_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3);
CORE_PIN32_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3);
switch (rx_pin_num) {
case 31: CORE_PIN31_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__)) // on T3.5 or T3.6
case 63: CORE_PIN63_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
#endif
}
switch (tx_pin_num) {
case 32: CORE_PIN32_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__)) // on T3.5 or T3.6
case 62: CORE_PIN62_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
#endif
}
UART3_BDH = (divisor >> 13) & 0x1F;
UART3_BDL = (divisor >> 5) & 0xFF;
UART3_C4 = divisor & 0x1F;
@@ -150,6 +161,18 @@ void serial4_end(void)
UART3_C2 = 0;
CORE_PIN31_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1);
CORE_PIN32_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1);
switch (rx_pin_num) {
case 31: CORE_PIN31_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); break; // PTC3
#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__)) // on T3.5 or T3.6
case 63: CORE_PIN63_CONFIG = 0; break;
#endif
}
switch (tx_pin_num & 127) {
case 32: CORE_PIN32_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); break; // PTC4
#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__)) // on T3.5 or T3.6
case 62: CORE_PIN62_CONFIG = 0; break;
#endif
}
rx_buffer_head = 0;
rx_buffer_tail = 0;
if (rts_pin) rts_deassert();
@@ -172,6 +195,9 @@ void serial4_set_tx(uint8_t pin, uint8_t opendrain)
if ((SIM_SCGC4 & SIM_SCGC4_UART3)) {
switch (tx_pin_num & 127) {
case 32: CORE_PIN32_CONFIG = 0; break; // PTB11
#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__)) // on T3.5 or T3.6
case 62: CORE_PIN62_CONFIG = 0; break;
#endif
}
if (opendrain) {
cfg = PORT_PCR_DSE | PORT_PCR_ODE;
@@ -180,6 +206,9 @@ void serial4_set_tx(uint8_t pin, uint8_t opendrain)
}
switch (pin & 127) {
case 32: CORE_PIN32_CONFIG = cfg | PORT_PCR_MUX(3); break;
#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__)) // on T3.5 or T3.6
case 62: CORE_PIN62_CONFIG = cfg | PORT_PCR_MUX(3);; break;
#endif
}
}
tx_pin_num = pin;
@@ -188,6 +217,22 @@ void serial4_set_tx(uint8_t pin, uint8_t opendrain)

void serial4_set_rx(uint8_t pin)
{
if (pin == rx_pin_num) return;
if ((SIM_SCGC4 & SIM_SCGC4_UART3)) {
switch (rx_pin_num) {
case 31: CORE_PIN31_CONFIG = 0; break; // PTC3
#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__)) // on T3.5 or T3.6
case 63: CORE_PIN63_CONFIG = 0; break;
#endif
}
switch (pin) {
case 31: CORE_PIN31_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__)) // on T3.5 or T3.6
case 63: CORE_PIN63_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
#endif
}
}
rx_pin_num = pin;
}

int serial4_set_rts(uint8_t pin)

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