Add more register defs & PLL config

teensy3/kinetis.h

@@ -363,6 +363,181 @@ enum IRQ_NUMBER_t {
 #define HAS_KINETIS_LLWU_16CH
 
 
+#elif defined(__MK64FX512__)
+enum IRQ_NUMBER_t {
+	IRQ_DMA_CH0 =		0,
+	IRQ_DMA_CH1 =		1,
+	IRQ_DMA_CH2 =		2,
+	IRQ_DMA_CH3 =		3,
+	IRQ_DMA_CH4 =		4,
+	IRQ_DMA_CH5 =		5,
+	IRQ_DMA_CH6 =		6,
+	IRQ_DMA_CH7 =		7,
+	IRQ_DMA_CH8 =		8,
+	IRQ_DMA_CH9 =		9,
+	IRQ_DMA_CH10 =		10,
+	IRQ_DMA_CH11 =		11,
+	IRQ_DMA_CH12 =		12,
+	IRQ_DMA_CH13 =		13,
+	IRQ_DMA_CH14 =		14,
+	IRQ_DMA_CH15 =		15,
+	IRQ_DMA_ERROR =		16,
+	IRQ_MCM =		17,
+	IRQ_FTFL_COMPLETE =	18,
+	IRQ_FTFL_COLLISION =	19,
+	IRQ_LOW_VOLTAGE =	20,
+	IRQ_LLWU =		21,
+	IRQ_WDOG =		22,
+	IRQ_RNG =		23,
+	IRQ_I2C0 =		24,
+	IRQ_I2C1 =		25,
+	IRQ_SPI0 =		26,
+	IRQ_SPI1 =		27,
+	IRQ_I2S0_TX =		28,
+	IRQ_I2S0_RX =		29,
+	IRQ_UART0_STATUS =	31,
+	IRQ_UART0_ERROR =	32,
+	IRQ_UART1_STATUS =	33,
+	IRQ_UART1_ERROR =	34,
+	IRQ_UART2_STATUS =	35,
+	IRQ_UART2_ERROR =	36,
+	IRQ_UART3_STATUS =	37,
+	IRQ_UART3_ERROR =	38,
+	IRQ_ADC0 =		39,
+	IRQ_CMP0 =		40,
+	IRQ_CMP1 =		41,
+	IRQ_FTM0 =		42,
+	IRQ_FTM1 =		43,
+	IRQ_FTM2 =		44,
+	IRQ_CMT =		45,
+	IRQ_RTC_ALARM =		46,
+	IRQ_RTC_SECOND =	47,
+	IRQ_PIT_CH0 =		48,
+	IRQ_PIT_CH1 =		49,
+	IRQ_PIT_CH2 =		50,
+	IRQ_PIT_CH3 =		51,
+	IRQ_PDB =		52,
+	IRQ_USBOTG =		53,
+	IRQ_USBDCD =		54,
+	IRQ_DAC0 =		56,
+	IRQ_MCG =		57,
+	IRQ_LPTMR =		58,
+	IRQ_PORTA =		59,
+	IRQ_PORTB =		60,
+	IRQ_PORTC =		61,
+	IRQ_PORTD =		62,
+	IRQ_PORTE =		63,
+	IRQ_SOFTWARE =		64,
+	IRQ_SPI2 =		65,
+	IRQ_UART4_STATUS =	66,
+	IRQ_UART4_ERROR =	67,
+	IRQ_UART5_STATUS =	68,
+	IRQ_UART5_ERROR =	69,
+	IRQ_CMP2 =		70,
+	IRQ_FTM3 =		71,
+	IRQ_DAC1 =		72,
+	IRQ_ADC1 =		73,
+	IRQ_I2C2 =		74,
+	IRQ_CAN0_MESSAGE =	75,
+	IRQ_CAN0_BUS_OFF =	76,
+	IRQ_CAN0_ERROR =	77,
+	IRQ_CAN0_TX_WARN =	78,
+	IRQ_CAN0_RX_WARN =	79,
+	IRQ_CAN0_WAKEUP =	80,
+	IRQ_SDHC =		81,
+	IRQ_ENET_TIMER =	82,
+	IRQ_ENET_TX =		83,
+	IRQ_ENET_RX =		84,
+	IRQ_ENET_ERROR =	85
+};
+#define NVIC_NUM_INTERRUPTS	86
+#define DMA_NUM_CHANNELS	16
+
+#define DMAMUX_SOURCE_TSI		1
+#define DMAMUX_SOURCE_UART0_RX		2
+#define DMAMUX_SOURCE_UART0_TX		3
+#define DMAMUX_SOURCE_UART1_RX		4
+#define DMAMUX_SOURCE_UART1_TX		5
+#define DMAMUX_SOURCE_UART2_RX		6
+#define DMAMUX_SOURCE_UART2_TX		7
+#define DMAMUX_SOURCE_UART3_RX		8
+#define DMAMUX_SOURCE_UART3_TX		9
+#define DMAMUX_SOURCE_UART4_RXTX	10
+#define DMAMUX_SOURCE_UART5_RXTX	11
+#define DMAMUX_SOURCE_I2S0_RX		12
+#define DMAMUX_SOURCE_I2S0_TX		13
+#define DMAMUX_SOURCE_SPI0_RX		14
+#define DMAMUX_SOURCE_SPI0_TX		14
+#define DMAMUX_SOURCE_SPI1_RX		16
+#define DMAMUX_SOURCE_SPI1_TX		17
+#define DMAMUX_SOURCE_I2C0		18
+#define DMAMUX_SOURCE_I2C1		19
+#define DMAMUX_SOURCE_I2C2		19
+#define DMAMUX_SOURCE_FTM0_CH0		20
+#define DMAMUX_SOURCE_FTM0_CH1		21
+#define DMAMUX_SOURCE_FTM0_CH2		22
+#define DMAMUX_SOURCE_FTM0_CH3		23
+#define DMAMUX_SOURCE_FTM0_CH4		24
+#define DMAMUX_SOURCE_FTM0_CH5		25
+#define DMAMUX_SOURCE_FTM0_CH6		26
+#define DMAMUX_SOURCE_FTM0_CH7		27
+#define DMAMUX_SOURCE_FTM1_CH0		28
+#define DMAMUX_SOURCE_FTM1_CH1		29
+#define DMAMUX_SOURCE_FTM2_CH0		30
+#define DMAMUX_SOURCE_FTM2_CH1		31
+#define DMAMUX_SOURCE_FTM3_CH0		32
+#define DMAMUX_SOURCE_FTM3_CH1		33
+#define DMAMUX_SOURCE_FTM3_CH2		34
+#define DMAMUX_SOURCE_FTM3_CH3		35
+#define DMAMUX_SOURCE_FTM3_CH4		36
+#define DMAMUX_SOURCE_FTM3_CH5		37
+#define DMAMUX_SOURCE_FTM3_CH6		38
+#define DMAMUX_SOURCE_FTM3_CH7		39
+#define DMAMUX_SOURCE_ADC0		40
+#define DMAMUX_SOURCE_ADC1		41
+#define DMAMUX_SOURCE_CMP0		42
+#define DMAMUX_SOURCE_CMP1		43
+#define DMAMUX_SOURCE_CMP2		44
+#define DMAMUX_SOURCE_DAC0		45
+#define DMAMUX_SOURCE_DAC1		46
+#define DMAMUX_SOURCE_CMT		47
+#define DMAMUX_SOURCE_PDB		48
+#define DMAMUX_SOURCE_PORTA		49
+#define DMAMUX_SOURCE_PORTB		50
+#define DMAMUX_SOURCE_PORTC		51
+#define DMAMUX_SOURCE_PORTD		52
+#define DMAMUX_SOURCE_PORTE		53
+#define DMAMUX_SOURCE_IEEE1588_T0	54
+#define DMAMUX_SOURCE_IEEE1588_T1	55
+#define DMAMUX_SOURCE_IEEE1588_T2	56
+#define DMAMUX_SOURCE_IEEE1588_T3	57
+#define DMAMUX_SOURCE_ALWAYS0		58
+#define DMAMUX_SOURCE_ALWAYS1		59
+#define DMAMUX_SOURCE_ALWAYS2		60
+#define DMAMUX_SOURCE_ALWAYS3		61
+#define DMAMUX_SOURCE_ALWAYS4		62
+#define DMAMUX_SOURCE_ALWAYS5		63
+#define DMAMUX_NUM_SOURCE_ALWAYS	6
+
+#define KINETISK
+#define HAS_KINETISK_UART0
+#define HAS_KINETISK_UART0_FIFO
+#define HAS_KINETISK_UART1
+#define HAS_KINETISK_UART1_FIFO
+#define HAS_KINETISK_UART2
+#define HAS_KINETISK_UART3
+#define HAS_KINETISK_UART4
+#define HAS_KINETISK_UART5
+#define HAS_KINETIS_I2C0
+#define HAS_KINETIS_I2C0_STOPF
+#define HAS_KINETIS_I2C1
+#define HAS_KINETIS_I2C1_STOPF
+#define HAS_KINETIS_I2C2
+#define HAS_KINETIS_I2C2_STOPF
+#define HAS_KINETIS_LLWU_32CH
+#define HAS_KINETIS_MPU
+
+
 #elif defined(__MK66FX1M0__)
 // https://forum.pjrc.com/threads/24633-Any-Chance-of-a-Teensy-3-1?p=78655&viewfull=1#post78655
 enum IRQ_NUMBER_t {
@@ -389,6 +564,7 @@ enum IRQ_NUMBER_t {
 	IRQ_LOW_VOLTAGE =	20,
 	IRQ_LLWU =		21,
 	IRQ_WDOG =		22,
+	IRQ_RNG =		23,
 	IRQ_I2C0 =		24,
 	IRQ_I2C1 =		25,
 	IRQ_SPI0 =		26,
@@ -565,7 +741,11 @@ enum IRQ_NUMBER_t {
 #endif // end of board-specific definitions
 
 
-#if (F_CPU == 180000000)
+#if (F_CPU == 192000000)
+ #define F_PLL 192000000
+ #define F_BUS 64000000
+ #define F_MEM 27428571
+#elif (F_CPU == 180000000)
  #define F_PLL 180000000
  #define F_BUS 60000000
  #define F_MEM 25714286
@@ -1041,6 +1221,7 @@ enum IRQ_NUMBER_t {
 // System Mode Controller
 
 #define SMC_PMPROT		(*(volatile uint8_t  *)0x4007E000) // Power Mode Protection Register
+#define SMC_PMPROT_AHSRUN		((uint8_t)0x80)			// Allow high speed run mode
 #define SMC_PMPROT_AVLP			((uint8_t)0x20)			// Allow very low power modes
 #define SMC_PMPROT_ALLS			((uint8_t)0x08)			// Allow low leakage stop mode
 #define SMC_PMPROT_AVLLS		((uint8_t)0x02)			// Allow very low leakage stop mode
@@ -1060,6 +1241,7 @@ enum IRQ_NUMBER_t {
 #define SMC_PMSTAT_VLPS			((uint8_t)0x10)			// Current power mode is VLPS
 #define SMC_PMSTAT_LLS			((uint8_t)0x20)			// Current power mode is LLS
 #define SMC_PMSTAT_VLLS			((uint8_t)0x40)			// Current power mode is VLLS
+#define SMC_PMSTAT_HSRUN		((uint8_t)0x80)			// Current power mode is HSRUN
 
 // Power Management Controller
 
@@ -4548,6 +4730,15 @@ typedef struct __attribute__((packed)) {
 #define SCB_HFSR		(*(volatile uint32_t *)0xE000ED2C) // HardFault Status
 #define SCB_DFSR		(*(volatile uint32_t *)0xE000ED30) // Debug Fault Status
 #define SCB_MMFAR		(*(volatile uint32_t *)0xE000ED34) // MemManage Fault Address
+#define SCB_BFAR		(*(volatile uint32_t *)0xE000ED38) // Bus Fault Address
+#define SCB_AFAR		(*(volatile uint32_t *)0xE000ED3C) // Aux Fault Address
+#define SCB_CPACR		(*(volatile uint32_t *)0xE000ED88) // Coprocessor Access Control
+#define SCB_FPCCR		(*(volatile uint32_t *)0xE000EF34) // FP Context Control
+#define SCB_FPCAR		(*(volatile uint32_t *)0xE000EF38) // FP Context Address
+#define SCB_FPDSCR		(*(volatile uint32_t *)0xE000EF3C) // FP Default Status Control
+#define SCB_MVFR0		(*(volatile uint32_t *)0xE000EF40) // Media & FP Feature 0
+#define SCB_MVFR1		(*(volatile uint32_t *)0xE000EF44) // Media & FP Feature 1
+#define SCB_MVFR2		(*(volatile uint32_t *)0xE000EF48) // Media & FP Feature 2
 
 #define SYST_CSR		(*(volatile uint32_t *)0xE000E010) // SysTick Control and Status
 #define SYST_CSR_COUNTFLAG		((uint32_t)0x00010000)

teensy3/mk20dx128.c

@@ -243,6 +243,8 @@ __attribute__ ((section(".dmabuffers"), used, aligned(256)))
 __attribute__ ((section(".dmabuffers"), used, aligned(512)))
 #elif defined(__MKL26Z64__)
 __attribute__ ((section(".dmabuffers"), used, aligned(256)))
+#elif defined(__MK64FX512__)
+__attribute__ ((section(".dmabuffers"), used, aligned(512)))
 #elif defined(__MK66FX1M0__)
 __attribute__ ((section(".dmabuffers"), used, aligned(512)))
 #endif
@@ -443,6 +445,93 @@ void (* const _VectorsFlash[NVIC_NUM_INTERRUPTS+16])(void) =
 	software_isr,					// 45 Software interrupt
 	porta_isr,					// 46 Pin detect (Port A)
 	portcd_isr,					// 47 Pin detect (Port C and D)
+#elif defined(__MK64FX512__)
+	dma_ch0_isr,					// 16 DMA channel 0 transfer complete
+	dma_ch1_isr,					// 17 DMA channel 1 transfer complete
+	dma_ch2_isr,					// 18 DMA channel 2 transfer complete
+	dma_ch3_isr,					// 19 DMA channel 3 transfer complete
+	dma_ch4_isr,					// 20 DMA channel 4 transfer complete
+	dma_ch5_isr,					// 21 DMA channel 5 transfer complete
+	dma_ch6_isr,					// 22 DMA channel 6 transfer complete
+	dma_ch7_isr,					// 23 DMA channel 7 transfer complete
+	dma_ch8_isr,					// 24 DMA channel 8 transfer complete
+	dma_ch9_isr,					// 25 DMA channel 9 transfer complete
+	dma_ch10_isr,					// 26 DMA channel 10 transfer complete
+	dma_ch11_isr,					// 27 DMA channel 11 transfer complete
+	dma_ch12_isr,					// 28 DMA channel 12 transfer complete
+	dma_ch13_isr,					// 29 DMA channel 13 transfer complete
+	dma_ch14_isr,					// 30 DMA channel 14 transfer complete
+	dma_ch15_isr,					// 31 DMA channel 15 transfer complete
+	dma_error_isr,					// 32 DMA error interrupt channel
+	mcm_isr,					// 33 MCM
+	flash_cmd_isr,					// 34 Flash Memory Command complete
+	flash_error_isr,				// 35 Flash Read collision
+	low_voltage_isr,				// 36 Low-voltage detect/warning
+	wakeup_isr,					// 37 Low Leakage Wakeup
+	watchdog_isr,					// 38 Both EWM and WDOG interrupt
+	randnum_isr,					// 39 Random Number Generator
+	i2c0_isr,					// 40 I2C0
+	i2c1_isr,					// 41 I2C1
+	spi0_isr,					// 42 SPI0
+	spi1_isr,					// 43 SPI1
+	i2s0_tx_isr,					// 44 I2S0 Transmit
+	i2s0_rx_isr,					// 45 I2S0 Receive
+	unused_isr,					// 46 --
+	uart0_status_isr,				// 47 UART0 status
+	uart0_error_isr,				// 48 UART0 error
+	uart1_status_isr,				// 49 UART1 status
+	uart1_error_isr,				// 50 UART1 error
+	uart2_status_isr,				// 51 UART2 status
+	uart2_error_isr,				// 52 UART2 error
+	uart3_status_isr,				// 53 UART3 status
+	uart3_error_isr,				// 54 UART3 error
+	adc0_isr,					// 55 ADC0
+	cmp0_isr,					// 56 CMP0
+	cmp1_isr,					// 57 CMP1
+	ftm0_isr,					// 58 FTM0
+	ftm1_isr,					// 59 FTM1
+	ftm2_isr,					// 60 FTM2
+	cmt_isr,					// 61 CMT
+	rtc_alarm_isr,					// 62 RTC Alarm interrupt
+	rtc_seconds_isr,				// 63 RTC Seconds interrupt
+	pit0_isr,					// 64 PIT Channel 0
+	pit1_isr,					// 65 PIT Channel 1
+	pit2_isr,					// 66 PIT Channel 2
+	pit3_isr,					// 67 PIT Channel 3
+	pdb_isr,					// 68 PDB Programmable Delay Block
+	usb_isr,					// 69 USB OTG
+	usb_charge_isr,					// 70 USB Charger Detect
+	unused_isr,					// 71 --
+	dac0_isr,					// 72 DAC0
+	mcg_isr,					// 73 MCG
+	lptmr_isr,					// 74 Low Power Timer
+	porta_isr,					// 75 Pin detect (Port A)
+	portb_isr,					// 76 Pin detect (Port B)
+	portc_isr,					// 77 Pin detect (Port C)
+	portd_isr,					// 78 Pin detect (Port D)
+	porte_isr,					// 79 Pin detect (Port E)
+	software_isr,					// 80 Software interrupt
+	spi2_isr,					// 81 SPI2
+	uart4_status_isr,				// 82 UART4 status
+	uart4_error_isr,				// 83 UART4 error
+	uart5_status_isr,				// 84 UART4 status
+	uart5_error_isr,				// 85 UART4 error
+	cmp2_isr,					// 86 CMP2
+	ftm3_isr,					// 87 FTM3
+	dac1_isr,					// 88 DAC1
+	adc1_isr,					// 89 ADC1
+	i2c2_isr,					// 90 I2C2
+	can0_message_isr,				// 91 CAN OR'ed Message buffer (0-15)
+	can0_bus_off_isr,				// 92 CAN Bus Off
+	can0_error_isr,					// 93 CAN Error
+	can0_tx_warn_isr,				// 94 CAN Transmit Warning
+	can0_rx_warn_isr,				// 95 CAN Receive Warning
+	can0_wakeup_isr,				// 96 CAN Wake Up
+	sdhc_isr,					// 97 SDHC
+	enet_timer_isr,					// 98 Ethernet IEEE1588 Timers
+	enet_tx_isr,					// 99 Ethernet Transmit
+	enet_rx_isr,					// 100 Ethernet Receive
+	enet_error_isr,					// 101 Ethernet Error
 #elif defined(__MK66FX1M0__)
 	dma_ch0_isr,					// 16 DMA channel 0 transfer complete
 	dma_ch1_isr,					// 17 DMA channel 1 transfer complete
@@ -530,7 +619,7 @@ void (* const _VectorsFlash[NVIC_NUM_INTERRUPTS+16])(void) =
 	enet_tx_isr,					// 99 Ethernet Transmit
 	enet_rx_isr,					// 100 Ethernet Receive
 	enet_error_isr,					// 101 Ethernet Error
-	lpuart0_status_isr,				// 102 ADC1
+	lpuart0_status_isr,				// 102 LPUART
 	tsi0_isr,					// 103 TSI0
 	tpm1_isr,					// 104 FTM1
 	tpm2_isr,					// 105 FTM2
@@ -611,7 +700,7 @@ void ResetHandler(void)
 	SIM_SCGC3 = SIM_SCGC3_ADC1 | SIM_SCGC3_FTM2;
 	SIM_SCGC5 = 0x00043F82;		// clocks active to all GPIO
 	SIM_SCGC6 = SIM_SCGC6_RTC | SIM_SCGC6_FTM0 | SIM_SCGC6_FTM1 | SIM_SCGC6_ADC0 | SIM_SCGC6_FTFL;
-#elif defined(__MK66FX1M0__)
+#elif defined(__MK64FX512__) || defined(__MK66FX1M0__)
 	SIM_SCGC3 = SIM_SCGC3_ADC1 | SIM_SCGC3_FTM2 | SIM_SCGC3_FTM3;
 	SIM_SCGC5 = 0x00043F82;		// clocks active to all GPIO
 	SIM_SCGC6 = SIM_SCGC6_RTC | SIM_SCGC6_FTM0 | SIM_SCGC6_FTM1 | SIM_SCGC6_ADC0 | SIM_SCGC6_FTFL;
@@ -624,6 +713,9 @@ void ResetHandler(void)
 	SIM_SCGC5 = 0x00003F82;		// clocks active to all GPIO
 	SIM_SCGC6 = SIM_SCGC6_ADC0 | SIM_SCGC6_TPM0 | SIM_SCGC6_TPM1 | SIM_SCGC6_TPM2 | SIM_SCGC6_FTFL;
 #endif
+#if defined(__MK64FX512__) || defined(__MK66FX1M0__)
+	SCB_CPACR = 0x00F00000;
+#endif
 #if 0
 	// testing only, enable ser_print
 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV4(1);
@@ -647,7 +739,11 @@ void ResetHandler(void)
 
     // since this is a write once register, make it visible to all F_CPU's
     // so we can into other sleep modes in the future at any speed
+#if defined(__MK66FX1M0__)
+	SMC_PMPROT = SMC_PMPROT_AHSRUN | SMC_PMPROT_AVLP | SMC_PMPROT_ALLS | SMC_PMPROT_AVLLS;
+#else
 	SMC_PMPROT = SMC_PMPROT_AVLP | SMC_PMPROT_ALLS | SMC_PMPROT_AVLLS;
+#endif
     
 	// TODO: do this while the PLL is waiting to lock....
 	while (dest < &_edata) *dest++ = *src++;
@@ -723,11 +819,33 @@ void ResetHandler(void)
   #else
 	// if we need faster than the crystal, turn on the PLL
    #if defined(__MK66FX1M0__)
-    #if F_CPU == 96000000
+    #if F_CPU > 120000000
+	SMC_PMCTRL = SMC_PMCTRL_RUNM(3); // enter HSRUN mode
+	while (SMC_PMSTAT != SMC_PMSTAT_HSRUN) ; // wait for HSRUN
+    #endif
+    #if F_CPU == 192000000
+	MCG_C5 = MCG_C5_PRDIV0(0);
+	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(8);
+    #elif F_CPU == 180000000
+	MCG_C5 = MCG_C5_PRDIV0(1);
+	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(29);
+    #elif F_CPU == 168000000
+	MCG_C5 = MCG_C5_PRDIV0(0);
+	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(5);
+    #elif F_CPU == 144000000
+	MCG_C5 = MCG_C5_PRDIV0(0);
+	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(2);
+    #elif F_CPU == 120000000
+	MCG_C5 = MCG_C5_PRDIV0(1);
+	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(14);
+    #elif F_CPU == 96000000 || F_CPU == 48000000 || F_CPU == 24000000
 	MCG_C5 = MCG_C5_PRDIV0(1);
 	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(8);
-    #else
-    #error "MK66FX1M0 only supports 96 MHz so far...."
+    #elif F_CPU == 72000000
+	MCG_C5 = MCG_C5_PRDIV0(1);
+	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(2);
+    #elif F_CPU > 16000000
+    #error "MK66FX1M0 does not support this clock speed yet...."
     #endif
    #else
     #if F_CPU == 72000000
@@ -743,12 +861,13 @@ void ResetHandler(void)
 	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(6); // config PLL for 120 MHz output
     #elif F_CPU == 72000000
 	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(3); // config PLL for 72 MHz output
-    #else
+    #elif F_CPU == 96000000 || F_CPU == 48000000 || F_CPU == 24000000
 	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0); // config PLL for 96 MHz output
+    #elif F_CPU > 16000000
+    #error "This clock speed isn't supported..."
     #endif
    #endif
 
-
 	// wait for PLL to start using xtal as its input
 	while (!(MCG_S & MCG_S_PLLST)) ;
 	// wait for PLL to lock
@@ -757,80 +876,89 @@ void ResetHandler(void)
   #endif
 #endif
 	// now program the clock dividers
-#if F_CPU == 168000000
+#if F_CPU == 192000000
+	// config divisors: 192 MHz core, 64 MHz bus, 27.4 MHz flash, USB = 192 * 4
+	// TODO: gradual ramp-up for HSRUN mode
+	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(2) | SIM_CLKDIV1_OUTDIV4(6);
+	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(3);
+#elif F_CPU == 180000000
+	// config divisors: 180 MHz core, 60 MHz bus, 25.7 MHz flash, USB = not feasible
+	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(2) | SIM_CLKDIV1_OUTDIV4(6);
+	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(6) | SIM_CLKDIV2_USBFRAC;
+#elif F_CPU == 168000000
 	// config divisors: 168 MHz core, 56 MHz bus, 28 MHz flash, USB = 168 * 2 / 7
-	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(2) |	 SIM_CLKDIV1_OUTDIV4(5);
+	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(2) | SIM_CLKDIV1_OUTDIV4(5);
 	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(6) | SIM_CLKDIV2_USBFRAC;
 #elif F_CPU == 144000000
 	// config divisors: 144 MHz core, 48 MHz bus, 28.8 MHz flash, USB = 144 / 3
-	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(2) |	 SIM_CLKDIV1_OUTDIV4(4);
+	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(2) | SIM_CLKDIV1_OUTDIV4(4);
 	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(2);
 #elif F_CPU == 120000000
 	// config divisors: 120 MHz core, 60 MHz bus, 24 MHz flash, USB = 128 * 2 / 5
-	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) |	 SIM_CLKDIV1_OUTDIV4(4);
+	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(4);
 	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC;
 #elif F_CPU == 96000000
 	// config divisors: 96 MHz core, 48 MHz bus, 24 MHz flash, USB = 96 / 2
-	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) |	 SIM_CLKDIV1_OUTDIV4(3);
+	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(3);
 	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1);
 #elif F_CPU == 72000000
 	// config divisors: 72 MHz core, 36 MHz bus, 24 MHz flash, USB = 72 * 2 / 3
-	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) |	 SIM_CLKDIV1_OUTDIV4(2);
+	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(2);
 	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC;
 #elif F_CPU == 48000000
 	// config divisors: 48 MHz core, 48 MHz bus, 24 MHz flash, USB = 96 / 2
-	#if defined(KINETISK)
-	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV2(1) |	 SIM_CLKDIV1_OUTDIV4(3);
+  #if defined(KINETISK)
+	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(3);
 	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1);
-	#elif defined(KINETISL)
+  #elif defined(KINETISL)
 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV4(1);
-	#endif
+  #endif
 #elif F_CPU == 24000000
 	// config divisors: 24 MHz core, 24 MHz bus, 24 MHz flash, USB = 96 / 2
 	#if defined(KINETISK)
-	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV2(3) |	 SIM_CLKDIV1_OUTDIV4(3);
+	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV2(3) | SIM_CLKDIV1_OUTDIV4(3);
 	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1);
 	#elif defined(KINETISL)
 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV4(0);
 	#endif
 #elif F_CPU == 16000000
 	// config divisors: 16 MHz core, 16 MHz bus, 16 MHz flash
-#if defined(KINETISK)
-    SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) |	 SIM_CLKDIV1_OUTDIV4(0);
-#elif defined(KINETISL)
-    SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV4(0);
-#endif
+  #if defined(KINETISK)
+	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) | SIM_CLKDIV1_OUTDIV4(0);
+  #elif defined(KINETISL)
+	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV4(0);
+  #endif
 #elif F_CPU == 8000000
 	// config divisors: 8 MHz core, 8 MHz bus, 8 MHz flash
-#if defined(KINETISK)
-    SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV2(1) |	 SIM_CLKDIV1_OUTDIV4(1);
-#elif defined(KINETISL)
-    SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV4(0);
-#endif
+  #if defined(KINETISK)
+	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(1);
+  #elif defined(KINETISL)
+	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV4(0);
+  #endif
 #elif F_CPU == 4000000
-    // config divisors: 4 MHz core, 4 MHz bus, 2 MHz flash
-    // since we are running from external clock 16MHz
-    // fix outdiv too -> cpu 16/4, bus 16/4, flash 16/4
-    // here we can go into vlpr?
+	// config divisors: 4 MHz core, 4 MHz bus, 2 MHz flash
+	// since we are running from external clock 16MHz
+	// fix outdiv too -> cpu 16/4, bus 16/4, flash 16/4
+	// here we can go into vlpr?
 	// config divisors: 4 MHz core, 4 MHz bus, 4 MHz flash
-#if defined(KINETISK)
-    SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV2(3) |	 SIM_CLKDIV1_OUTDIV4(3);
-#elif defined(KINETISL)
-    SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV4(0);
-#endif
+  #if defined(KINETISK)
+	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV2(3) | SIM_CLKDIV1_OUTDIV4(3);
+  #elif defined(KINETISL)
+	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV4(0);
+  #endif
 #elif F_CPU == 2000000
-    // since we are running from the fast internal reference clock 4MHz
-    // but is divided down by 2 so we actually have a 2MHz, MCG_SC[FCDIV] default is 2
-    // fix outdiv -> cpu 2/1, bus 2/1, flash 2/2
+	// since we are running from the fast internal reference clock 4MHz
+	// but is divided down by 2 so we actually have a 2MHz, MCG_SC[FCDIV] default is 2
+	// fix outdiv -> cpu 2/1, bus 2/1, flash 2/2
 	// config divisors: 2 MHz core, 2 MHz bus, 1 MHz flash
-#if defined(KINETISK)
-    SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) |	 SIM_CLKDIV1_OUTDIV4(1);
-#elif defined(KINETISL)
-    // config divisors: 2 MHz core, 1 MHz bus, 1 MHz flash
-    SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV4(1);
-#endif
+  #if defined(KINETISK)
+	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) | SIM_CLKDIV1_OUTDIV4(1);
+  #elif defined(KINETISL)
+	// config divisors: 2 MHz core, 1 MHz bus, 1 MHz flash
+	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV4(1);
+  #endif
 #else
-#error "Error, F_CPU must be 168, 144, 120, 96, 72, 48, 24, 16, 8, 4, or 2 MHz"
+#error "Error, F_CPU must be 192, 180, 168, 144, 120, 96, 72, 48, 24, 16, 8, 4, or 2 MHz"
 #endif
 
 #if F_CPU > 16000000

teensy3/mk64fx512.ld

@@ -0,0 +1,114 @@
+/* Teensyduino Core Library
+ * http://www.pjrc.com/teensy/
+ * Copyright (c) 2013 PJRC.COM, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * 1. The above copyright notice and this permission notice shall be 
+ * included in all copies or substantial portions of the Software.
+ *
+ * 2. If the Software is incorporated into a build system that allows 
+ * selection among a list of target devices, then similar target
+ * devices manufactured by PJRC.COM must be included in the list of
+ * target devices and selectable in the same manner.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+MEMORY
+{
+	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+	RAM  (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 192K
+}
+
+
+SECTIONS
+{
+	.text : {
+		. = 0;
+		KEEP(*(.vectors))
+		*(.startup*)
+		/* TODO: does linker detect startup overflow onto flashconfig? */
+		. = 0x400;
+		KEEP(*(.flashconfig*))
+		*(.text*)
+		*(.rodata*)
+		. = ALIGN(4);
+		KEEP(*(.init))
+		. = ALIGN(4);
+		__preinit_array_start = .;
+		KEEP (*(.preinit_array))
+		__preinit_array_end = .;
+		__init_array_start = .;
+		KEEP (*(SORT(.init_array.*)))
+		KEEP (*(.init_array))
+		__init_array_end = .;
+	} > FLASH = 0xFF
+
+	.ARM.exidx : {
+		__exidx_start = .;
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+		__exidx_end = .;
+	} > FLASH
+	_etext = .;
+
+	.usbdescriptortable (NOLOAD) : {
+		/* . = ORIGIN(RAM); */
+		. = ALIGN(512);
+		*(.usbdescriptortable*)
+	} > RAM
+
+	.dmabuffers (NOLOAD) : {
+		. = ALIGN(4);
+		*(.dmabuffers*)
+	} > RAM
+
+	.usbbuffers (NOLOAD) : {
+		. = ALIGN(4);
+		*(.usbbuffers*)
+	} > RAM
+
+	.data : AT (_etext) {
+		. = ALIGN(4);
+		_sdata = .; 
+		*(.fastrun*)
+		*(.data*)
+		. = ALIGN(4);
+		_edata = .; 
+	} > RAM
+
+	.noinit (NOLOAD) : {
+		*(.noinit*)
+	} > RAM
+
+	.bss : {
+		. = ALIGN(4);
+		_sbss = .;
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		_ebss = .;
+		__bss_end = .;
+		__bss_end__ = .;
+	} > RAM
+
+	_estack = ORIGIN(RAM) + LENGTH(RAM);
+}
+
+
+
+