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Remove unused IMXRT1052 stuff

main
PaulStoffregen 5 years ago
parent
5aeeb9ad58
commit
ddb23fa5d9
7 changed files with 5 additions and 817 deletions
Unified View Show Diff Stats
  1. +1
    -3
      teensy4/AudioStream.cpp
  2. +1
    -3
      teensy4/bootdata.c
  3. +1
    -602
      teensy4/core_pins.h
  4. +0
    -89
      teensy4/imxrt1052.ld
  5. +0
    -72
      teensy4/interrupt.c
  6. +1
    -1
      teensy4/pins_arduino.h
  7. +1
    -47
      teensy4/pwm.c

+ 1
- 3
teensy4/AudioStream.cpp View File

#include <Arduino.h> #include <Arduino.h>
#include "AudioStream.h" #include "AudioStream.h"


#if defined(__IMXRT1052__)
#define MAX_AUDIO_MEMORY 229376
#elif defined(__IMXRT1062__)
#if defined(__IMXRT1062__)
#define MAX_AUDIO_MEMORY 229376 #define MAX_AUDIO_MEMORY 229376
#endif #endif



+ 1
- 3
teensy4/bootdata.c View File



__attribute__ ((section(".vectors"), used)) __attribute__ ((section(".vectors"), used))
const uint32_t vector_table[2] = { const uint32_t vector_table[2] = {
#if defined(__IMXRT1052__)
(uint32_t)&_estack,
#elif defined(__IMXRT1062__)
#if defined(__IMXRT1062__)
0x20010000, // 64K DTCM for boot, ResetHandler configures stack after ITCM/DTCM setup 0x20010000, // 64K DTCM for boot, ResetHandler configures stack after ITCM/DTCM setup
#endif #endif
(uint32_t)&ResetHandler (uint32_t)&ResetHandler

+ 1
- 602
teensy4/core_pins.h View File

#define CORE_PIN39_BITMASK (1<<(CORE_PIN39_BIT)) #define CORE_PIN39_BITMASK (1<<(CORE_PIN39_BIT))




#if 1
// Fast GPIO // Fast GPIO
#define CORE_PIN0_PORTREG GPIO6_DR #define CORE_PIN0_PORTREG GPIO6_DR
#define CORE_PIN1_PORTREG GPIO6_DR #define CORE_PIN1_PORTREG GPIO6_DR
#define CORE_PIN39_PINREG GPIO8_PSR #define CORE_PIN39_PINREG GPIO8_PSR




#else
// Slow GPIO
#define CORE_PIN0_PORTREG GPIO1_DR
#define CORE_PIN1_PORTREG GPIO1_DR
#define CORE_PIN2_PORTREG GPIO4_DR
#define CORE_PIN3_PORTREG GPIO4_DR
#define CORE_PIN4_PORTREG GPIO4_DR
#define CORE_PIN5_PORTREG GPIO4_DR
#define CORE_PIN6_PORTREG GPIO2_DR
#define CORE_PIN7_PORTREG GPIO2_DR
#define CORE_PIN8_PORTREG GPIO2_DR
#define CORE_PIN9_PORTREG GPIO2_DR
#define CORE_PIN10_PORTREG GPIO2_DR
#define CORE_PIN11_PORTREG GPIO2_DR
#define CORE_PIN12_PORTREG GPIO2_DR
#define CORE_PIN13_PORTREG GPIO2_DR
#define CORE_PIN14_PORTREG GPIO1_DR
#define CORE_PIN15_PORTREG GPIO1_DR
#define CORE_PIN16_PORTREG GPIO1_DR
#define CORE_PIN17_PORTREG GPIO1_DR
#define CORE_PIN18_PORTREG GPIO1_DR
#define CORE_PIN19_PORTREG GPIO1_DR
#define CORE_PIN20_PORTREG GPIO1_DR
#define CORE_PIN21_PORTREG GPIO1_DR
#define CORE_PIN22_PORTREG GPIO1_DR
#define CORE_PIN23_PORTREG GPIO1_DR
#define CORE_PIN24_PORTREG GPIO1_DR
#define CORE_PIN25_PORTREG GPIO1_DR
#define CORE_PIN26_PORTREG GPIO1_DR
#define CORE_PIN27_PORTREG GPIO1_DR
#define CORE_PIN28_PORTREG GPIO3_DR
#define CORE_PIN29_PORTREG GPIO4_DR
#define CORE_PIN30_PORTREG GPIO3_DR
#define CORE_PIN31_PORTREG GPIO3_DR
#define CORE_PIN32_PORTREG GPIO2_DR
#define CORE_PIN33_PORTREG GPIO4_DR
#define CORE_PIN34_PORTREG GPIO3_DR
#define CORE_PIN35_PORTREG GPIO3_DR
#define CORE_PIN36_PORTREG GPIO3_DR
#define CORE_PIN37_PORTREG GPIO3_DR
#define CORE_PIN38_PORTREG GPIO3_DR
#define CORE_PIN39_PORTREG GPIO3_DR

#define CORE_PIN0_PORTSET GPIO1_DR_SET
#define CORE_PIN1_PORTSET GPIO1_DR_SET
#define CORE_PIN2_PORTSET GPIO4_DR_SET
#define CORE_PIN3_PORTSET GPIO4_DR_SET
#define CORE_PIN4_PORTSET GPIO4_DR_SET
#define CORE_PIN5_PORTSET GPIO4_DR_SET
#define CORE_PIN6_PORTSET GPIO2_DR_SET
#define CORE_PIN7_PORTSET GPIO2_DR_SET
#define CORE_PIN8_PORTSET GPIO2_DR_SET
#define CORE_PIN9_PORTSET GPIO2_DR_SET
#define CORE_PIN10_PORTSET GPIO2_DR_SET
#define CORE_PIN11_PORTSET GPIO2_DR_SET
#define CORE_PIN12_PORTSET GPIO2_DR_SET
#define CORE_PIN13_PORTSET GPIO2_DR_SET
#define CORE_PIN14_PORTSET GPIO1_DR_SET
#define CORE_PIN15_PORTSET GPIO1_DR_SET
#define CORE_PIN16_PORTSET GPIO1_DR_SET
#define CORE_PIN17_PORTSET GPIO1_DR_SET
#define CORE_PIN18_PORTSET GPIO1_DR_SET
#define CORE_PIN19_PORTSET GPIO1_DR_SET
#define CORE_PIN20_PORTSET GPIO1_DR_SET
#define CORE_PIN21_PORTSET GPIO1_DR_SET
#define CORE_PIN22_PORTSET GPIO1_DR_SET
#define CORE_PIN23_PORTSET GPIO1_DR_SET
#define CORE_PIN24_PORTSET GPIO1_DR_SET
#define CORE_PIN25_PORTSET GPIO1_DR_SET
#define CORE_PIN26_PORTSET GPIO1_DR_SET
#define CORE_PIN27_PORTSET GPIO1_DR_SET
#define CORE_PIN28_PORTSET GPIO3_DR_SET
#define CORE_PIN29_PORTSET GPIO4_DR_SET
#define CORE_PIN30_PORTSET GPIO3_DR_SET
#define CORE_PIN31_PORTSET GPIO3_DR_SET
#define CORE_PIN32_PORTSET GPIO2_DR_SET
#define CORE_PIN33_PORTSET GPIO4_DR_SET
#define CORE_PIN34_PORTSET GPIO3_DR_SET
#define CORE_PIN35_PORTSET GPIO3_DR_SET
#define CORE_PIN36_PORTSET GPIO3_DR_SET
#define CORE_PIN37_PORTSET GPIO3_DR_SET
#define CORE_PIN38_PORTSET GPIO3_DR_SET
#define CORE_PIN39_PORTSET GPIO3_DR_SET

#define CORE_PIN0_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN1_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN2_PORTCLEAR GPIO4_DR_CLEAR
#define CORE_PIN3_PORTCLEAR GPIO4_DR_CLEAR
#define CORE_PIN4_PORTCLEAR GPIO4_DR_CLEAR
#define CORE_PIN5_PORTCLEAR GPIO4_DR_CLEAR
#define CORE_PIN6_PORTCLEAR GPIO2_DR_CLEAR
#define CORE_PIN7_PORTCLEAR GPIO2_DR_CLEAR
#define CORE_PIN8_PORTCLEAR GPIO2_DR_CLEAR
#define CORE_PIN9_PORTCLEAR GPIO2_DR_CLEAR
#define CORE_PIN10_PORTCLEAR GPIO2_DR_CLEAR
#define CORE_PIN11_PORTCLEAR GPIO2_DR_CLEAR
#define CORE_PIN12_PORTCLEAR GPIO2_DR_CLEAR
#define CORE_PIN13_PORTCLEAR GPIO2_DR_CLEAR
#define CORE_PIN14_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN15_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN16_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN17_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN18_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN19_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN20_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN21_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN22_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN23_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN24_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN25_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN26_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN27_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN28_PORTCLEAR GPIO3_DR_CLEAR
#define CORE_PIN29_PORTCLEAR GPIO4_DR_CLEAR
#define CORE_PIN30_PORTCLEAR GPIO3_DR_CLEAR
#define CORE_PIN31_PORTCLEAR GPIO3_DR_CLEAR
#define CORE_PIN32_PORTCLEAR GPIO2_DR_CLEAR
#define CORE_PIN33_PORTCLEAR GPIO4_DR_CLEAR
#define CORE_PIN34_PORTCLEAR GPIO3_DR_CLEAR
#define CORE_PIN35_PORTCLEAR GPIO3_DR_CLEAR
#define CORE_PIN36_PORTCLEAR GPIO3_DR_CLEAR
#define CORE_PIN37_PORTCLEAR GPIO3_DR_CLEAR
#define CORE_PIN38_PORTCLEAR GPIO3_DR_CLEAR
#define CORE_PIN39_PORTCLEAR GPIO3_DR_CLEAR

#define CORE_PIN0_DDRREG GPIO1_GDIR
#define CORE_PIN1_DDRREG GPIO1_GDIR
#define CORE_PIN2_DDRREG GPIO4_GDIR
#define CORE_PIN3_DDRREG GPIO4_GDIR
#define CORE_PIN4_DDRREG GPIO4_GDIR
#define CORE_PIN5_DDRREG GPIO4_GDIR
#define CORE_PIN6_DDRREG GPIO2_GDIR
#define CORE_PIN7_DDRREG GPIO2_GDIR
#define CORE_PIN8_DDRREG GPIO2_GDIR
#define CORE_PIN9_DDRREG GPIO2_GDIR
#define CORE_PIN10_DDRREG GPIO2_GDIR
#define CORE_PIN11_DDRREG GPIO2_GDIR
#define CORE_PIN12_DDRREG GPIO2_GDIR
#define CORE_PIN13_DDRREG GPIO2_GDIR
#define CORE_PIN14_DDRREG GPIO1_GDIR
#define CORE_PIN15_DDRREG GPIO1_GDIR
#define CORE_PIN16_DDRREG GPIO1_GDIR
#define CORE_PIN17_DDRREG GPIO1_GDIR
#define CORE_PIN18_DDRREG GPIO1_GDIR
#define CORE_PIN19_DDRREG GPIO1_GDIR
#define CORE_PIN20_DDRREG GPIO1_GDIR
#define CORE_PIN21_DDRREG GPIO1_GDIR
#define CORE_PIN22_DDRREG GPIO1_GDIR
#define CORE_PIN23_DDRREG GPIO1_GDIR
#define CORE_PIN24_DDRREG GPIO1_GDIR
#define CORE_PIN25_DDRREG GPIO1_GDIR
#define CORE_PIN26_DDRREG GPIO1_GDIR
#define CORE_PIN27_DDRREG GPIO1_GDIR
#define CORE_PIN28_DDRREG GPIO3_GDIR
#define CORE_PIN29_DDRREG GPIO4_GDIR
#define CORE_PIN30_DDRREG GPIO3_GDIR
#define CORE_PIN31_DDRREG GPIO3_GDIR
#define CORE_PIN32_DDRREG GPIO2_GDIR
#define CORE_PIN33_DDRREG GPIO4_GDIR
#define CORE_PIN34_DDRREG GPIO3_GDIR
#define CORE_PIN35_DDRREG GPIO3_GDIR
#define CORE_PIN36_DDRREG GPIO3_GDIR
#define CORE_PIN37_DDRREG GPIO3_GDIR
#define CORE_PIN38_DDRREG GPIO3_GDIR
#define CORE_PIN39_DDRREG GPIO3_GDIR

#define CORE_PIN0_PINREG GPIO1_PSR
#define CORE_PIN1_PINREG GPIO1_PSR
#define CORE_PIN2_PINREG GPIO4_PSR
#define CORE_PIN3_PINREG GPIO4_PSR
#define CORE_PIN4_PINREG GPIO4_PSR
#define CORE_PIN5_PINREG GPIO4_PSR
#define CORE_PIN6_PINREG GPIO2_PSR
#define CORE_PIN7_PINREG GPIO2_PSR
#define CORE_PIN8_PINREG GPIO2_PSR
#define CORE_PIN9_PINREG GPIO2_PSR
#define CORE_PIN10_PINREG GPIO2_PSR
#define CORE_PIN11_PINREG GPIO2_PSR
#define CORE_PIN12_PINREG GPIO2_PSR
#define CORE_PIN13_PINREG GPIO2_PSR
#define CORE_PIN14_PINREG GPIO1_PSR
#define CORE_PIN15_PINREG GPIO1_PSR
#define CORE_PIN16_PINREG GPIO1_PSR
#define CORE_PIN17_PINREG GPIO1_PSR
#define CORE_PIN18_PINREG GPIO1_PSR
#define CORE_PIN19_PINREG GPIO1_PSR
#define CORE_PIN20_PINREG GPIO1_PSR
#define CORE_PIN21_PINREG GPIO1_PSR
#define CORE_PIN22_PINREG GPIO1_PSR
#define CORE_PIN23_PINREG GPIO1_PSR
#define CORE_PIN24_PINREG GPIO1_PSR
#define CORE_PIN25_PINREG GPIO1_PSR
#define CORE_PIN26_PINREG GPIO1_PSR
#define CORE_PIN27_PINREG GPIO1_PSR
#define CORE_PIN28_PINREG GPIO3_PSR
#define CORE_PIN29_PINREG GPIO4_PSR
#define CORE_PIN30_PINREG GPIO3_PSR
#define CORE_PIN31_PINREG GPIO3_PSR
#define CORE_PIN32_PINREG GPIO2_PSR
#define CORE_PIN33_PINREG GPIO4_PSR
#define CORE_PIN34_PINREG GPIO3_PSR
#define CORE_PIN35_PINREG GPIO3_PSR
#define CORE_PIN36_PINREG GPIO3_PSR
#define CORE_PIN37_PINREG GPIO3_PSR
#define CORE_PIN38_PINREG GPIO3_PSR
#define CORE_PIN39_PINREG GPIO3_PSR
#endif // Slow GPIO



// mux config registers control which peripheral uses the pin // mux config registers control which peripheral uses the pin
#define CORE_PIN0_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 #define CORE_PIN0_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03
#define CORE_INT39_PIN 39 #define CORE_INT39_PIN 39
#define CORE_INT_EVERY_PIN 1 #define CORE_INT_EVERY_PIN 1



#elif defined(__IMXRT1052__)

#define CORE_NUM_TOTAL_PINS 34
#define CORE_NUM_DIGITAL 34
#define CORE_NUM_INTERRUPT 34
#define CORE_NUM_ANALOG 14
#define CORE_NUM_PWM 27

#define CORE_PIN0_BIT 3
#define CORE_PIN1_BIT 2
#define CORE_PIN2_BIT 4
#define CORE_PIN3_BIT 5
#define CORE_PIN4_BIT 6
#define CORE_PIN5_BIT 7
#define CORE_PIN6_BIT 17
#define CORE_PIN7_BIT 16
#define CORE_PIN8_BIT 10
#define CORE_PIN9_BIT 11
#define CORE_PIN10_BIT 0
#define CORE_PIN11_BIT 2
#define CORE_PIN12_BIT 1
#define CORE_PIN13_BIT 3
#define CORE_PIN14_BIT 18
#define CORE_PIN15_BIT 19
#define CORE_PIN16_BIT 23
#define CORE_PIN17_BIT 22
#define CORE_PIN18_BIT 17
#define CORE_PIN19_BIT 16
#define CORE_PIN20_BIT 26
#define CORE_PIN21_BIT 27
#define CORE_PIN22_BIT 24
#define CORE_PIN23_BIT 25
#define CORE_PIN24_BIT 12
#define CORE_PIN25_BIT 13
#define CORE_PIN26_BIT 30
#define CORE_PIN27_BIT 31
#define CORE_PIN28_BIT 18
#define CORE_PIN29_BIT 31
#define CORE_PIN30_BIT 24
#define CORE_PIN31_BIT 23
#define CORE_PIN32_BIT 12
#define CORE_PIN33_BIT 8

#define CORE_PIN0_BITMASK (1<<(CORE_PIN0_BIT))
#define CORE_PIN1_BITMASK (1<<(CORE_PIN1_BIT))
#define CORE_PIN2_BITMASK (1<<(CORE_PIN2_BIT))
#define CORE_PIN3_BITMASK (1<<(CORE_PIN3_BIT))
#define CORE_PIN4_BITMASK (1<<(CORE_PIN4_BIT))
#define CORE_PIN5_BITMASK (1<<(CORE_PIN5_BIT))
#define CORE_PIN6_BITMASK (1<<(CORE_PIN6_BIT))
#define CORE_PIN7_BITMASK (1<<(CORE_PIN7_BIT))
#define CORE_PIN8_BITMASK (1<<(CORE_PIN8_BIT))
#define CORE_PIN9_BITMASK (1<<(CORE_PIN9_BIT))
#define CORE_PIN10_BITMASK (1<<(CORE_PIN10_BIT))
#define CORE_PIN11_BITMASK (1<<(CORE_PIN11_BIT))
#define CORE_PIN12_BITMASK (1<<(CORE_PIN12_BIT))
#define CORE_PIN13_BITMASK (1<<(CORE_PIN13_BIT))
#define CORE_PIN14_BITMASK (1<<(CORE_PIN14_BIT))
#define CORE_PIN15_BITMASK (1<<(CORE_PIN15_BIT))
#define CORE_PIN16_BITMASK (1<<(CORE_PIN16_BIT))
#define CORE_PIN17_BITMASK (1<<(CORE_PIN17_BIT))
#define CORE_PIN18_BITMASK (1<<(CORE_PIN18_BIT))
#define CORE_PIN19_BITMASK (1<<(CORE_PIN19_BIT))
#define CORE_PIN20_BITMASK (1<<(CORE_PIN20_BIT))
#define CORE_PIN21_BITMASK (1<<(CORE_PIN21_BIT))
#define CORE_PIN22_BITMASK (1<<(CORE_PIN22_BIT))
#define CORE_PIN23_BITMASK (1<<(CORE_PIN23_BIT))
#define CORE_PIN24_BITMASK (1<<(CORE_PIN24_BIT))
#define CORE_PIN25_BITMASK (1<<(CORE_PIN25_BIT))
#define CORE_PIN26_BITMASK (1<<(CORE_PIN26_BIT))
#define CORE_PIN27_BITMASK (1<<(CORE_PIN27_BIT))
#define CORE_PIN28_BITMASK (1<<(CORE_PIN28_BIT))
#define CORE_PIN29_BITMASK (1<<(CORE_PIN29_BIT))
#define CORE_PIN30_BITMASK (1<<(CORE_PIN30_BIT))
#define CORE_PIN31_BITMASK (1<<(CORE_PIN31_BIT))
#define CORE_PIN32_BITMASK (1<<(CORE_PIN32_BIT))
#define CORE_PIN33_BITMASK (1<<(CORE_PIN33_BIT))

#define CORE_PIN0_PORTREG GPIO1_DR
#define CORE_PIN1_PORTREG GPIO1_DR
#define CORE_PIN2_PORTREG GPIO4_DR
#define CORE_PIN3_PORTREG GPIO4_DR
#define CORE_PIN4_PORTREG GPIO4_DR
#define CORE_PIN5_PORTREG GPIO4_DR
#define CORE_PIN6_PORTREG GPIO2_DR
#define CORE_PIN7_PORTREG GPIO2_DR
#define CORE_PIN8_PORTREG GPIO2_DR
#define CORE_PIN9_PORTREG GPIO2_DR
#define CORE_PIN10_PORTREG GPIO2_DR
#define CORE_PIN11_PORTREG GPIO2_DR
#define CORE_PIN12_PORTREG GPIO2_DR
#define CORE_PIN13_PORTREG GPIO2_DR
#define CORE_PIN14_PORTREG GPIO1_DR
#define CORE_PIN15_PORTREG GPIO1_DR
#define CORE_PIN16_PORTREG GPIO1_DR
#define CORE_PIN17_PORTREG GPIO1_DR
#define CORE_PIN18_PORTREG GPIO1_DR
#define CORE_PIN19_PORTREG GPIO1_DR
#define CORE_PIN20_PORTREG GPIO1_DR
#define CORE_PIN21_PORTREG GPIO1_DR
#define CORE_PIN22_PORTREG GPIO1_DR
#define CORE_PIN23_PORTREG GPIO1_DR
#define CORE_PIN24_PORTREG GPIO1_DR
#define CORE_PIN25_PORTREG GPIO1_DR
#define CORE_PIN26_PORTREG GPIO1_DR
#define CORE_PIN27_PORTREG GPIO1_DR
#define CORE_PIN28_PORTREG GPIO3_DR
#define CORE_PIN29_PORTREG GPIO4_DR
#define CORE_PIN30_PORTREG GPIO4_DR
#define CORE_PIN31_PORTREG GPIO4_DR
#define CORE_PIN32_PORTREG GPIO2_DR
#define CORE_PIN33_PORTREG GPIO4_DR

#define CORE_PIN0_PORTSET GPIO1_DR_SET
#define CORE_PIN1_PORTSET GPIO1_DR_SET
#define CORE_PIN2_PORTSET GPIO4_DR_SET
#define CORE_PIN3_PORTSET GPIO4_DR_SET
#define CORE_PIN4_PORTSET GPIO4_DR_SET
#define CORE_PIN5_PORTSET GPIO4_DR_SET
#define CORE_PIN6_PORTSET GPIO2_DR_SET
#define CORE_PIN7_PORTSET GPIO2_DR_SET
#define CORE_PIN8_PORTSET GPIO2_DR_SET
#define CORE_PIN9_PORTSET GPIO2_DR_SET
#define CORE_PIN10_PORTSET GPIO2_DR_SET
#define CORE_PIN11_PORTSET GPIO2_DR_SET
#define CORE_PIN12_PORTSET GPIO2_DR_SET
#define CORE_PIN13_PORTSET GPIO2_DR_SET
#define CORE_PIN14_PORTSET GPIO1_DR_SET
#define CORE_PIN15_PORTSET GPIO1_DR_SET
#define CORE_PIN16_PORTSET GPIO1_DR_SET
#define CORE_PIN17_PORTSET GPIO1_DR_SET
#define CORE_PIN18_PORTSET GPIO1_DR_SET
#define CORE_PIN19_PORTSET GPIO1_DR_SET
#define CORE_PIN20_PORTSET GPIO1_DR_SET
#define CORE_PIN21_PORTSET GPIO1_DR_SET
#define CORE_PIN22_PORTSET GPIO1_DR_SET
#define CORE_PIN23_PORTSET GPIO1_DR_SET
#define CORE_PIN24_PORTSET GPIO1_DR_SET
#define CORE_PIN25_PORTSET GPIO1_DR_SET
#define CORE_PIN26_PORTSET GPIO1_DR_SET
#define CORE_PIN27_PORTSET GPIO1_DR_SET
#define CORE_PIN28_PORTSET GPIO3_DR_SET
#define CORE_PIN29_PORTSET GPIO4_DR_SET
#define CORE_PIN30_PORTSET GPIO4_DR_SET
#define CORE_PIN31_PORTSET GPIO4_DR_SET
#define CORE_PIN32_PORTSET GPIO2_DR_SET
#define CORE_PIN33_PORTSET GPIO4_DR_SET

#define CORE_PIN0_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN1_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN2_PORTCLEAR GPIO4_DR_CLEAR
#define CORE_PIN3_PORTCLEAR GPIO4_DR_CLEAR
#define CORE_PIN4_PORTCLEAR GPIO4_DR_CLEAR
#define CORE_PIN5_PORTCLEAR GPIO4_DR_CLEAR
#define CORE_PIN6_PORTCLEAR GPIO2_DR_CLEAR
#define CORE_PIN7_PORTCLEAR GPIO2_DR_CLEAR
#define CORE_PIN8_PORTCLEAR GPIO2_DR_CLEAR
#define CORE_PIN9_PORTCLEAR GPIO2_DR_CLEAR
#define CORE_PIN10_PORTCLEAR GPIO2_DR_CLEAR
#define CORE_PIN11_PORTCLEAR GPIO2_DR_CLEAR
#define CORE_PIN12_PORTCLEAR GPIO2_DR_CLEAR
#define CORE_PIN13_PORTCLEAR GPIO2_DR_CLEAR
#define CORE_PIN14_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN15_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN16_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN17_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN18_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN19_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN20_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN21_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN22_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN23_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN24_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN25_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN26_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN27_PORTCLEAR GPIO1_DR_CLEAR
#define CORE_PIN28_PORTCLEAR GPIO3_DR_CLEAR
#define CORE_PIN29_PORTCLEAR GPIO4_DR_CLEAR
#define CORE_PIN30_PORTCLEAR GPIO4_DR_CLEAR
#define CORE_PIN31_PORTCLEAR GPIO4_DR_CLEAR
#define CORE_PIN32_PORTCLEAR GPIO2_DR_CLEAR
#define CORE_PIN33_PORTCLEAR GPIO4_DR_CLEAR

#define CORE_PIN0_DDRREG GPIO1_GDIR
#define CORE_PIN1_DDRREG GPIO1_GDIR
#define CORE_PIN2_DDRREG GPIO4_GDIR
#define CORE_PIN3_DDRREG GPIO4_GDIR
#define CORE_PIN4_DDRREG GPIO4_GDIR
#define CORE_PIN5_DDRREG GPIO4_GDIR
#define CORE_PIN6_DDRREG GPIO2_GDIR
#define CORE_PIN7_DDRREG GPIO2_GDIR
#define CORE_PIN8_DDRREG GPIO2_GDIR
#define CORE_PIN9_DDRREG GPIO2_GDIR
#define CORE_PIN10_DDRREG GPIO2_GDIR
#define CORE_PIN11_DDRREG GPIO2_GDIR
#define CORE_PIN12_DDRREG GPIO2_GDIR
#define CORE_PIN13_DDRREG GPIO2_GDIR
#define CORE_PIN14_DDRREG GPIO1_GDIR
#define CORE_PIN15_DDRREG GPIO1_GDIR
#define CORE_PIN16_DDRREG GPIO1_GDIR
#define CORE_PIN17_DDRREG GPIO1_GDIR
#define CORE_PIN18_DDRREG GPIO1_GDIR
#define CORE_PIN19_DDRREG GPIO1_GDIR
#define CORE_PIN20_DDRREG GPIO1_GDIR
#define CORE_PIN21_DDRREG GPIO1_GDIR
#define CORE_PIN22_DDRREG GPIO1_GDIR
#define CORE_PIN23_DDRREG GPIO1_GDIR
#define CORE_PIN24_DDRREG GPIO1_GDIR
#define CORE_PIN25_DDRREG GPIO1_GDIR
#define CORE_PIN26_DDRREG GPIO1_GDIR
#define CORE_PIN27_DDRREG GPIO1_GDIR
#define CORE_PIN28_DDRREG GPIO3_GDIR
#define CORE_PIN29_DDRREG GPIO4_GDIR
#define CORE_PIN30_DDRREG GPIO4_GDIR
#define CORE_PIN31_DDRREG GPIO4_GDIR
#define CORE_PIN32_DDRREG GPIO2_GDIR
#define CORE_PIN33_DDRREG GPIO4_GDIR

#define CORE_PIN0_PINREG GPIO1_PSR
#define CORE_PIN1_PINREG GPIO1_PSR
#define CORE_PIN2_PINREG GPIO4_PSR
#define CORE_PIN3_PINREG GPIO4_PSR
#define CORE_PIN4_PINREG GPIO4_PSR
#define CORE_PIN5_PINREG GPIO4_PSR
#define CORE_PIN6_PINREG GPIO2_PSR
#define CORE_PIN7_PINREG GPIO2_PSR
#define CORE_PIN8_PINREG GPIO2_PSR
#define CORE_PIN9_PINREG GPIO2_PSR
#define CORE_PIN10_PINREG GPIO2_PSR
#define CORE_PIN11_PINREG GPIO2_PSR
#define CORE_PIN12_PINREG GPIO2_PSR
#define CORE_PIN13_PINREG GPIO2_PSR
#define CORE_PIN14_PINREG GPIO1_PSR
#define CORE_PIN15_PINREG GPIO1_PSR
#define CORE_PIN16_PINREG GPIO1_PSR
#define CORE_PIN17_PINREG GPIO1_PSR
#define CORE_PIN18_PINREG GPIO1_PSR
#define CORE_PIN19_PINREG GPIO1_PSR
#define CORE_PIN20_PINREG GPIO1_PSR
#define CORE_PIN21_PINREG GPIO1_PSR
#define CORE_PIN22_PINREG GPIO1_PSR
#define CORE_PIN23_PINREG GPIO1_PSR
#define CORE_PIN24_PINREG GPIO1_PSR
#define CORE_PIN25_PINREG GPIO1_PSR
#define CORE_PIN26_PINREG GPIO1_PSR
#define CORE_PIN27_PINREG GPIO1_PSR
#define CORE_PIN28_PINREG GPIO3_PSR
#define CORE_PIN29_PINREG GPIO4_PSR
#define CORE_PIN30_PINREG GPIO4_PSR
#define CORE_PIN31_PINREG GPIO4_PSR
#define CORE_PIN32_PINREG GPIO2_PSR
#define CORE_PIN33_PINREG GPIO4_PSR

// mux config registers control which peripheral uses the pin
#define CORE_PIN0_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03
#define CORE_PIN1_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02
#define CORE_PIN2_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04
#define CORE_PIN3_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05
#define CORE_PIN4_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06
#define CORE_PIN5_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07
#define CORE_PIN6_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01
#define CORE_PIN7_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00
#define CORE_PIN8_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10
#define CORE_PIN9_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11
#define CORE_PIN10_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00
#define CORE_PIN11_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02
#define CORE_PIN12_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01
#define CORE_PIN13_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03
#define CORE_PIN14_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02
#define CORE_PIN15_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03
#define CORE_PIN16_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07
#define CORE_PIN17_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06
#define CORE_PIN18_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01
#define CORE_PIN19_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00
#define CORE_PIN20_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10
#define CORE_PIN21_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11
#define CORE_PIN22_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08
#define CORE_PIN23_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09
#define CORE_PIN24_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12
#define CORE_PIN25_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13
#define CORE_PIN26_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14
#define CORE_PIN27_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15
#define CORE_PIN28_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32
#define CORE_PIN29_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31
#define CORE_PIN30_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24
#define CORE_PIN31_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23
#define CORE_PIN32_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12
#define CORE_PIN33_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08

// pad config registers control pullup/pulldown/keeper, drive strength, etc
#define CORE_PIN0_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03
#define CORE_PIN1_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02
#define CORE_PIN2_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04
#define CORE_PIN3_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05
#define CORE_PIN4_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06
#define CORE_PIN5_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07
#define CORE_PIN6_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01
#define CORE_PIN7_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00
#define CORE_PIN8_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10
#define CORE_PIN9_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11
#define CORE_PIN10_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00
#define CORE_PIN11_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02
#define CORE_PIN12_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01
#define CORE_PIN13_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03
#define CORE_PIN14_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02
#define CORE_PIN15_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03
#define CORE_PIN16_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07
#define CORE_PIN17_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06
#define CORE_PIN18_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01
#define CORE_PIN19_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00
#define CORE_PIN20_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10
#define CORE_PIN21_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11
#define CORE_PIN22_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08
#define CORE_PIN23_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09
#define CORE_PIN24_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12
#define CORE_PIN25_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13
#define CORE_PIN26_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14
#define CORE_PIN27_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15
#define CORE_PIN28_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32
#define CORE_PIN29_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31
#define CORE_PIN30_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24
#define CORE_PIN31_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23
#define CORE_PIN32_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12
#define CORE_PIN33_PADCONFIG IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08

#define CORE_LED0_PIN 13

#define CORE_ADC0_PIN 14
#define CORE_ADC1_PIN 15
#define CORE_ADC2_PIN 16
#define CORE_ADC3_PIN 17
#define CORE_ADC4_PIN 18
#define CORE_ADC5_PIN 19
#define CORE_ADC6_PIN 20
#define CORE_ADC7_PIN 21
#define CORE_ADC8_PIN 22
#define CORE_ADC9_PIN 23

#define CORE_RXD0_PIN 0
#define CORE_TXD0_PIN 1
#define CORE_RXD1_PIN 6
#define CORE_TXD1_PIN 7
#define CORE_RXD2_PIN 15
#define CORE_TXD2_PIN 14
#define CORE_RXD3_PIN 16
#define CORE_TXD3_PIN 17
#define CORE_RXD4_PIN 21
#define CORE_TXD4_PIN 20
#define CORE_RXD5_PIN 25
#define CORE_TXD5_PIN 24
#define CORE_RXD6_PIN 28
#define CORE_TXD6_PIN 29
#define CORE_RXD7_PIN 30
#define CORE_TXD7_PIN 31

#define CORE_INT0_PIN 0
#define CORE_INT1_PIN 1
#define CORE_INT2_PIN 2
#define CORE_INT3_PIN 3
#define CORE_INT4_PIN 4
#define CORE_INT5_PIN 5
#define CORE_INT6_PIN 6
#define CORE_INT7_PIN 7
#define CORE_INT8_PIN 8
#define CORE_INT9_PIN 9
#define CORE_INT10_PIN 10
#define CORE_INT11_PIN 11
#define CORE_INT12_PIN 12
#define CORE_INT13_PIN 13
#define CORE_INT14_PIN 14
#define CORE_INT15_PIN 15
#define CORE_INT16_PIN 16
#define CORE_INT17_PIN 17
#define CORE_INT18_PIN 18
#define CORE_INT19_PIN 19
#define CORE_INT20_PIN 20
#define CORE_INT21_PIN 21
#define CORE_INT22_PIN 22
#define CORE_INT23_PIN 23
#define CORE_INT24_PIN 24
#define CORE_INT25_PIN 25
#define CORE_INT26_PIN 26
#define CORE_INT27_PIN 27
#define CORE_INT28_PIN 28
#define CORE_INT29_PIN 29
#define CORE_INT30_PIN 30
#define CORE_INT31_PIN 31
#define CORE_INT32_PIN 32
#define CORE_INT33_PIN 33
#define CORE_INT_EVERY_PIN 1

#endif // __IMXRT1052__
#endif // __IMXRT1062__


#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {

+ 0
- 89
teensy4/imxrt1052.ld View File

MEMORY
{
ITCM (rwx): ORIGIN = 0x00000000, LENGTH = 128K
DTCM (rwx): ORIGIN = 0x20000000, LENGTH = 128K
RAM (rwx): ORIGIN = 0x20200000, LENGTH = 256K
FLASH (rwx): ORIGIN = 0x60000000, LENGTH = 1536K
}

ENTRY(ImageVectorTable)

SECTIONS
{
.text.progmem : {
KEEP(*(.flashconfig))
FILL(0xFF)
. = ORIGIN(FLASH) + 0x1000;
KEEP(*(.ivt))
KEEP(*(.bootdata))
KEEP(*(.vectors))
KEEP(*(.startup))
*(.progmem*)
. = ALIGN(4);
KEEP(*(.init))
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
__init_array_start = .;
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(16);
} > FLASH

.text : {
. = . + 32; /* MPU to trap NULL pointer deref */
*(.fastrun)
*(.text*)
. = ALIGN(16);
} > ITCM AT> FLASH

.vectorsRAM (NOLOAD) : {
. = ALIGN(4);
*(.vectorsRAM*)
} > DTCM
.data : {
*(.rodata*)
*(.data*)
. = ALIGN(16);
} > DTCM AT> FLASH

.bss ALIGN(4) : {
*(.bss*)
*(COMMON)
. = ALIGN(32);
. = . + 32; /* MPU to trap stack overflow */
} > DTCM

.bss.dma (NOLOAD) : {
*(.dmabuffers)
. = ALIGN(16);
} > RAM

_stext = ADDR(.text);
_etext = ADDR(.text) + SIZEOF(.text);
_stextload = LOADADDR(.text);

_sdata = ADDR(.data);
_edata = ADDR(.data) + SIZEOF(.data);
_sdataload = LOADADDR(.data);

_estack = ORIGIN(DTCM) + LENGTH(DTCM);

_sbss = ADDR(.bss);
_ebss = ADDR(.bss) + SIZEOF(.bss);

_heap_start = ADDR(.bss.dma) + SIZEOF(.bss.dma);
_heap_end = ORIGIN(RAM) + LENGTH(RAM);

_flashimagelen = SIZEOF(.text.progmem) + SIZEOF(.text) + SIZEOF(.data);
_teensy_model_identifier = 0x23;

.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }

}

+ 0
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teensy4/interrupt.c View File

irq_anyport(&GPIO9_DR, isr_table_gpio4); irq_anyport(&GPIO9_DR, isr_table_gpio4);
} }


#elif defined(__IMXRT1052__)

FASTRUN
void irq_anyport(volatile uint32_t *gpio, voidFuncPtr *table)
{
uint32_t status = gpio[ISR] & gpio[IMR];
gpio[ISR] = status;
while (status) {
uint32_t index = __builtin_ctz(status);
table[index]();
status = status & ~(1 << index);
//status = status & (status - 1);
}
}

FASTRUN
void irq_gpio1(void)
{
irq_anyport(&GPIO1_DR, isr_table_gpio1);
}

FASTRUN
void irq_gpio2(void)
{
irq_anyport(&GPIO2_DR, isr_table_gpio2);
}

FASTRUN
void irq_gpio3(void)
{
irq_anyport(&GPIO3_DR, isr_table_gpio3);
}

FASTRUN
void irq_gpio4(void)
{
irq_anyport(&GPIO4_DR, isr_table_gpio4);
}

#endif #endif


void attachInterrupt(uint8_t pin, void (*function)(void), int mode) void attachInterrupt(uint8_t pin, void (*function)(void), int mode)
attachInterruptVector(IRQ_GPIO6789, &irq_gpio6789); attachInterruptVector(IRQ_GPIO6789, &irq_gpio6789);
NVIC_ENABLE_IRQ(IRQ_GPIO6789); NVIC_ENABLE_IRQ(IRQ_GPIO6789);


#elif defined(__IMXRT1052__)
switch((uint32_t)gpio) {
case (uint32_t)&GPIO1_DR:
table = isr_table_gpio1;
attachInterruptVector(IRQ_GPIO1_0_15, &irq_gpio1);
attachInterruptVector(IRQ_GPIO1_16_31, &irq_gpio1);
NVIC_ENABLE_IRQ(IRQ_GPIO1_0_15);
NVIC_ENABLE_IRQ(IRQ_GPIO1_16_31);
break;
case (uint32_t)&GPIO2_DR:
table = isr_table_gpio2;
attachInterruptVector(IRQ_GPIO2_0_15, &irq_gpio2);
attachInterruptVector(IRQ_GPIO2_16_31, &irq_gpio2);
NVIC_ENABLE_IRQ(IRQ_GPIO2_0_15);
NVIC_ENABLE_IRQ(IRQ_GPIO2_16_31);
break;
case (uint32_t)&GPIO3_DR:
table = isr_table_gpio3;
attachInterruptVector(IRQ_GPIO3_0_15, &irq_gpio3);
attachInterruptVector(IRQ_GPIO3_16_31, &irq_gpio3);
NVIC_ENABLE_IRQ(IRQ_GPIO3_0_15);
NVIC_ENABLE_IRQ(IRQ_GPIO3_16_31);
break;
case (uint32_t)&GPIO4_DR:
table = isr_table_gpio4;
attachInterruptVector(IRQ_GPIO4_0_15, &irq_gpio4);
attachInterruptVector(IRQ_GPIO4_16_31, &irq_gpio4);
NVIC_ENABLE_IRQ(IRQ_GPIO4_0_15);
NVIC_ENABLE_IRQ(IRQ_GPIO4_16_31);
break;
default:
return;
}
#endif #endif


uint32_t icr; uint32_t icr;

+ 1
- 1
teensy4/pins_arduino.h View File

#define NOT_AN_INTERRUPT -1 #define NOT_AN_INTERRUPT -1




#if defined(__IMXRT1052__) || defined(__IMXRT1062__)
#if defined(__IMXRT1062__)
#define analogInputToDigitalPin(p) (((p) <= 9) ? (p) + 14 : (((p) >= 14 && (p) <= 27) ? (p) : -1)) #define analogInputToDigitalPin(p) (((p) <= 9) ? (p) + 14 : (((p) >= 14 && (p) <= 27) ? (p) : -1))
#define digitalPinHasPWM(p) ((p) <= 15 || (p) == 18 || (p) == 19 || ((p) >= 22 && (p) <= 25) || ((p) >= 28 && (p) <= 31) || (p) == 33) #define digitalPinHasPWM(p) ((p) <= 15 || (p) == 18 || (p) == 19 || ((p) >= 22 && (p) <= 25) || ((p) >= 28 && (p) <= 31) || (p) == 33)
#define digitalPinToInterrupt(p) ((p) < NUM_DIGITAL_PINS ? (p) : -1) #define digitalPinToInterrupt(p) ((p) < NUM_DIGITAL_PINS ? (p) : -1)

+ 1
- 47
teensy4/pwm.c View File

{1, M(1, 2), 1, 1}, // FlexPWM1_2_A 39 // SD_B0_04 {1, M(1, 2), 1, 1}, // FlexPWM1_2_A 39 // SD_B0_04
}; };


#elif defined(__IMXRT1052__)

const struct pwm_pin_info_struct pwm_pin_info[] = {
{1, M(1, 1), 0, 4}, // FlexPWM1_1_X 0 // AD_B0_03
{1, M(1, 0), 0, 4}, // FlexPWM1_0_X 1 // AD_B0_02
{1, M(4, 2), 1, 1}, // FlexPWM4_2_A 2 // EMC_04
{1, M(4, 2), 2, 1}, // FlexPWM4_2_B 3 // EMC_05
{1, M(2, 0), 1, 1}, // FlexPWM2_0_A 4 // EMC_06
{1, M(2, 0), 2, 1}, // FlexPWM2_0_B 5 // EMC_07
{1, M(1, 3), 2, 6}, // FlexPWM1_3_B 6 // B1_01
{1, M(1, 3), 1, 6}, // FlexPWM1_3_A 7 // B1_00
{1, M(2, 2), 1, 2}, // FlexPWM2_2_A 8 // B0_10
{1, M(2, 2), 2, 2}, // FlexPWM2_2_B 9 // B0_11
{2, M(1, 0), 0, 1}, // QuadTimer1_0 10 // B0_00
{2, M(1, 2), 0, 1}, // QuadTimer1_2 11 // B0_02
{2, M(1, 1), 0, 1}, // QuadTimer1_1 12 // B0_01
{2, M(2, 0), 0, 1}, // QuadTimer2_0 13 // B0_03
{2, M(3, 2), 0, 1}, // QuadTimer3_2 14 // AD_B1_02
{2, M(3, 3), 0, 1}, // QuadTimer3_3 15 // AD_B1_03
{0, M(1, 0), 0, 0},
{0, M(1, 0), 0, 0},
{2, M(3, 1), 0, 1}, // QuadTimer3_1 18 // AD_B1_01
{2, M(3, 0), 0, 1}, // QuadTimer3_0 19 // AD_B1_00
{0, M(1, 0), 0, 0},
{0, M(1, 0), 0, 0},
{1, M(4, 0), 1, 1}, // FlexPWM4_0_A 22 // AD_B1_08
{1, M(4, 1), 1, 1}, // FlexPWM4_1_A 23 // AD_B1_09
{1, M(1, 2), 0, 4}, // FlexPWM1_2_X 24 // AD_B0_12
{1, M(1, 3), 0, 4}, // FlexPWM1_3_X 25 // AD_B0_13
{0, M(1, 0), 0, 0},
{0, M(1, 0), 0, 0},
{1, M(3, 1), 2, 1}, // FlexPWM3_1_B 28 // EMC_32
{1, M(3, 1), 1, 1}, // FlexPWM3_1_A 29 // EMC_31
{1, M(1, 0), 2, 1}, // FlexPWM1_0_B 30 // EMC_24
{1, M(1, 0), 1, 1}, // FlexPWM1_0_A 31 // EMC_23
{0, M(1, 0), 0, 0},
{1, M(2, 1), 1, 1}, // FlexPWM2_1_A 33 // EMC_08
{1, M(2, 0), 2, 1}, // FlexPWM2_0_B 33 // EMC_07
{1, M(1, 1), 2, 1}, // FlexPWM1_1_B 34 // SD_B0_03
{1, M(1, 1), 1, 1}, // FlexPWM1_1_A 35 // SD_B0_02
{1, M(1, 0), 2, 1}, // FlexPWM1_0_B 36 // SD_B0_01
{1, M(1, 0), 1, 1}, // FlexPWM1_0_A 37 // SD_B0_00
{1, M(1, 2), 2, 1}, // FlexPWM1_2_B 38 // SD_B0_05
{1, M(1, 2), 1, 1}, // FlexPWM1_2_A 39 // SD_B0_04
};

#endif // __IMXRT1052__
#endif // __IMXRT1062__


void flexpwmWrite(IMXRT_FLEXPWM_t *p, unsigned int submodule, uint8_t channel, uint16_t val) void flexpwmWrite(IMXRT_FLEXPWM_t *p, unsigned int submodule, uint8_t channel, uint16_t val)
{ {

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