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teensy-cores
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8 Commits (179953284a278c9d6bb3078ab3859ffb4bc5f09e)

Author SHA1 Message Date
  PaulStoffregen ea4252feb8 Add internal analog channels on Teensy-LC 9 years ago
  PaulStoffregen af89f7072e Add support for Teensy-LC DAC 9 years ago
  PaulStoffregen 9b8d74c089 Initial support for Teensy-LC 9 years ago
  PaulStoffregen 663e4fddec Add support for 2, 4, 8, 16MHz (Duff) 10 years ago
  PaulStoffregen 7bee55654c Support more CPU and bus frequencies 10 years ago
  Frank Bösing fdcaeb932e Stripped to 144MHz only for Paul 10 years ago
  Frank Bösing bbd726f690 Update to 168MHz, 42 MHZ Bus, 28MHz Flash 10 years ago
  Frank Bösing 856a79b321 Modified for additional 120MHz Core-Clock 10 years ago
  PaulStoffregen a781e92f77 Fix analogRead(39) (Vref) on Teensy 3.1 10 years ago
  PaulStoffregen 729c211500 Support for Teensy 3.1 11 years ago
  PaulStoffregen 5cecdee933 Initial commit, version 1.17-rc1 11 years ago