teensy-cores

Träd: 18edc30616

Upphovsman	SHA1	Meddelande	Datum
PaulStoffregen	3ad57aacac	Revert "teensy3: usb_serial: Extract core usb_serial_port" This reverts commit `6fb4c61b45`.	4 år sedan
Geert Uytterhoeven	6fb4c61b45	teensy3: usb_serial: Extract core usb_serial_port Extract core USB serial functionality in a new usb_serial_port C class, to allow creating multiple USB serial instances without duplicating all code. The original API is retained by creating static inline functions and preprocessor macros using the old names, which are wrappers around the new usb_serial_port functions and data members. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	4 år sedan
Frank Bösing	11bd76352d	FCPU 256MHz	6 år sedan
PaulStoffregen	7099935c0e	Update open source license info	7 år sedan
Frank	9febfa653b	Fix: write returns zero (#202 ) https://forum.pjrc.com/threads/40893-Incorrect-return-for-Serial-write()-on-Teensy-3-6?p=127732#post127732 I'm not sure if this fix has some side-effects - how will other functions react when it does not return zero anymore ?	8 år sedan
PaulStoffregen	6040145aac	More K66 overclocking options	8 år sedan
PaulStoffregen	c364608480	Even more defs	8 år sedan
PaulStoffregen	1225f43fd0	Report Serial bool operator true only after 25 ms Sometimes the PC or Mac drivers are not actually ready to begin receiving data immediately after they cause DTR or RTS to assert. This delay allows the PC to become ready before we tell sketches the Serial device is true (ready).	9 år sedan
PaulStoffregen	caa5312fbc	Opps, fix compile for slow speeds	9 år sedan
PaulStoffregen	8bdc442fdf	Add TODO comment in USB Serial	10 år sedan
PaulStoffregen	9c1e41e70e	Change room() to writeBufferFree() https://groups.google.com/a/arduino.cc/d/msg/developers/ls3hkviFYM4/XWT2LbfzNcgJ	10 år sedan
PaulStoffregen	71160e91c2	Add Serial.room()	10 år sedan
PaulStoffregen	d783be33c1	Clean up trailing whitespace	10 år sedan
PaulStoffregen	7bee55654c	Support more CPU and bus frequencies	10 år sedan
Frank Bösing	6942a12ff4	Stripped to overclock add. 144MHz only for Paul	10 år sedan
Frank Bösing	bbd726f690	Update to 168MHz, 42 MHZ Bus, 28MHz Flash	10 år sedan
Frank Bösing	856a79b321	Modified for additional 120MHz Core-Clock	10 år sedan
PaulStoffregen	5cecdee933	Initial commit, version 1.17-rc1	11 år sedan

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