Drop HSRUN across Ser# read with interrupts off

https://forum.pjrc.com/threads/34808-K66-Beta-Test?p=116690&viewfull=1#post116690

Results in valid serial # presented to USB host when T_3.6 is in HSRUN mode.

Fix PWM and Analog Pin counts om T3.5 and T3.6

Recent additions did not update these counts.

Seperated T3.5 from T3.6 as PWM and Analog counts are different

T35 use sdcard pins

Add A23 and A24 for T3.5 and T3.6 board

Fix spi0 dma for t3 5

Fix Serial6 for Teensy 3.5

Needed to add new Define for clock gate

Plus defines to use the new clock gate, plus correct case name for the
serial6 isr to match what is in system isr table

I added pins  49 and 50 as analog pins A23 and A24.  I still left in the
special casing for pins 44 and 45 being used for Temp and analog
reference

With the new beta boards, for those users who don't need an SDCard for
their project, it would be great to allow them to use the 6 IO pins
associated with the SDCARD for other purposes.  This would probably
require a cheap adapter, but these are nice signals to be able to be
used.  They include:

SPI1: SCK, MISO, MOSI, CS0-2
Serail2: TX/RX
Serial4: TX/RX
I2C1: SCL/SDA

This change adds support for GPIO, SPI, Serial2 and Serial4

When concat is same string to string, use memcpy

https://forum.pjrc.com/threads/35688-Something-wrong-with-Adding-a-String-to-itself!?p=111109#post111109

Enable Uart 2 stop bit capabilities

The T-LC and the new beta boards T3.6 and soon T3.5 hardware uarts have
ability to turn on 2 stop bits.  So enabled on these boards.

Beta Board names Change

Ser2 ser4 fixes

Was using UART2, should be UART3

On T3.2 if you do something like:
Serial2.setTX(31);
Serial2.setRX(26);
Serial2.begin(.9600);
...
Serial2.end();

It will on the end call will always reconfigure pins 9 and 10 to be
digital pins MUX = 1

Add serialEvent6 to yield

fixes #159

T3 5 beta serial6

missed pin 26 in SPIFIFO

Make update of these flags be hopefully interrupt safe

This is a WIP,  But I have now been able to create Serial6 on T3.4 beta,
and so far have tested Send/Receive basic stuff at 115200 and have tried
at several CPU speeds in MHZ (192, 216, 180, 120, 96)

T T3.4 T3.5 SPI2 support

trigger mode enable cmp register def