teensy-cores

Auteur	SHA1	Message	Date
PaulStoffregen	aee29bc892	Fix compiler warnings	il y a 5 ans
Frank	2a8b5d066e	rmv warning "implicit declaration of function 'delay'"	il y a 5 ans
PaulStoffregen	a1ff3e9256	Fix USB serial issues printing before device ready	il y a 5 ans
PaulStoffregen	7153086e77	Don't disturb pin 13 (leftover debugging code)	il y a 5 ans
PaulStoffregen	addd88d076	basic usb serial on imxrt	il y a 6 ans
PaulStoffregen	e687673ddf	First commit, Teensy4 work-in-progress	il y a 6 ans
Frank Bösing	11bd76352d	FCPU 256MHz	il y a 6 ans
PaulStoffregen	7099935c0e	Update open source license info	il y a 7 ans
Frank	9febfa653b	Fix: write returns zero (#202 ) https://forum.pjrc.com/threads/40893-Incorrect-return-for-Serial-write()-on-Teensy-3-6?p=127732#post127732 I'm not sure if this fix has some side-effects - how will other functions react when it does not return zero anymore ?	il y a 8 ans
PaulStoffregen	6040145aac	More K66 overclocking options	il y a 8 ans
PaulStoffregen	c364608480	Even more defs	il y a 8 ans
PaulStoffregen	1225f43fd0	Report Serial bool operator true only after 25 ms Sometimes the PC or Mac drivers are not actually ready to begin receiving data immediately after they cause DTR or RTS to assert. This delay allows the PC to become ready before we tell sketches the Serial device is true (ready).	il y a 9 ans
PaulStoffregen	caa5312fbc	Opps, fix compile for slow speeds	il y a 9 ans
PaulStoffregen	8bdc442fdf	Add TODO comment in USB Serial	il y a 10 ans
PaulStoffregen	9c1e41e70e	Change room() to writeBufferFree() https://groups.google.com/a/arduino.cc/d/msg/developers/ls3hkviFYM4/XWT2LbfzNcgJ	il y a 10 ans
PaulStoffregen	71160e91c2	Add Serial.room()	il y a 10 ans
PaulStoffregen	d783be33c1	Clean up trailing whitespace	il y a 10 ans
PaulStoffregen	7bee55654c	Support more CPU and bus frequencies	il y a 10 ans
Frank Bösing	6942a12ff4	Stripped to overclock add. 144MHz only for Paul	il y a 10 ans
Frank Bösing	bbd726f690	Update to 168MHz, 42 MHZ Bus, 28MHz Flash	il y a 10 ans
Frank Bösing	856a79b321	Modified for additional 120MHz Core-Clock	il y a 10 ans
PaulStoffregen	5cecdee933	Initial commit, version 1.17-rc1	il y a 11 ans

6 Révisions (5c7cd9c57a348efbdd28394db2c2de14a6855927)