visus
/
teensy-cores
Watch 1
Star 0
Fork 0
Code Issues 0 Pull Requests 0 Releases 0 Wiki Activity
936 Commits
1 Branch
Tree: bc2762a426
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from 'bc2762a426'
${ noResults }
Commit Graph

28 Commits (bc2762a426f59ae04105e50a95b268678ea67e59)

Author SHA1 Message Date
  Frank Bösing 7d43e33fbe cosmetic changes 6 years ago
  Frank Bösing 72d7b11fb6 F_BUS 128MHz analog.c 6 years ago
  PaulStoffregen 27cdeb1cb9 Teensy LC does not support saturate instruction 6 years ago
  shkshk90 edc3f0c12b
Add saturate instruction 6 years ago
  shkshk90 b90f36c8b7
Update analog.c 6 years ago
  PaulStoffregen 392c93cb87 Fix analogReadAveraging with ADC1 7 years ago
  PaulStoffregen 7099935c0e Update open source license info 7 years ago
  Tilo Nitzsche 56b2af9f9a analogWrite() can fail with LTO. Fix casts with undefined behavior. 7 years ago
  PaulStoffregen 2185bdc936 Fix analogReadResolution ADC1 cal 8 years ago
  PaulStoffregen 3b96d28851 Fix pin number comments 8 years ago
  PaulStoffregen 28d7ba477e Use analog pin to channel tables (faster) 8 years ago
  Kurt Eckhardt 8fdabf68ed One less compare 8 years ago
  Kurt Eckhardt cf6bf5863a Add A23 and A24 for T3.5 and T3.6 board 8 years ago
  PaulStoffregen de0677a6e0 Enable VREF on K66 8 years ago
  Frank Bösing 8752969dbb Add missing F_BUS 8 years ago
  PaulStoffregen 6856d4eedc Fix analogRead on K66 8 years ago
  PaulStoffregen 6040145aac More K66 overclocking options 8 years ago
  PaulStoffregen e0dd146824 More defs 8 years ago
  PaulStoffregen aa212b61e0 Defs for MK66FX1M0 9 years ago
  PaulStoffregen 1e49af2dd2 Add register definitions 9 years ago
  PaulStoffregen ea4252feb8 Add internal analog channels on Teensy-LC 9 years ago
  PaulStoffregen af89f7072e Add support for Teensy-LC DAC 9 years ago
  PaulStoffregen 9b8d74c089 Initial support for Teensy-LC 9 years ago
  PaulStoffregen 663e4fddec Add support for 2, 4, 8, 16MHz (Duff) 10 years ago
  PaulStoffregen 7bee55654c Support more CPU and bus frequencies 10 years ago
  Frank Bösing fdcaeb932e Stripped to 144MHz only for Paul 10 years ago
  Frank Bösing bbd726f690 Update to 168MHz, 42 MHZ Bus, 28MHz Flash 10 years ago
  Frank Bösing 856a79b321 Modified for additional 120MHz Core-Clock 10 years ago
  PaulStoffregen a781e92f77 Fix analogRead(39) (Vref) on Teensy 3.1 10 years ago
  PaulStoffregen 729c211500 Support for Teensy 3.1 11 years ago
  PaulStoffregen 5cecdee933 Initial commit, version 1.17-rc1 11 years ago