Needed to add new Define for clock gate

Plus defines to use the new clock gate, plus correct case name for the
serial6 isr to match what is in system isr table

The T-LC and the new beta boards T3.6 and soon T3.5 hardware uarts have
ability to turn on 2 stop bits.  So enabled on these boards.

This is a WIP,  But I have now been able to create Serial6 on T3.4 beta,
and so far have tested Send/Receive basic stuff at 115200 and have tried
at several CPU speeds in MHZ (192, 216, 180, 120, 96)

On Serial 3 this addition is for all 3.x.  Before it was ifdefed to only
do work on Teensy_LC as there is only one valid TX pin.  But we now pass
in open drain as an option so this code should allow you to not turn it
on/off on Serial3 on all of these boards

and on Serial4 and Serial5 on the new boards.

https://forum.pjrc.com/threads/29446-Teensy-Hardware-Flow-Control-RTS-CTS?p=80425#post80425

https://forum.pjrc.com/threads/27093-Fix-for-9-bit-serial-receive-bug

https://groups.google.com/a/arduino.cc/d/msg/developers/ls3hkviFYM4/XWT2LbfzNcgJ

http://forum.pjrc.com/threads/26064-Large-transfers-over-serial-on-Teensy-3-1
http://forum.arduino.cc/index.php/topic,165574.0.html