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teensy-cores/teensy3/mk20dx128.c

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  1. /* Teensyduino Core Library

  2.  * http://www.pjrc.com/teensy/

  3.  * Copyright (c) 2013 PJRC.COM, LLC.

  4.  *

  5.  * Permission is hereby granted, free of charge, to any person obtaining

  6.  * a copy of this software and associated documentation files (the

  7.  * "Software"), to deal in the Software without restriction, including

  8.  * without limitation the rights to use, copy, modify, merge, publish,

  9.  * distribute, sublicense, and/or sell copies of the Software, and to

  10.  * permit persons to whom the Software is furnished to do so, subject to

  11.  * the following conditions:

  12.  *

  13.  * 1. The above copyright notice and this permission notice shall be 

  14.  * included in all copies or substantial portions of the Software.

  15.  *

  16.  * 2. If the Software is incorporated into a build system that allows 

  17.  * selection among a list of target devices, then similar target

  18.  * devices manufactured by PJRC.COM must be included in the list of

  19.  * target devices and selectable in the same manner.

  20.  *

  21.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

  22.  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

  23.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

  24.  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS

  25.  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN

  26.  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

  27.  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

  28.  * SOFTWARE.

  29.  */

  30. 

  31. #include "kinetis.h"

  32. #include "core_pins.h" // testing only

  33. #include "ser_print.h" // testing only

  34. 

  35. extern unsigned long _stext;

  36. extern unsigned long _etext;

  37. extern unsigned long _sdata;

  38. extern unsigned long _edata;

  39. extern unsigned long _sbss;

  40. extern unsigned long _ebss;

  41. extern unsigned long _estack;

  42. //extern void __init_array_start(void);

  43. //extern void __init_array_end(void);

  44. 

  45. 

  46. 

  47. extern int main (void);

  48. void ResetHandler(void);

  49. void _init_Teensyduino_internal_(void);

  50. void __libc_init_array(void);

  51. 

  52. 

  53. void fault_isr(void)

  54. {

  55. #if 0

  56. 	uint32_t addr;

  57. 

  58. 	SIM_SCGC4 |= 0x00000400;

  59. 	UART0_BDH = 0;

  60. 	UART0_BDL = 26; // 115200 at 48 MHz

  61. 	UART0_C2 = UART_C2_TE;

  62. 	PORTB_PCR17 = PORT_PCR_MUX(3);

  63. 	ser_print("\nfault: \n??: ");

  64.         asm("ldr %0, [sp, #52]" : "=r" (addr) ::);

  65.         ser_print_hex32(addr);

  66.         ser_print("\n??: ");

  67.         asm("ldr %0, [sp, #48]" : "=r" (addr) ::);

  68.         ser_print_hex32(addr);

  69.         ser_print("\n??: ");

  70.         asm("ldr %0, [sp, #44]" : "=r" (addr) ::);

  71.         ser_print_hex32(addr);

  72.         ser_print("\npsr:");

  73.         asm("ldr %0, [sp, #40]" : "=r" (addr) ::);

  74.         ser_print_hex32(addr);

  75.         ser_print("\nadr:");

  76.         asm("ldr %0, [sp, #36]" : "=r" (addr) ::);

  77.         ser_print_hex32(addr);

  78.         ser_print("\nlr: ");

  79.         asm("ldr %0, [sp, #32]" : "=r" (addr) ::);

  80.         ser_print_hex32(addr);

  81.         ser_print("\nr12:");

  82.         asm("ldr %0, [sp, #28]" : "=r" (addr) ::);

  83.         ser_print_hex32(addr);

  84.         ser_print("\nr3: ");

  85.         asm("ldr %0, [sp, #24]" : "=r" (addr) ::);

  86.         ser_print_hex32(addr);

  87.         ser_print("\nr2: ");

  88.         asm("ldr %0, [sp, #20]" : "=r" (addr) ::);

  89.         ser_print_hex32(addr);

  90.         ser_print("\nr1: ");

  91.         asm("ldr %0, [sp, #16]" : "=r" (addr) ::);

  92.         ser_print_hex32(addr);

  93.         ser_print("\nr0: ");

  94.         asm("ldr %0, [sp, #12]" : "=r" (addr) ::);

  95.         ser_print_hex32(addr);

  96.         ser_print("\nr4: ");

  97.         asm("ldr %0, [sp, #8]" : "=r" (addr) ::);

  98.         ser_print_hex32(addr);

  99.         ser_print("\nlr: ");

  100.         asm("ldr %0, [sp, #4]" : "=r" (addr) ::);

  101.         ser_print_hex32(addr);

  102.         ser_print("\n");

  103.         asm("ldr %0, [sp, #0]" : "=r" (addr) ::);

  104. #endif

  105. 	while (1) {

  106. 		// keep polling some communication while in fault

  107. 		// mode, so we don't completely die.

  108. 		if (SIM_SCGC4 & SIM_SCGC4_USBOTG) usb_isr();

  109. 		if (SIM_SCGC4 & SIM_SCGC4_UART0) uart0_status_isr();

  110. 		if (SIM_SCGC4 & SIM_SCGC4_UART1) uart1_status_isr();

  111. 		if (SIM_SCGC4 & SIM_SCGC4_UART2) uart2_status_isr();

  112. 	}

  113. }

  114. 

  115. void unused_isr(void)

  116. {

  117. 	fault_isr();

  118. }

  119. 

  120. extern volatile uint32_t systick_millis_count;

  121. void systick_default_isr(void)

  122. {

  123. 	systick_millis_count++;

  124. }

  125. 

  126. void nmi_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  127. void hard_fault_isr(void)	__attribute__ ((weak, alias("fault_isr")));

  128. void memmanage_fault_isr(void)	__attribute__ ((weak, alias("fault_isr")));

  129. void bus_fault_isr(void)	__attribute__ ((weak, alias("fault_isr")));

  130. void usage_fault_isr(void)	__attribute__ ((weak, alias("fault_isr")));

  131. void svcall_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  132. void debugmonitor_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  133. void pendablesrvreq_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  134. void systick_isr(void)		__attribute__ ((weak, alias("systick_default_isr")));

  135. 

  136. void dma_ch0_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  137. void dma_ch1_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  138. void dma_ch2_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  139. void dma_ch3_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  140. void dma_ch4_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  141. void dma_ch5_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  142. void dma_ch6_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  143. void dma_ch7_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  144. void dma_ch8_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  145. void dma_ch9_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  146. void dma_ch10_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  147. void dma_ch11_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  148. void dma_ch12_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  149. void dma_ch13_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  150. void dma_ch14_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  151. void dma_ch15_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  152. void dma_error_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  153. void mcm_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  154. void randnum_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  155. void flash_cmd_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  156. void flash_error_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  157. void low_voltage_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  158. void wakeup_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  159. void watchdog_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  160. void i2c0_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  161. void i2c1_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  162. void i2c2_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  163. void i2c3_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  164. void spi0_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  165. void spi1_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  166. void spi2_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  167. void sdhc_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  168. void enet_timer_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  169. void enet_tx_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  170. void enet_rx_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  171. void enet_error_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  172. void can0_message_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  173. void can0_bus_off_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  174. void can0_error_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  175. void can0_tx_warn_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  176. void can0_rx_warn_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  177. void can0_wakeup_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  178. void can1_message_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  179. void can1_bus_off_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  180. void can1_error_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  181. void can1_tx_warn_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  182. void can1_rx_warn_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  183. void can1_wakeup_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  184. void i2s0_tx_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  185. void i2s0_rx_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  186. void i2s0_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  187. void uart0_lon_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  188. void uart0_status_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  189. void uart0_error_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  190. void uart1_status_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  191. void uart1_error_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  192. void uart2_status_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  193. void uart2_error_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  194. void uart3_status_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  195. void uart3_error_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  196. void uart4_status_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  197. void uart4_error_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  198. void uart5_status_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  199. void uart5_error_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  200. void lpuart0_status_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  201. void adc0_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  202. void adc1_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  203. void cmp0_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  204. void cmp1_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  205. void cmp2_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  206. void cmp3_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  207. void ftm0_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  208. void ftm1_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  209. void ftm2_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  210. void ftm3_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  211. void tpm0_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  212. void tpm1_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  213. void tpm2_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  214. void cmt_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  215. void rtc_alarm_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  216. void rtc_seconds_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  217. void pit_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  218. void pit0_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  219. void pit1_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  220. void pit2_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  221. void pit3_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  222. void pdb_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  223. void usb_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  224. void usb_charge_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  225. void usbhs_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  226. void usbhs_phy_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  227. void dac0_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  228. void dac1_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  229. void tsi0_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  230. void mcg_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  231. void lptmr_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  232. void porta_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  233. void portb_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  234. void portc_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  235. void portd_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  236. void porte_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  237. void portcd_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  238. void software_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  239. 

  240. #if defined(__MK20DX128__)

  241. __attribute__ ((section(".dmabuffers"), used, aligned(256)))

  242. #elif defined(__MK20DX256__)

  243. __attribute__ ((section(".dmabuffers"), used, aligned(512)))

  244. #elif defined(__MKL26Z64__)

  245. __attribute__ ((section(".dmabuffers"), used, aligned(256)))

  246. #elif defined(__MK66FX1M0__)

  247. __attribute__ ((section(".dmabuffers"), used, aligned(512)))

  248. #endif

  249. void (* _VectorsRam[NVIC_NUM_INTERRUPTS+16])(void);

  250. 

  251. __attribute__ ((section(".vectors"), used))

  252. void (* const _VectorsFlash[NVIC_NUM_INTERRUPTS+16])(void) =

  253. {

  254. 	(void (*)(void))((unsigned long)&_estack),	//  0 ARM: Initial Stack Pointer

  255. 	ResetHandler,					//  1 ARM: Initial Program Counter

  256. 	nmi_isr,					//  2 ARM: Non-maskable Interrupt (NMI)

  257. 	hard_fault_isr,					//  3 ARM: Hard Fault

  258. 	memmanage_fault_isr,				//  4 ARM: MemManage Fault

  259. 	bus_fault_isr,					//  5 ARM: Bus Fault

  260. 	usage_fault_isr,				//  6 ARM: Usage Fault

  261. 	fault_isr,					//  7 --

  262. 	fault_isr,					//  8 --

  263. 	fault_isr,					//  9 --

  264. 	fault_isr,					// 10 --

  265. 	svcall_isr,					// 11 ARM: Supervisor call (SVCall)

  266. 	debugmonitor_isr,				// 12 ARM: Debug Monitor

  267. 	fault_isr,					// 13 --

  268. 	pendablesrvreq_isr,				// 14 ARM: Pendable req serv(PendableSrvReq)

  269. 	systick_isr,					// 15 ARM: System tick timer (SysTick)

  270. #if defined(__MK20DX128__)

  271. 	dma_ch0_isr,					// 16 DMA channel 0 transfer complete

  272. 	dma_ch1_isr,					// 17 DMA channel 1 transfer complete

  273. 	dma_ch2_isr,					// 18 DMA channel 2 transfer complete

  274. 	dma_ch3_isr,					// 19 DMA channel 3 transfer complete

  275. 	dma_error_isr,					// 20 DMA error interrupt channel

  276. 	unused_isr,					// 21 DMA --

  277. 	flash_cmd_isr,					// 22 Flash Memory Command complete

  278. 	flash_error_isr,				// 23 Flash Read collision

  279. 	low_voltage_isr,				// 24 Low-voltage detect/warning

  280. 	wakeup_isr,					// 25 Low Leakage Wakeup

  281. 	watchdog_isr,					// 26 Both EWM and WDOG interrupt

  282. 	i2c0_isr,					// 27 I2C0

  283. 	spi0_isr,					// 28 SPI0

  284. 	i2s0_tx_isr,					// 29 I2S0 Transmit

  285. 	i2s0_rx_isr,					// 30 I2S0 Receive

  286. 	uart0_lon_isr,					// 31 UART0 CEA709.1-B (LON) status

  287. 	uart0_status_isr,				// 32 UART0 status

  288. 	uart0_error_isr,				// 33 UART0 error

  289. 	uart1_status_isr,				// 34 UART1 status

  290. 	uart1_error_isr,				// 35 UART1 error

  291. 	uart2_status_isr,				// 36 UART2 status

  292. 	uart2_error_isr,				// 37 UART2 error

  293. 	adc0_isr,					// 38 ADC0

  294. 	cmp0_isr,					// 39 CMP0

  295. 	cmp1_isr,					// 40 CMP1

  296. 	ftm0_isr,					// 41 FTM0

  297. 	ftm1_isr,					// 42 FTM1

  298. 	cmt_isr,					// 43 CMT

  299. 	rtc_alarm_isr,					// 44 RTC Alarm interrupt

  300. 	rtc_seconds_isr,				// 45 RTC Seconds interrupt

  301. 	pit0_isr,					// 46 PIT Channel 0

  302. 	pit1_isr,					// 47 PIT Channel 1

  303. 	pit2_isr,					// 48 PIT Channel 2

  304. 	pit3_isr,					// 49 PIT Channel 3

  305. 	pdb_isr,					// 50 PDB Programmable Delay Block

  306. 	usb_isr,					// 51 USB OTG

  307. 	usb_charge_isr,					// 52 USB Charger Detect

  308. 	tsi0_isr,					// 53 TSI0

  309. 	mcg_isr,					// 54 MCG

  310. 	lptmr_isr,					// 55 Low Power Timer

  311. 	porta_isr,					// 56 Pin detect (Port A)

  312. 	portb_isr,					// 57 Pin detect (Port B)

  313. 	portc_isr,					// 58 Pin detect (Port C)

  314. 	portd_isr,					// 59 Pin detect (Port D)

  315. 	porte_isr,					// 60 Pin detect (Port E)

  316. 	software_isr,					// 61 Software interrupt

  317. #elif defined(__MK20DX256__)

  318. 	dma_ch0_isr,					// 16 DMA channel 0 transfer complete

  319. 	dma_ch1_isr,					// 17 DMA channel 1 transfer complete

  320. 	dma_ch2_isr,					// 18 DMA channel 2 transfer complete

  321. 	dma_ch3_isr,					// 19 DMA channel 3 transfer complete

  322. 	dma_ch4_isr,					// 20 DMA channel 4 transfer complete

  323. 	dma_ch5_isr,					// 21 DMA channel 5 transfer complete

  324. 	dma_ch6_isr,					// 22 DMA channel 6 transfer complete

  325. 	dma_ch7_isr,					// 23 DMA channel 7 transfer complete

  326. 	dma_ch8_isr,					// 24 DMA channel 8 transfer complete

  327. 	dma_ch9_isr,					// 25 DMA channel 9 transfer complete

  328. 	dma_ch10_isr,					// 26 DMA channel 10 transfer complete

  329. 	dma_ch11_isr,					// 27 DMA channel 11 transfer complete

  330. 	dma_ch12_isr,					// 28 DMA channel 12 transfer complete

  331. 	dma_ch13_isr,					// 29 DMA channel 13 transfer complete

  332. 	dma_ch14_isr,					// 30 DMA channel 14 transfer complete

  333. 	dma_ch15_isr,					// 31 DMA channel 15 transfer complete

  334. 	dma_error_isr,					// 32 DMA error interrupt channel

  335. 	unused_isr,					// 33 --

  336. 	flash_cmd_isr,					// 34 Flash Memory Command complete

  337. 	flash_error_isr,				// 35 Flash Read collision

  338. 	low_voltage_isr,				// 36 Low-voltage detect/warning

  339. 	wakeup_isr,					// 37 Low Leakage Wakeup

  340. 	watchdog_isr,					// 38 Both EWM and WDOG interrupt

  341. 	unused_isr,					// 39 --

  342. 	i2c0_isr,					// 40 I2C0

  343. 	i2c1_isr,					// 41 I2C1

  344. 	spi0_isr,					// 42 SPI0

  345. 	spi1_isr,					// 43 SPI1

  346. 	unused_isr,					// 44 --

  347. 	can0_message_isr,				// 45 CAN OR'ed Message buffer (0-15)

  348. 	can0_bus_off_isr,				// 46 CAN Bus Off

  349. 	can0_error_isr,					// 47 CAN Error

  350. 	can0_tx_warn_isr,				// 48 CAN Transmit Warning

  351. 	can0_rx_warn_isr,				// 49 CAN Receive Warning

  352. 	can0_wakeup_isr,				// 50 CAN Wake Up

  353. 	i2s0_tx_isr,					// 51 I2S0 Transmit

  354. 	i2s0_rx_isr,					// 52 I2S0 Receive

  355. 	unused_isr,					// 53 --

  356. 	unused_isr,					// 54 --

  357. 	unused_isr,					// 55 --

  358. 	unused_isr,					// 56 --

  359. 	unused_isr,					// 57 --

  360. 	unused_isr,					// 58 --

  361. 	unused_isr,					// 59 --

  362. 	uart0_lon_isr,					// 60 UART0 CEA709.1-B (LON) status

  363. 	uart0_status_isr,				// 61 UART0 status

  364. 	uart0_error_isr,				// 62 UART0 error

  365. 	uart1_status_isr,				// 63 UART1 status

  366. 	uart1_error_isr,				// 64 UART1 error

  367. 	uart2_status_isr,				// 65 UART2 status

  368. 	uart2_error_isr,				// 66 UART2 error

  369. 	unused_isr,					// 67 --

  370. 	unused_isr,					// 68 --

  371. 	unused_isr,					// 69 --

  372. 	unused_isr,					// 70 --

  373. 	unused_isr,					// 71 --

  374. 	unused_isr,					// 72 --

  375. 	adc0_isr,					// 73 ADC0

  376. 	adc1_isr,					// 74 ADC1

  377. 	cmp0_isr,					// 75 CMP0

  378. 	cmp1_isr,					// 76 CMP1

  379. 	cmp2_isr,					// 77 CMP2

  380. 	ftm0_isr,					// 78 FTM0

  381. 	ftm1_isr,					// 79 FTM1

  382. 	ftm2_isr,					// 80 FTM2

  383. 	cmt_isr,					// 81 CMT

  384. 	rtc_alarm_isr,					// 82 RTC Alarm interrupt

  385. 	rtc_seconds_isr,				// 83 RTC Seconds interrupt

  386. 	pit0_isr,					// 84 PIT Channel 0

  387. 	pit1_isr,					// 85 PIT Channel 1

  388. 	pit2_isr,					// 86 PIT Channel 2

  389. 	pit3_isr,					// 87 PIT Channel 3

  390. 	pdb_isr,					// 88 PDB Programmable Delay Block

  391. 	usb_isr,					// 89 USB OTG

  392. 	usb_charge_isr,					// 90 USB Charger Detect

  393. 	unused_isr,					// 91 --

  394. 	unused_isr,					// 92 --

  395. 	unused_isr,					// 93 --

  396. 	unused_isr,					// 94 --

  397. 	unused_isr,					// 95 --

  398. 	unused_isr,					// 96 --

  399. 	dac0_isr,					// 97 DAC0

  400. 	unused_isr,					// 98 --

  401. 	tsi0_isr,					// 99 TSI0

  402. 	mcg_isr,					// 100 MCG

  403. 	lptmr_isr,					// 101 Low Power Timer

  404. 	unused_isr,					// 102 --

  405. 	porta_isr,					// 103 Pin detect (Port A)

  406. 	portb_isr,					// 104 Pin detect (Port B)

  407. 	portc_isr,					// 105 Pin detect (Port C)

  408. 	portd_isr,					// 106 Pin detect (Port D)

  409. 	porte_isr,					// 107 Pin detect (Port E)

  410. 	unused_isr,					// 108 --

  411. 	unused_isr,					// 109 --

  412. 	software_isr,					// 110 Software interrupt

  413. #elif defined(__MKL26Z64__)

  414. 	dma_ch0_isr,					// 16 DMA channel 0 transfer complete

  415. 	dma_ch1_isr,					// 17 DMA channel 1 transfer complete

  416. 	dma_ch2_isr,					// 18 DMA channel 2 transfer complete

  417. 	dma_ch3_isr,					// 19 DMA channel 3 transfer complete

  418. 	unused_isr,					// 20 --

  419. 	flash_cmd_isr,					// 21 Flash Memory Command complete

  420. 	low_voltage_isr,				// 22 Low-voltage detect/warning

  421. 	wakeup_isr,					// 23 Low Leakage Wakeup

  422. 	i2c0_isr,					// 24 I2C0

  423. 	i2c1_isr,					// 25 I2C1

  424. 	spi0_isr,					// 26 SPI0

  425. 	spi1_isr,					// 27 SPI1

  426. 	uart0_status_isr,				// 28 UART0 status & error

  427. 	uart1_status_isr,				// 29 UART1 status & error

  428. 	uart2_status_isr,				// 30 UART2 status & error

  429. 	adc0_isr,					// 31 ADC0

  430. 	cmp0_isr,					// 32 CMP0

  431. 	ftm0_isr,					// 33 FTM0

  432. 	ftm1_isr,					// 34 FTM1

  433. 	ftm2_isr,					// 35 FTM2

  434. 	rtc_alarm_isr,					// 36 RTC Alarm interrupt

  435. 	rtc_seconds_isr,				// 37 RTC Seconds interrupt

  436. 	pit_isr,					// 38 PIT Both Channels

  437. 	i2s0_isr,					// 39 I2S0 Transmit & Receive

  438. 	usb_isr,					// 40 USB OTG

  439. 	dac0_isr,					// 41 DAC0

  440. 	tsi0_isr,					// 42 TSI0

  441. 	mcg_isr,					// 43 MCG

  442. 	lptmr_isr,					// 44 Low Power Timer

  443. 	software_isr,					// 45 Software interrupt

  444. 	porta_isr,					// 46 Pin detect (Port A)

  445. 	portcd_isr,					// 47 Pin detect (Port C and D)

  446. #elif defined(__MK66FX1M0__)

  447. 	dma_ch0_isr,					// 16 DMA channel 0 transfer complete

  448. 	dma_ch1_isr,					// 17 DMA channel 1 transfer complete

  449. 	dma_ch2_isr,					// 18 DMA channel 2 transfer complete

  450. 	dma_ch3_isr,					// 19 DMA channel 3 transfer complete

  451. 	dma_ch4_isr,					// 20 DMA channel 4 transfer complete

  452. 	dma_ch5_isr,					// 21 DMA channel 5 transfer complete

  453. 	dma_ch6_isr,					// 22 DMA channel 6 transfer complete

  454. 	dma_ch7_isr,					// 23 DMA channel 7 transfer complete

  455. 	dma_ch8_isr,					// 24 DMA channel 8 transfer complete

  456. 	dma_ch9_isr,					// 25 DMA channel 9 transfer complete

  457. 	dma_ch10_isr,					// 26 DMA channel 10 transfer complete

  458. 	dma_ch11_isr,					// 27 DMA channel 11 transfer complete

  459. 	dma_ch12_isr,					// 28 DMA channel 12 transfer complete

  460. 	dma_ch13_isr,					// 29 DMA channel 13 transfer complete

  461. 	dma_ch14_isr,					// 30 DMA channel 14 transfer complete

  462. 	dma_ch15_isr,					// 31 DMA channel 15 transfer complete

  463. 	dma_error_isr,					// 32 DMA error interrupt channel

  464. 	mcm_isr,					// 33 MCM

  465. 	flash_cmd_isr,					// 34 Flash Memory Command complete

  466. 	flash_error_isr,				// 35 Flash Read collision

  467. 	low_voltage_isr,				// 36 Low-voltage detect/warning

  468. 	wakeup_isr,					// 37 Low Leakage Wakeup

  469. 	watchdog_isr,					// 38 Both EWM and WDOG interrupt

  470. 	randnum_isr,					// 39 Random Number Generator

  471. 	i2c0_isr,					// 40 I2C0

  472. 	i2c1_isr,					// 41 I2C1

  473. 	spi0_isr,					// 42 SPI0

  474. 	spi1_isr,					// 43 SPI1

  475. 	i2s0_tx_isr,					// 44 I2S0 Transmit

  476. 	i2s0_rx_isr,					// 45 I2S0 Receive

  477. 	unused_isr,					// 46 --

  478. 	uart0_status_isr,				// 47 UART0 status

  479. 	uart0_error_isr,				// 48 UART0 error

  480. 	uart1_status_isr,				// 49 UART1 status

  481. 	uart1_error_isr,				// 50 UART1 error

  482. 	uart2_status_isr,				// 51 UART2 status

  483. 	uart2_error_isr,				// 52 UART2 error

  484. 	uart3_status_isr,				// 53 UART3 status

  485. 	uart3_error_isr,				// 54 UART3 error

  486. 	adc0_isr,					// 55 ADC0

  487. 	cmp0_isr,					// 56 CMP0

  488. 	cmp1_isr,					// 57 CMP1

  489. 	ftm0_isr,					// 58 FTM0

  490. 	ftm1_isr,					// 59 FTM1

  491. 	ftm2_isr,					// 60 FTM2

  492. 	cmt_isr,					// 61 CMT

  493. 	rtc_alarm_isr,					// 62 RTC Alarm interrupt

  494. 	rtc_seconds_isr,				// 63 RTC Seconds interrupt

  495. 	pit0_isr,					// 64 PIT Channel 0

  496. 	pit1_isr,					// 65 PIT Channel 1

  497. 	pit2_isr,					// 66 PIT Channel 2

  498. 	pit3_isr,					// 67 PIT Channel 3

  499. 	pdb_isr,					// 68 PDB Programmable Delay Block

  500. 	usb_isr,					// 69 USB OTG

  501. 	usb_charge_isr,					// 70 USB Charger Detect

  502. 	unused_isr,					// 71 --

  503. 	dac0_isr,					// 72 DAC0

  504. 	mcg_isr,					// 73 MCG

  505. 	lptmr_isr,					// 74 Low Power Timer

  506. 	porta_isr,					// 75 Pin detect (Port A)

  507. 	portb_isr,					// 76 Pin detect (Port B)

  508. 	portc_isr,					// 77 Pin detect (Port C)

  509. 	portd_isr,					// 78 Pin detect (Port D)

  510. 	porte_isr,					// 79 Pin detect (Port E)

  511. 	software_isr,					// 80 Software interrupt

  512. 	spi2_isr,					// 81 SPI2

  513. 	uart4_status_isr,				// 82 UART4 status

  514. 	uart4_error_isr,				// 83 UART4 error

  515. 	unused_isr,					// 84 --

  516. 	unused_isr,					// 85 --

  517. 	cmp2_isr,					// 86 CMP2

  518. 	ftm3_isr,					// 87 FTM3

  519. 	dac1_isr,					// 88 DAC1

  520. 	adc1_isr,					// 89 ADC1

  521. 	i2c2_isr,					// 90 I2C2

  522. 	can0_message_isr,				// 91 CAN OR'ed Message buffer (0-15)

  523. 	can0_bus_off_isr,				// 92 CAN Bus Off

  524. 	can0_error_isr,					// 93 CAN Error

  525. 	can0_tx_warn_isr,				// 94 CAN Transmit Warning

  526. 	can0_rx_warn_isr,				// 95 CAN Receive Warning

  527. 	can0_wakeup_isr,				// 96 CAN Wake Up

  528. 	sdhc_isr,					// 97 SDHC

  529. 	enet_timer_isr,					// 98 Ethernet IEEE1588 Timers

  530. 	enet_tx_isr,					// 99 Ethernet Transmit

  531. 	enet_rx_isr,					// 100 Ethernet Receive

  532. 	enet_error_isr,					// 101 Ethernet Error

  533. 	lpuart0_status_isr,				// 102 ADC1

  534. 	tsi0_isr,					// 103 TSI0

  535. 	tpm1_isr,					// 104 FTM1

  536. 	tpm2_isr,					// 105 FTM2

  537. 	usbhs_phy_isr,					// 106 USB-HS Phy

  538. 	i2c3_isr,					// 107 I2C3

  539. 	cmp3_isr,					// 108 CMP3

  540. 	usbhs_isr,					// 109 USB-HS

  541. 	can1_message_isr,				// 110 CAN OR'ed Message buffer (0-15)

  542. 	can1_bus_off_isr,				// 111 CAN Bus Off

  543. 	can1_error_isr,					// 112 CAN Error

  544. 	can1_tx_warn_isr,				// 113 CAN Transmit Warning

  545. 	can1_rx_warn_isr,				// 114 CAN Receive Warning

  546. 	can1_wakeup_isr,				// 115 CAN Wake Up

  547. #endif

  548. };

  549. 

  550. 

  551. __attribute__ ((section(".flashconfig"), used))

  552. const uint8_t flashconfigbytes[16] = {

  553. 	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,

  554. 	0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF

  555. };

  556. 

  557. 

  558. // Automatically initialize the RTC.  When the build defines the compile

  559. // time, and the user has added a crystal, the RTC will automatically

  560. // begin at the time of the first upload.

  561. #ifndef TIME_T

  562. #define TIME_T 1349049600 // default 1 Oct 2012 (never used, Arduino sets this)

  563. #endif

  564. extern void *__rtc_localtime; // Arduino build process sets this

  565. extern void rtc_set(unsigned long t);

  566. 

  567. 

  568. static void startup_default_early_hook(void) {

  569. #if defined(KINETISK)

  570. 	WDOG_STCTRLH = WDOG_STCTRLH_ALLOWUPDATE;

  571. #elif defined(KINETISL)

  572. 	SIM_COPC = 0;  // disable the watchdog

  573. #endif

  574. }

  575. static void startup_default_late_hook(void) {}

  576. void startup_early_hook(void)		__attribute__ ((weak, alias("startup_default_early_hook")));

  577. void startup_late_hook(void)		__attribute__ ((weak, alias("startup_default_late_hook")));

  578. 

  579. 

  580. __attribute__ ((section(".startup"),optimize("-Os")))

  581. void ResetHandler(void)

  582. {

  583. 	uint32_t *src = &_etext;

  584. 	uint32_t *dest = &_sdata;

  585. 	unsigned int i;

  586. #if F_CPU <= 2000000

  587. 	volatile int n;

  588. #endif

  589. 	//volatile int count;

  590. 

  591. #ifdef KINETISK

  592. 	WDOG_UNLOCK = WDOG_UNLOCK_SEQ1;

  593. 	WDOG_UNLOCK = WDOG_UNLOCK_SEQ2;

  594. 	__asm__ volatile ("nop");

  595. 	__asm__ volatile ("nop");

  596. #endif

  597. 	// programs using the watchdog timer or needing to initialize hardware as

  598. 	// early as possible can implement startup_early_hook()

  599. 	startup_early_hook();

  600. 

  601. 	// enable clocks to always-used peripherals

  602. #if defined(__MK20DX128__)

  603. 	SIM_SCGC5 = 0x00043F82;		// clocks active to all GPIO

  604. 	SIM_SCGC6 = SIM_SCGC6_RTC | SIM_SCGC6_FTM0 | SIM_SCGC6_FTM1 | SIM_SCGC6_ADC0 | SIM_SCGC6_FTFL;

  605. #elif defined(__MK20DX256__)

  606. 	SIM_SCGC3 = SIM_SCGC3_ADC1 | SIM_SCGC3_FTM2;

  607. 	SIM_SCGC5 = 0x00043F82;		// clocks active to all GPIO

  608. 	SIM_SCGC6 = SIM_SCGC6_RTC | SIM_SCGC6_FTM0 | SIM_SCGC6_FTM1 | SIM_SCGC6_ADC0 | SIM_SCGC6_FTFL;

  609. #elif defined(__MK66FX1M0__)

  610. 	SIM_SCGC3 = SIM_SCGC3_ADC1 | SIM_SCGC3_FTM2 | SIM_SCGC3_FTM3;

  611. 	SIM_SCGC5 = 0x00043F82;		// clocks active to all GPIO

  612. 	SIM_SCGC6 = SIM_SCGC6_RTC | SIM_SCGC6_FTM0 | SIM_SCGC6_FTM1 | SIM_SCGC6_ADC0 | SIM_SCGC6_FTFL;

  613. 	PORTC_PCR5 = PORT_PCR_MUX(1) | PORT_PCR_DSE | PORT_PCR_SRE;

  614. 	GPIOC_PDDR |= (1<<5);

  615. 	GPIOC_PSOR = (1<<5);

  616. 	//while (1);

  617. #elif defined(__MKL26Z64__)

  618. 	SIM_SCGC4 = SIM_SCGC4_USBOTG | 0xF0000030;

  619. 	SIM_SCGC5 = 0x00003F82;		// clocks active to all GPIO

  620. 	SIM_SCGC6 = SIM_SCGC6_ADC0 | SIM_SCGC6_TPM0 | SIM_SCGC6_TPM1 | SIM_SCGC6_TPM2 | SIM_SCGC6_FTFL;

  621. #endif

  622. #if 0

  623. 	// testing only, enable ser_print

  624. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV4(1);

  625. 	MCG_C4 |= MCG_C4_DMX32 | MCG_C4_DRST_DRS(1);

  626. 	SIM_SOPT2 = SIM_SOPT2_UART0SRC(1) | SIM_SOPT2_TPMSRC(1);

  627. 	SIM_SCGC4 |= 0x00000400;

  628. 	UART0_BDH = 0;

  629. 	UART0_BDL = 26; // 115200 at 48 MHz

  630. 	UART0_C2 = UART_C2_TE;

  631. 	PORTB_PCR17 = PORT_PCR_MUX(3);

  632. #endif

  633. #ifdef KINETISK

  634. 	// if the RTC oscillator isn't enabled, get it started early

  635. 	if (!(RTC_CR & RTC_CR_OSCE)) {

  636. 		RTC_SR = 0;

  637. 		RTC_CR = RTC_CR_SC16P | RTC_CR_SC4P | RTC_CR_OSCE;

  638. 	}

  639. #endif

  640. 	// release I/O pins hold, if we woke up from VLLS mode

  641. 	if (PMC_REGSC & PMC_REGSC_ACKISO) PMC_REGSC |= PMC_REGSC_ACKISO;

  642. 

  643.     // since this is a write once register, make it visible to all F_CPU's

  644.     // so we can into other sleep modes in the future at any speed

  645. 	SMC_PMPROT = SMC_PMPROT_AVLP | SMC_PMPROT_ALLS | SMC_PMPROT_AVLLS;

  646.     

  647. 	// TODO: do this while the PLL is waiting to lock....

  648. 	while (dest < &_edata) *dest++ = *src++;

  649. 	dest = &_sbss;

  650. 	while (dest < &_ebss) *dest++ = 0;

  651. 

  652. 	// default all interrupts to medium priority level

  653. 	for (i=0; i < NVIC_NUM_INTERRUPTS + 16; i++) _VectorsRam[i] = _VectorsFlash[i];

  654. 	for (i=0; i < NVIC_NUM_INTERRUPTS; i++) NVIC_SET_PRIORITY(i, 128);

  655. 	SCB_VTOR = (uint32_t)_VectorsRam;	// use vector table in RAM

  656. 

  657. 	// hardware always starts in FEI mode

  658. 	//  C1[CLKS] bits are written to 00

  659. 	//  C1[IREFS] bit is written to 1

  660. 	//  C6[PLLS] bit is written to 0

  661. // MCG_SC[FCDIV] defaults to divide by two for internal ref clock

  662. // I tried changing MSG_SC to divide by 1, it didn't work for me

  663. #if F_CPU <= 2000000

  664.     #if defined(KINETISK)

  665.     MCG_C1 = MCG_C1_CLKS(1) | MCG_C1_IREFS;

  666.     #elif defined(KINETISL)

  667. 	// use the internal oscillator

  668. 	MCG_C1 = MCG_C1_CLKS(1) | MCG_C1_IREFS | MCG_C1_IRCLKEN;

  669.     #endif

  670. 	// wait for MCGOUT to use oscillator

  671. 	while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(1)) ;

  672. 	for (n=0; n<10; n++) ; // TODO: why do we get 2 mA extra without this delay?

  673. 	MCG_C2 = MCG_C2_IRCS;

  674. 	while (!(MCG_S & MCG_S_IRCST)) ;

  675. 	// now in FBI mode:

  676. 	//  C1[CLKS] bits are written to 01

  677. 	//  C1[IREFS] bit is written to 1

  678. 	//  C6[PLLS] is written to 0

  679. 	//  C2[LP] is written to 0

  680. 	MCG_C2 = MCG_C2_IRCS | MCG_C2_LP;

  681. 	// now in BLPI mode:

  682. 	//  C1[CLKS] bits are written to 01

  683. 	//  C1[IREFS] bit is written to 1

  684. 	//  C6[PLLS] bit is written to 0

  685. 	//  C2[LP] bit is written to 1

  686. #else

  687.     #if defined(KINETISK)

  688.     // enable capacitors for crystal

  689.     OSC0_CR = OSC_SC8P | OSC_SC2P;

  690.     #elif defined(KINETISL)

  691.     // enable capacitors for crystal

  692.     OSC0_CR = OSC_SC8P | OSC_SC2P | OSC_ERCLKEN;

  693.     #endif

  694. 	// enable osc, 8-32 MHz range, low power mode

  695. 	MCG_C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS;

  696. 	// switch to crystal as clock source, FLL input = 16 MHz / 512

  697. 	MCG_C1 =  MCG_C1_CLKS(2) | MCG_C1_FRDIV(4);

  698. 	// wait for crystal oscillator to begin

  699. 	while ((MCG_S & MCG_S_OSCINIT0) == 0) ;

  700. 	// wait for FLL to use oscillator

  701. 	while ((MCG_S & MCG_S_IREFST) != 0) ;

  702. 	// wait for MCGOUT to use oscillator

  703. 	while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2)) ;

  704. 

  705. 	// now in FBE mode

  706. 	//  C1[CLKS] bits are written to 10

  707. 	//  C1[IREFS] bit is written to 0

  708. 	//  C1[FRDIV] must be written to divide xtal to 31.25-39 kHz

  709. 	//  C6[PLLS] bit is written to 0

  710. 	//  C2[LP] is written to 0

  711.   #if F_CPU <= 16000000

  712. 	// if the crystal is fast enough, use it directly (no FLL or PLL)

  713. 	MCG_C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS | MCG_C2_LP;

  714. 	// BLPE mode:

  715. 	//   C1[CLKS] bits are written to 10

  716. 	//   C1[IREFS] bit is written to 0

  717. 	//   C2[LP] bit is written to 1

  718.   #else

  719. 	// if we need faster than the crystal, turn on the PLL

  720.    #if defined(__MK66FX1M0__)

  721.     #if F_CPU == 96000000

  722. 	MCG_C5 = MCG_C5_PRDIV0(1);

  723. 	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(8);

  724.     #else

  725.     #error "MK66FX1M0 only supports 96 MHz so far...."

  726.     #endif

  727.    #else

  728.     #if F_CPU == 72000000

  729. 	MCG_C5 = MCG_C5_PRDIV0(5);		 // config PLL input for 16 MHz Crystal / 6 = 2.667 Hz

  730.     #else

  731. 	MCG_C5 = MCG_C5_PRDIV0(3);		 // config PLL input for 16 MHz Crystal / 4 = 4 MHz

  732.     #endif

  733.     #if F_CPU == 168000000

  734. 	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(18); // config PLL for 168 MHz output

  735.     #elif F_CPU == 144000000

  736. 	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(12); // config PLL for 144 MHz output

  737.     #elif F_CPU == 120000000

  738. 	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(6); // config PLL for 120 MHz output

  739.     #elif F_CPU == 72000000

  740. 	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(3); // config PLL for 72 MHz output

  741.     #else

  742. 	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0); // config PLL for 96 MHz output

  743.     #endif

  744.    #endif

  745. 

  746. 

  747. 	// wait for PLL to start using xtal as its input

  748. 	while (!(MCG_S & MCG_S_PLLST)) ;

  749. 	// wait for PLL to lock

  750. 	while (!(MCG_S & MCG_S_LOCK0)) ;

  751. 	// now we're in PBE mode

  752.   #endif

  753. #endif

  754. 	// now program the clock dividers

  755. #if F_CPU == 168000000

  756. 	// config divisors: 168 MHz core, 56 MHz bus, 28 MHz flash, USB = 168 * 2 / 7

  757. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(2) |	 SIM_CLKDIV1_OUTDIV4(5);

  758. 	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(6) | SIM_CLKDIV2_USBFRAC;

  759. #elif F_CPU == 144000000

  760. 	// config divisors: 144 MHz core, 48 MHz bus, 28.8 MHz flash, USB = 144 / 3

  761. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(2) |	 SIM_CLKDIV1_OUTDIV4(4);

  762. 	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(2);

  763. #elif F_CPU == 120000000

  764. 	// config divisors: 120 MHz core, 60 MHz bus, 24 MHz flash, USB = 128 * 2 / 5

  765. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) |	 SIM_CLKDIV1_OUTDIV4(4);

  766. 	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC;

  767. #elif F_CPU == 96000000

  768. 	// config divisors: 96 MHz core, 48 MHz bus, 24 MHz flash, USB = 96 / 2

  769. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) |	 SIM_CLKDIV1_OUTDIV4(3);

  770. 	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1);

  771. #elif F_CPU == 72000000

  772. 	// config divisors: 72 MHz core, 36 MHz bus, 24 MHz flash, USB = 72 * 2 / 3

  773. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) |	 SIM_CLKDIV1_OUTDIV4(2);

  774. 	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC;

  775. #elif F_CPU == 48000000

  776. 	// config divisors: 48 MHz core, 48 MHz bus, 24 MHz flash, USB = 96 / 2

  777. 	#if defined(KINETISK)

  778. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV2(1) |	 SIM_CLKDIV1_OUTDIV4(3);

  779. 	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1);

  780. 	#elif defined(KINETISL)

  781. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV4(1);

  782. 	#endif

  783. #elif F_CPU == 24000000

  784. 	// config divisors: 24 MHz core, 24 MHz bus, 24 MHz flash, USB = 96 / 2

  785. 	#if defined(KINETISK)

  786. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV2(3) |	 SIM_CLKDIV1_OUTDIV4(3);

  787. 	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1);

  788. 	#elif defined(KINETISL)

  789. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV4(0);

  790. 	#endif

  791. #elif F_CPU == 16000000

  792. 	// config divisors: 16 MHz core, 16 MHz bus, 16 MHz flash

  793. #if defined(KINETISK)

  794.     SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) |	 SIM_CLKDIV1_OUTDIV4(0);

  795. #elif defined(KINETISL)

  796.     SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV4(0);

  797. #endif

  798. #elif F_CPU == 8000000

  799. 	// config divisors: 8 MHz core, 8 MHz bus, 8 MHz flash

  800. #if defined(KINETISK)

  801.     SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV2(1) |	 SIM_CLKDIV1_OUTDIV4(1);

  802. #elif defined(KINETISL)

  803.     SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV4(0);

  804. #endif

  805. #elif F_CPU == 4000000

  806.     // config divisors: 4 MHz core, 4 MHz bus, 2 MHz flash

  807.     // since we are running from external clock 16MHz

  808.     // fix outdiv too -> cpu 16/4, bus 16/4, flash 16/4

  809.     // here we can go into vlpr?

  810. 	// config divisors: 4 MHz core, 4 MHz bus, 4 MHz flash

  811. #if defined(KINETISK)

  812.     SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV2(3) |	 SIM_CLKDIV1_OUTDIV4(3);

  813. #elif defined(KINETISL)

  814.     SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV4(0);

  815. #endif

  816. #elif F_CPU == 2000000

  817.     // since we are running from the fast internal reference clock 4MHz

  818.     // but is divided down by 2 so we actually have a 2MHz, MCG_SC[FCDIV] default is 2

  819.     // fix outdiv -> cpu 2/1, bus 2/1, flash 2/2

  820. 	// config divisors: 2 MHz core, 2 MHz bus, 1 MHz flash

  821. #if defined(KINETISK)

  822.     SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) |	 SIM_CLKDIV1_OUTDIV4(1);

  823. #elif defined(KINETISL)

  824.     // config divisors: 2 MHz core, 1 MHz bus, 1 MHz flash

  825.     SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV4(1);

  826. #endif

  827. #else

  828. #error "Error, F_CPU must be 168, 144, 120, 96, 72, 48, 24, 16, 8, 4, or 2 MHz"

  829. #endif

  830. 

  831. #if F_CPU > 16000000

  832. 	// switch to PLL as clock source, FLL input = 16 MHz / 512

  833. 	MCG_C1 = MCG_C1_CLKS(0) | MCG_C1_FRDIV(4);

  834. 	// wait for PLL clock to be used

  835. 	while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(3)) ;

  836. 	// now we're in PEE mode

  837. 	// USB uses PLL clock, trace is CPU clock, CLKOUT=OSCERCLK0

  838. 	#if defined(KINETISK)

  839. 	SIM_SOPT2 = SIM_SOPT2_USBSRC | SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_TRACECLKSEL

  840. 		| SIM_SOPT2_CLKOUTSEL(6);

  841. 	#elif defined(KINETISL)

  842. 	SIM_SOPT2 = SIM_SOPT2_USBSRC | SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_CLKOUTSEL(6)

  843. 		| SIM_SOPT2_UART0SRC(1) | SIM_SOPT2_TPMSRC(1);

  844. 	#endif

  845. #else

  846.     

  847. #if F_CPU == 2000000

  848. 	SIM_SOPT2 = SIM_SOPT2_TRACECLKSEL | SIM_SOPT2_CLKOUTSEL(4) | SIM_SOPT2_UART0SRC(3);

  849. #else

  850.     SIM_SOPT2 = SIM_SOPT2_TRACECLKSEL | SIM_SOPT2_CLKOUTSEL(6) | SIM_SOPT2_UART0SRC(2);

  851. #endif

  852.     

  853. #endif

  854. 

  855. #if F_CPU <= 2000000

  856.     // since we are not going into "stop mode" i removed it

  857. 	SMC_PMCTRL = SMC_PMCTRL_RUNM(2); // VLPR mode :-)

  858. #endif

  859. 

  860. 	// initialize the SysTick counter

  861. 	SYST_RVR = (F_CPU / 1000) - 1;

  862. 	SYST_CVR = 0;

  863. 	SYST_CSR = SYST_CSR_CLKSOURCE | SYST_CSR_TICKINT | SYST_CSR_ENABLE;

  864. 	SCB_SHPR3 = 0x20200000;  // Systick = priority 32

  865. 

  866. 	//init_pins();

  867. 	__enable_irq();

  868. 

  869. 	_init_Teensyduino_internal_();

  870. 

  871. #if defined(KINETISK)

  872. 	// RTC initialization

  873. 	if (RTC_SR & RTC_SR_TIF) {

  874. 		// this code will normally run on a power-up reset

  875. 		// when VBAT has detected a power-up.  Normally our

  876. 		// compiled-in time will be stale.  Write a special

  877. 		// flag into the VBAT register file indicating the

  878. 		// RTC is set with known-stale time and should be

  879. 		// updated when fresh time is known.

  880. 		#if ARDUINO >= 10600

  881. 		rtc_set((uint32_t)&__rtc_localtime);

  882. 		#else

  883. 		rtc_set(TIME_T);

  884. 		#endif

  885. 		*(uint32_t *)0x4003E01C = 0x5A94C3A5;

  886. 	}

  887. 	if ((RCM_SRS0 & RCM_SRS0_PIN) && (*(uint32_t *)0x4003E01C == 0x5A94C3A5)) {

  888. 		// this code should run immediately after an upload

  889. 		// where the Teensy Loader causes the Mini54 to reset.

  890. 		// Our compiled-in time will be very fresh, so set

  891. 		// the RTC with this, and clear the VBAT resister file

  892. 		// data so we don't mess with the time after it's been

  893. 		// set well.

  894. 		#if ARDUINO >= 10600

  895. 		rtc_set((uint32_t)&__rtc_localtime);

  896. 		#else

  897. 		rtc_set(TIME_T);

  898. 		#endif

  899. 		*(uint32_t *)0x4003E01C = 0;

  900. 	}

  901. #endif

  902. 

  903. 	__libc_init_array();

  904. 

  905. 	startup_late_hook();

  906. 	main();

  907. 	while (1) ;

  908. }

  909. 

  910. char *__brkval = (char *)&_ebss;

  911. 

  912. void * _sbrk(int incr)

  913. {

  914. 	char *prev = __brkval;

  915. 	__brkval += incr;

  916. 	return prev;

  917. }

  918. 

  919. __attribute__((weak)) 

  920. int _read(int file, char *ptr, int len)

  921. {

  922. 	return 0;

  923. }

  924. 

  925. __attribute__((weak)) 

  926. int _close(int fd)

  927. {

  928. 	return -1;

  929. }

  930. 

  931. #include <sys/stat.h>

  932. 

  933. __attribute__((weak)) 

  934. int _fstat(int fd, struct stat *st)

  935. {

  936. 	st->st_mode = S_IFCHR;

  937. 	return 0;

  938. }

  939. 

  940. __attribute__((weak)) 

  941. int _isatty(int fd)

  942. {

  943. 	return 1;

  944. }

  945. 

  946. __attribute__((weak)) 

  947. int _lseek(int fd, long long offset, int whence)

  948. {

  949. 	return -1;

  950. }

  951. 

  952. __attribute__((weak)) 

  953. void _exit(int status)

  954. {

  955. 	while (1);

  956. }

  957. 

  958. __attribute__((weak)) 

  959. void __cxa_pure_virtual()

  960. {

  961. 	while (1);

  962. }

  963. 

  964. __attribute__((weak)) 

  965. int __cxa_guard_acquire (char *g) 

  966. {

  967. 	return !(*g);

  968. }

  969. 

  970. __attribute__((weak)) 

  971. void __cxa_guard_release(char *g)

  972. {

  973. 	*g = 1;

  974. }

  975. 

  976. int nvic_execution_priority(void)

  977. {

  978. 	int priority=256;

  979. 	uint32_t primask, faultmask, basepri, ipsr;

  980. 

  981. 	// full algorithm in ARM DDI0403D, page B1-639

  982. 	// this isn't quite complete, but hopefully good enough

  983. 	__asm__ volatile("mrs %0, faultmask\n" : "=r" (faultmask)::);

  984. 	if (faultmask) return -1;

  985. 	__asm__ volatile("mrs %0, primask\n" : "=r" (primask)::);

  986. 	if (primask) return 0;

  987. 	__asm__ volatile("mrs %0, ipsr\n" : "=r" (ipsr)::);

  988. 	if (ipsr) {

  989. 		if (ipsr < 16) priority = 0; // could be non-zero

  990. 		else priority = NVIC_GET_PRIORITY(ipsr - 16);

  991. 	}

  992. 	__asm__ volatile("mrs %0, basepri\n" : "=r" (basepri)::);

  993. 	if (basepri > 0 && basepri < priority) priority = basepri;

  994. 	return priority;

  995. }