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teensy-cores/teensy3/analog.c

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原始文件 Blame 文件歷史 

  1. /* Teensyduino Core Library

  2.  * http://www.pjrc.com/teensy/

  3.  * Copyright (c) 2017 PJRC.COM, LLC.

  4.  *

  5.  * Permission is hereby granted, free of charge, to any person obtaining

  6.  * a copy of this software and associated documentation files (the

  7.  * "Software"), to deal in the Software without restriction, including

  8.  * without limitation the rights to use, copy, modify, merge, publish,

  9.  * distribute, sublicense, and/or sell copies of the Software, and to

  10.  * permit persons to whom the Software is furnished to do so, subject to

  11.  * the following conditions:

  12.  *

  13.  * 1. The above copyright notice and this permission notice shall be

  14.  * included in all copies or substantial portions of the Software.

  15.  *

  16.  * 2. If the Software is incorporated into a build system that allows

  17.  * selection among a list of target devices, then similar target

  18.  * devices manufactured by PJRC.COM must be included in the list of

  19.  * target devices and selectable in the same manner.

  20.  *

  21.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

  22.  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

  23.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

  24.  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS

  25.  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN

  26.  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

  27.  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

  28.  * SOFTWARE.

  29.  */

  30. 

  31. #include "core_pins.h"

  32. //#include "HardwareSerial.h"

  33. 

  34. static uint8_t calibrating;

  35. static uint8_t analog_right_shift = 0;

  36. static uint8_t analog_config_bits = 10;

  37. static uint8_t analog_num_average = 4;

  38. static uint8_t analog_reference_internal = 0;

  39. 

  40. // the alternate clock is connected to OSCERCLK (16 MHz).

  41. // datasheet says ADC clock should be 2 to 12 MHz for 16 bit mode

  42. // datasheet says ADC clock should be 1 to 18 MHz for 8-12 bit mode

  43. 

  44. #if F_BUS == 120000000

  45.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(3) + ADC_CFG1_ADICLK(1) // 7.5 MHz

  46.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 15 MHz

  47.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 15 MHz

  48.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 15 MHz

  49. #elif F_BUS == 108000000

  50.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(3) + ADC_CFG1_ADICLK(1) // 7 MHz

  51.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 14 MHz

  52.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 14 MHz

  53.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 14 MHz

  54. #elif F_BUS == 96000000

  55.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 12 MHz

  56.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 12 MHz

  57.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 12 MHz

  58.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 24 MHz

  59. #elif F_BUS == 90000000

  60.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 11.25 MHz

  61.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 11.25 MHz

  62.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 11.25 MHz

  63.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 22.5 MHz

  64. #elif F_BUS == 80000000

  65.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 10 MHz

  66.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 10 MHz

  67.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 10 MHz

  68.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 20 MHz			

  69. #elif F_BUS == 72000000

  70.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 9 MHz

  71.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 18 MHz

  72.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 18 MHz

  73.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 18 MHz

  74. #elif F_BUS == 64000000

  75.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 8 MHz

  76.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 16 MHz

  77.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 16 MHz

  78.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 16 MHz

  79. #elif F_BUS == 60000000

  80.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 7.5 MHz

  81.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz

  82.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz

  83.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz

  84. #elif F_BUS == 56000000 || F_BUS == 54000000

  85.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 7 MHz

  86.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 14 MHz

  87.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 14 MHz

  88.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 14 MHz

  89. #elif F_BUS == 48000000

  90.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 12 MHz

  91.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 12 MHz

  92.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 12 MHz

  93.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 24 MHz

  94. #elif F_BUS == 40000000

  95.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 10 MHz

  96.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 10 MHz

  97.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 10 MHz

  98.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 20 MHz

  99. #elif F_BUS == 36000000

  100.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 9 MHz

  101.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 18 MHz

  102.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 18 MHz

  103.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 18 MHz

  104. #elif F_BUS == 24000000

  105.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(0) // 12 MHz

  106.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(0) // 12 MHz

  107.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(0) // 12 MHz

  108.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 24 MHz

  109. #elif F_BUS == 16000000

  110.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz

  111.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz

  112.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz

  113.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 16 MHz

  114. #elif F_BUS == 8000000

  115.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz

  116.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz

  117.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz

  118.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz

  119. #elif F_BUS == 4000000

  120.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 4 MHz

  121.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 4 MHz

  122.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 4 MHz

  123.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 4 MHz

  124. #elif F_BUS == 2000000

  125.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz

  126.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz

  127.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz

  128.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz

  129. #else

  130. #error "F_BUS must be 120, 108, 96, 90, 80, 72, 64, 60, 56, 54, 48, 40, 36, 24, 4 or 2 MHz"

  131. #endif

  132. 

  133. void analog_init(void)

  134. {

  135. 	uint32_t num;

  136. 

  137. 	#if defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MK64FX512__) || defined(__MK66FX1M0__)

  138. 	VREF_TRM = 0x60;

  139. 	VREF_SC = 0xE1;		// enable 1.2 volt ref

  140. 	#endif

  141. 

  142. 	if (analog_config_bits == 8) {

  143. 		ADC0_CFG1 = ADC_CFG1_8BIT + ADC_CFG1_MODE(0);

  144. 		ADC0_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(3);

  145. 		#ifdef HAS_KINETIS_ADC1

  146. 		ADC1_CFG1 = ADC_CFG1_8BIT + ADC_CFG1_MODE(0);

  147. 		ADC1_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(3);

  148. 		#endif

  149. 	} else if (analog_config_bits == 10) {

  150. 		ADC0_CFG1 = ADC_CFG1_10BIT + ADC_CFG1_MODE(2) + ADC_CFG1_ADLSMP;

  151. 		ADC0_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(3);

  152. 		#ifdef HAS_KINETIS_ADC1

  153. 		ADC1_CFG1 = ADC_CFG1_10BIT + ADC_CFG1_MODE(2) + ADC_CFG1_ADLSMP;

  154. 		ADC1_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(3);

  155. 		#endif

  156. 	} else if (analog_config_bits == 12) {

  157. 		ADC0_CFG1 = ADC_CFG1_12BIT + ADC_CFG1_MODE(1) + ADC_CFG1_ADLSMP;

  158. 		ADC0_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(2);

  159. 		#ifdef HAS_KINETIS_ADC1

  160. 		ADC1_CFG1 = ADC_CFG1_12BIT + ADC_CFG1_MODE(1) + ADC_CFG1_ADLSMP;

  161. 		ADC1_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(2);

  162. 		#endif

  163. 	} else {

  164. 		ADC0_CFG1 = ADC_CFG1_16BIT + ADC_CFG1_MODE(3) + ADC_CFG1_ADLSMP;

  165. 		ADC0_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(2);

  166. 		#ifdef HAS_KINETIS_ADC1

  167. 		ADC1_CFG1 = ADC_CFG1_16BIT + ADC_CFG1_MODE(3) + ADC_CFG1_ADLSMP;

  168. 		ADC1_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(2);

  169. 		#endif

  170. 	}

  171. 

  172. 	#if defined(__MK20DX128__)

  173. 	if (analog_reference_internal) {

  174. 		ADC0_SC2 = ADC_SC2_REFSEL(1); // 1.2V ref

  175. 	} else {

  176. 		ADC0_SC2 = ADC_SC2_REFSEL(0); // vcc/ext ref

  177. 	}

  178. 	#elif defined(__MK20DX256__) || defined(__MK64FX512__) || defined(__MK66FX1M0__)

  179. 	if (analog_reference_internal) {

  180. 		ADC0_SC2 = ADC_SC2_REFSEL(1); // 1.2V ref

  181. 		ADC1_SC2 = ADC_SC2_REFSEL(1); // 1.2V ref

  182. 	} else {

  183. 		ADC0_SC2 = ADC_SC2_REFSEL(0); // vcc/ext ref

  184. 		ADC1_SC2 = ADC_SC2_REFSEL(0); // vcc/ext ref

  185. 	}

  186. 	#elif defined(__MKL26Z64__)

  187. 	if (analog_reference_internal) {

  188. 		ADC0_SC2 = ADC_SC2_REFSEL(0); // external AREF

  189. 	} else {

  190. 		ADC0_SC2 = ADC_SC2_REFSEL(1); // vcc

  191. 	}

  192. 	#endif

  193. 

  194. 	num = analog_num_average;

  195. 	if (num <= 1) {

  196. 		ADC0_SC3 = ADC_SC3_CAL;  // begin cal

  197. 		#ifdef HAS_KINETIS_ADC1

  198. 		ADC1_SC3 = ADC_SC3_CAL;  // begin cal

  199. 		#endif

  200. 	} else if (num <= 4) {

  201. 		ADC0_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(0);

  202. 		#ifdef HAS_KINETIS_ADC1

  203. 		ADC1_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(0);

  204. 		#endif

  205. 	} else if (num <= 8) {

  206. 		ADC0_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(1);

  207. 		#ifdef HAS_KINETIS_ADC1

  208. 		ADC1_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(1);

  209. 		#endif

  210. 	} else if (num <= 16) {

  211. 		ADC0_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(2);

  212. 		#ifdef HAS_KINETIS_ADC1

  213. 		ADC1_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(2);

  214. 		#endif

  215. 	} else {

  216. 		ADC0_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(3);

  217. 		#ifdef HAS_KINETIS_ADC1

  218. 		ADC1_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(3);

  219. 		#endif

  220. 	}

  221. 	calibrating = 1;

  222. }

  223. 

  224. static void wait_for_cal(void)

  225. {

  226. 	uint16_t sum;

  227. 

  228. 	//serial_print("wait_for_cal\n");

  229. #if defined(HAS_KINETIS_ADC0) && defined(HAS_KINETIS_ADC1)

  230. 	while ((ADC0_SC3 & ADC_SC3_CAL) || (ADC1_SC3 & ADC_SC3_CAL)) {

  231. 		// wait

  232. 	}

  233. #elif defined(HAS_KINETIS_ADC0)

  234. 	while (ADC0_SC3 & ADC_SC3_CAL) {

  235. 		// wait

  236. 	}

  237. #endif

  238. 	__disable_irq();

  239. 	if (calibrating) {

  240. 		//serial_print("\n");

  241. 		sum = ADC0_CLPS + ADC0_CLP4 + ADC0_CLP3 + ADC0_CLP2 + ADC0_CLP1 + ADC0_CLP0;

  242. 		sum = (sum / 2) | 0x8000;

  243. 		ADC0_PG = sum;

  244. 		//serial_print("ADC0_PG = ");

  245. 		//serial_phex16(sum);

  246. 		//serial_print("\n");

  247. 		sum = ADC0_CLMS + ADC0_CLM4 + ADC0_CLM3 + ADC0_CLM2 + ADC0_CLM1 + ADC0_CLM0;

  248. 		sum = (sum / 2) | 0x8000;

  249. 		ADC0_MG = sum;

  250. 		//serial_print("ADC0_MG = ");

  251. 		//serial_phex16(sum);

  252. 		//serial_print("\n");

  253. #ifdef HAS_KINETIS_ADC1

  254. 		sum = ADC1_CLPS + ADC1_CLP4 + ADC1_CLP3 + ADC1_CLP2 + ADC1_CLP1 + ADC1_CLP0;

  255. 		sum = (sum / 2) | 0x8000;

  256. 		ADC1_PG = sum;

  257. 		sum = ADC1_CLMS + ADC1_CLM4 + ADC1_CLM3 + ADC1_CLM2 + ADC1_CLM1 + ADC1_CLM0;

  258. 		sum = (sum / 2) | 0x8000;

  259. 		ADC1_MG = sum;

  260. #endif

  261. 		calibrating = 0;

  262. 	}

  263. 	__enable_irq();

  264. }

  265. 

  266. // ADCx_SC2[REFSEL] bit selects the voltage reference sources for ADC.

  267. //   VREFH/VREFL - connected as the primary reference option

  268. //   1.2 V VREF_OUT - connected as the VALT reference option

  269. 

  270. #if defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MK64FX512__) || defined(__MK66FX1M0__)

  271. #define DEFAULT         0

  272. #define INTERNAL        2

  273. #define INTERNAL1V2     2

  274. #define INTERNAL1V1     2

  275. #define EXTERNAL        0

  276. 

  277. #elif defined(__MKL26Z64__)

  278. #define DEFAULT         0

  279. #define INTERNAL        0

  280. #define EXTERNAL        1

  281. #endif

  282. 

  283. void analogReference(uint8_t type)

  284. {

  285. 	if (type) {

  286. 		// internal reference requested

  287. 		if (!analog_reference_internal) {

  288. 			analog_reference_internal = 1;

  289. 			if (calibrating) {

  290. 				ADC0_SC3 = 0; // cancel cal

  291. #ifdef HAS_KINETIS_ADC1

  292. 				ADC1_SC3 = 0; // cancel cal

  293. #endif

  294. 			}

  295. 			analog_init();

  296. 		}

  297. 	} else {

  298. 		// vcc or external reference requested

  299. 		if (analog_reference_internal) {

  300. 			analog_reference_internal = 0;

  301. 			if (calibrating) {

  302. 				ADC0_SC3 = 0; // cancel cal

  303. #ifdef HAS_KINETIS_ADC1

  304. 				ADC1_SC3 = 0; // cancel cal

  305. #endif

  306. 			}

  307. 			analog_init();

  308. 		}

  309. 	}

  310. }

  311. 

  312. 

  313. void analogReadRes(unsigned int bits)

  314. {

  315. 	unsigned int config;

  316. 

  317. 	if (bits >= 13) {

  318. 		if (bits > 16) bits = 16;

  319. 		config = 16;

  320. 	} else if (bits >= 11) {

  321. 		config = 12;

  322. 	} else if (bits >= 9) {

  323. 		config = 10;

  324. 	} else {

  325. 		config = 8;

  326. 	}

  327. 	analog_right_shift = config - bits;

  328. 	if (config != analog_config_bits) {

  329. 		analog_config_bits = config;

  330. 		if (calibrating) {

  331. 			ADC0_SC3 = 0; // cancel cal

  332. 			#ifdef HAS_KINETIS_ADC1

  333. 			ADC1_SC3 = 0;

  334. 			#endif

  335. 		}

  336. 		analog_init();

  337. 	}

  338. }

  339. 

  340. void analogReadAveraging(unsigned int num)

  341. {

  342. 

  343. 	if (calibrating) wait_for_cal();

  344. 	if (num <= 1) {

  345. 		num = 0;

  346. 		ADC0_SC3 = 0;

  347. 	} else if (num <= 4) {

  348. 		num = 4;

  349. 		ADC0_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(0);

  350. #ifdef HAS_KINETIS_ADC1

  351. 		ADC1_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(0);

  352. #endif

  353. 	} else if (num <= 8) {

  354. 		num = 8;

  355. 		ADC0_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(1);

  356. #ifdef HAS_KINETIS_ADC1

  357. 		ADC1_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(1);

  358. #endif

  359. 	} else if (num <= 16) {

  360. 		num = 16;

  361. 		ADC0_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(2);

  362. #ifdef HAS_KINETIS_ADC1

  363. 		ADC1_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(2);

  364. #endif

  365. 	} else {

  366. 		num = 32;

  367. 		ADC0_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(3);

  368. #ifdef HAS_KINETIS_ADC1

  369. 		ADC1_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(3);

  370. #endif

  371. 	}

  372. 	analog_num_average = num;

  373. }

  374. 

  375. // The SC1A register is used for both software and hardware trigger modes of operation.

  376. 

  377. #if defined(__MK20DX128__)

  378. static const uint8_t pin2sc1a[] = {

  379. 	5, 14, 8, 9, 13, 12, 6, 7, 15, 4, 0, 19, 3, 21, // 0-13 -> A0-A13

  380. 	5, 14, 8, 9, 13, 12, 6, 7, 15, 4, // 14-23 are A0-A9

  381. 	255, 255, 255, 255, 255, 255, 255, 255, 255, 255, // 24-33 are digital only

  382. 	0, 19, 3, 21, // 34-37 are A10-A13

  383. 	26,           // 38 is temp sensor

  384. 	22,           // 39 is vref

  385. 	23            // 40 is unused analog pin

  386. };

  387. #elif defined(__MK20DX256__)

  388. static const uint8_t pin2sc1a[] = {

  389. 	5, 14, 8, 9, 13, 12, 6, 7, 15, 4, 0, 19, 3, 19+128, // 0-13 -> A0-A13

  390. 	5, 14, 8, 9, 13, 12, 6, 7, 15, 4, // 14-23 are A0-A9

  391. 	255, 255, // 24-25 are digital only

  392. 	5+192, 5+128, 4+128, 6+128, 7+128, 4+192, // 26-31 are A15-A20

  393. 	255, 255, // 32-33 are digital only

  394. 	0, 19, 3, 19+128, // 34-37 are A10-A13

  395. 	26,     // 38 is temp sensor,

  396. 	18+128, // 39 is vref

  397. 	23      // 40 is A14

  398. };

  399. #elif defined(__MKL26Z64__)

  400. static const uint8_t pin2sc1a[] = {

  401. 	5, 14, 8, 9, 13, 12, 6, 7, 15, 11, 0, 4+64, 23, // 0-12 -> A0-A12

  402. 	255, // 13 is digital only (no A13 alias)

  403. 	5, 14, 8, 9, 13, 12, 6, 7, 15, 11, 0, 4+64, 23, // 14-26 are A0-A12

  404. 	255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, // 27-37 unused

  405. 	26, // 38=temperature

  406. 	27  // 39=bandgap ref (PMC_REGSC |= PMC_REGSC_BGBE)

  407. };

  408. #elif defined(__MK64FX512__) || defined(__MK66FX1M0__)

  409. static const uint8_t pin2sc1a[] = {

  410. 	5, 14, 8, 9, 13, 12, 6, 7, 15, 4, 3, 19+128, 14+128, 15+128, // 0-13 -> A0-A13

  411. 	5, 14, 8, 9, 13, 12, 6, 7, 15, 4, // 14-23 are A0-A9

  412. 	255, 255, 255, 255, 255, 255, 255, // 24-30 are digital only

  413. 	14+128, 15+128, 17, 18, 4+128, 5+128, 6+128, 7+128, 17+128,  // 31-39 are A12-A20

  414. 	255, 255, 255, 255, 255, 255, 255, 255, 255,  // 40-48 are digital only

  415. 	10+128, 11+128, // 49-50 are A23-A24

  416. 	255, 255, 255, 255, 255, 255, 255, // 51-57 are digital only

  417. 	255, 255, 255, 255, 255, 255, // 58-63 (sd card pins) are digital only

  418. 	3, 19+128, // 64-65 are A10-A11

  419. 	23, 23+128,// 66-67 are A21-A22 (DAC pins)

  420. 	1, 1+128,  // 68-69 are A25-A26 (unused USB host port on Teensy 3.5)

  421. 	26,        // 70 is Temperature Sensor

  422. 	18+128     // 71 is Vref

  423. };

  424. #endif

  425. 

  426. 

  427. 

  428. // TODO: perhaps this should store the NVIC priority, so it works recursively?

  429. static volatile uint8_t analogReadBusyADC0 = 0;

  430. #ifdef HAS_KINETIS_ADC1

  431. static volatile uint8_t analogReadBusyADC1 = 0;

  432. #endif

  433. 

  434. int analogRead(uint8_t pin)

  435. {

  436. 	int result;

  437. 	uint8_t channel;

  438. 

  439. 	//serial_phex(pin);

  440. 	//serial_print(" ");

  441. 

  442. 	if (pin >= sizeof(pin2sc1a)) return 0;

  443. 	channel = pin2sc1a[pin];

  444. 	if (channel == 255) return 0;

  445. 

  446. 	if (calibrating) wait_for_cal();

  447. 

  448. #ifdef HAS_KINETIS_ADC1

  449. 	if (channel & 0x80) goto beginADC1;

  450. #endif

  451. 

  452. 	__disable_irq();

  453. startADC0:

  454. 	//serial_print("startADC0\n");

  455. #if defined(__MKL26Z64__)

  456. 	if (channel & 0x40) {

  457. 		ADC0_CFG2 &= ~ADC_CFG2_MUXSEL;

  458. 		channel &= 0x3F;

  459. 	} else {

  460. 		ADC0_CFG2 |= ADC_CFG2_MUXSEL;

  461. 	}

  462. #endif

  463. 	ADC0_SC1A = channel;

  464. 	analogReadBusyADC0 = 1;

  465. 	__enable_irq();

  466. 	while (1) {

  467. 		__disable_irq();

  468. 		if ((ADC0_SC1A & ADC_SC1_COCO)) {

  469. 			result = ADC0_RA;

  470. 			analogReadBusyADC0 = 0;

  471. 			__enable_irq();

  472. 			result >>= analog_right_shift;

  473. 			return result;

  474. 		}

  475. 		// detect if analogRead was used from an interrupt

  476. 		// if so, our analogRead got canceled, so it must

  477. 		// be restarted.

  478. 		if (!analogReadBusyADC0) goto startADC0;

  479. 		__enable_irq();

  480. 		yield();

  481. 	}

  482. 

  483. #ifdef HAS_KINETIS_ADC1

  484. beginADC1:

  485. 	__disable_irq();

  486. startADC1:

  487. 	//serial_print("startADC1\n");

  488. 	// ADC1_CFG2[MUXSEL] bit selects between ADCx_SEn channels a and b.

  489. 	if (channel & 0x40) {

  490. 		ADC1_CFG2 &= ~ADC_CFG2_MUXSEL;

  491. 	} else {

  492. 		ADC1_CFG2 |= ADC_CFG2_MUXSEL;

  493. 	}

  494. 	ADC1_SC1A = channel & 0x3F;

  495. 	analogReadBusyADC1 = 1;

  496. 	__enable_irq();

  497. 	while (1) {

  498. 		__disable_irq();

  499. 		if ((ADC1_SC1A & ADC_SC1_COCO)) {

  500. 			result = ADC1_RA;

  501. 			analogReadBusyADC1 = 0;

  502. 			__enable_irq();

  503. 			result >>= analog_right_shift;

  504. 			return result;

  505. 		}

  506. 		// detect if analogRead was used from an interrupt

  507. 		// if so, our analogRead got canceled, so it must

  508. 		// be restarted.

  509. 		if (!analogReadBusyADC1) goto startADC1;

  510. 		__enable_irq();

  511. 		yield();

  512. 	}

  513. #endif

  514. }

  515. 

  516. typedef int16_t __attribute__((__may_alias__)) aliased_int16_t;

  517. 

  518. void analogWriteDAC0(int val)

  519. {

  520. #if defined(__MK20DX256__) || defined(__MK64FX512__) || defined(__MK66FX1M0__)

  521. 	SIM_SCGC2 |= SIM_SCGC2_DAC0;

  522. 	if (analog_reference_internal) {

  523. 		DAC0_C0 = DAC_C0_DACEN;  // 1.2V ref is DACREF_1

  524. 	} else {

  525. 		DAC0_C0 = DAC_C0_DACEN | DAC_C0_DACRFS; // 3.3V VDDA is DACREF_2

  526. 	}

  527. 	__asm__ ("usat    %[value], #12, %[value]\n\t" : [value] "+r" (val));  // 0 <= val <= 4095

  528. 

  529. 	*(volatile aliased_int16_t *)&(DAC0_DAT0L) = val;

  530. #elif defined(__MKL26Z64__)

  531. 	SIM_SCGC6 |= SIM_SCGC6_DAC0;

  532. 	if (analog_reference_internal == 0) {

  533. 		// use 3.3V VDDA power as the reference (this is the default)

  534. 		DAC0_C0 = DAC_C0_DACEN | DAC_C0_DACRFS | DAC_C0_DACSWTRG; // 3.3V VDDA

  535. 	} else {

  536. 		// use whatever voltage is on the AREF pin

  537. 		DAC0_C0 = DAC_C0_DACEN | DAC_C0_DACSWTRG; // 3.3V VDDA

  538. 	}

  539. 	if (val < 0) val = 0;

  540. 	else if (val > 4095) val = 4095;

  541. 

  542. 	*(volatile aliased_int16_t *)&(DAC0_DAT0L) = val;

  543. #endif

  544. }

  545. 

  546. 

  547. #if defined(__MK64FX512__) || defined(__MK66FX1M0__)

  548. void analogWriteDAC1(int val)

  549. {

  550. 	SIM_SCGC2 |= SIM_SCGC2_DAC1;

  551. 	if (analog_reference_internal) {

  552. 		DAC1_C0 = DAC_C0_DACEN;  // 1.2V ref is DACREF_1

  553. 	} else {

  554. 		DAC1_C0 = DAC_C0_DACEN | DAC_C0_DACRFS; // 3.3V VDDA is DACREF_2

  555. 	}

  556. 	__asm__ ("usat    %[value], #12, %[value]\n\t" : [value] "+r" (val));  // 0 <= val <= 4095

  557. 

  558. 	*(volatile aliased_int16_t *)&(DAC1_DAT0L) = val;

  559. }

  560. #endif

  561. 

  562. 

  563. 

  564. 

  565. 

  566. 

  567. 

  568. 

  569. 

  570. 

  571. 

  572. 

  573. 

  574.